1 /** @file 2 SMM profile internal header file. 3 4 Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.<BR> 5 Copyright (c) 2020, AMD Incorporated. All rights reserved.<BR> 6 SPDX-License-Identifier: BSD-2-Clause-Patent 7 8 **/ 9 10 #ifndef _SMM_PROFILE_INTERNAL_H_ 11 #define _SMM_PROFILE_INTERNAL_H_ 12 13 #include <Protocol/SmmReadyToLock.h> 14 #include <Library/UefiRuntimeServicesTableLib.h> 15 #include <Library/DxeServicesTableLib.h> 16 #include <Library/CpuLib.h> 17 #include <Library/UefiCpuLib.h> 18 #include <IndustryStandard/Acpi.h> 19 20 #include "SmmProfileArch.h" 21 22 // 23 // Configure the SMM_PROFILE DTS region size 24 // 25 #define SMM_PROFILE_DTS_SIZE (4 * 1024 * 1024) // 4M 26 27 #define MAX_PF_PAGE_COUNT 0x2 28 29 #define PEBS_RECORD_NUMBER 0x2 30 31 #define MAX_PF_ENTRY_COUNT 10 32 33 // 34 // This MACRO just enable unit test for the profile 35 // Please disable it. 36 // 37 38 #define IA32_PF_EC_ID (1u << 4) 39 40 #define SMM_PROFILE_NAME L"SmmProfileData" 41 42 // 43 // CPU generic definition 44 // 45 #define CPUID1_EDX_XD_SUPPORT 0x100000 46 #define MSR_EFER 0xc0000080 47 #define MSR_EFER_XD 0x800 48 49 #define CPUID1_EDX_BTS_AVAILABLE 0x200000 50 51 #define DR6_SINGLE_STEP 0x4000 52 #define RFLAG_TF 0x100 53 54 #define MSR_DEBUG_CTL 0x1D9 55 #define MSR_DEBUG_CTL_LBR 0x1 56 #define MSR_DEBUG_CTL_TR 0x40 57 #define MSR_DEBUG_CTL_BTS 0x80 58 #define MSR_DEBUG_CTL_BTINT 0x100 59 #define MSR_DS_AREA 0x600 60 61 #define HEAP_GUARD_NONSTOP_MODE \ 62 ((PcdGet8 (PcdHeapGuardPropertyMask) & (BIT6|BIT3|BIT2)) > BIT6) 63 64 #define NULL_DETECTION_NONSTOP_MODE \ 65 ((PcdGet8 (PcdNullPointerDetectionPropertyMask) & (BIT6|BIT1)) > BIT6) 66 67 typedef struct { 68 EFI_PHYSICAL_ADDRESS Base; 69 EFI_PHYSICAL_ADDRESS Top; 70 } MEMORY_RANGE; 71 72 typedef struct { 73 MEMORY_RANGE Range; 74 BOOLEAN Present; 75 BOOLEAN Nx; 76 } MEMORY_PROTECTION_RANGE; 77 78 typedef struct { 79 UINT64 HeaderSize; 80 UINT64 MaxDataEntries; 81 UINT64 MaxDataSize; 82 UINT64 CurDataEntries; 83 UINT64 CurDataSize; 84 UINT64 TsegStart; 85 UINT64 TsegSize; 86 UINT64 NumSmis; 87 UINT64 NumCpus; 88 } SMM_PROFILE_HEADER; 89 90 typedef struct { 91 UINT64 SmiNum; 92 UINT64 CpuNum; 93 UINT64 ApicId; 94 UINT64 ErrorCode; 95 UINT64 Instruction; 96 UINT64 Address; 97 UINT64 SmiCmd; 98 } SMM_PROFILE_ENTRY; 99 100 extern SMM_S3_RESUME_STATE *mSmmS3ResumeState; 101 extern UINTN gSmiExceptionHandlers[]; 102 extern BOOLEAN mXdSupported; 103 X86_ASSEMBLY_PATCH_LABEL gPatchXdSupported; 104 X86_ASSEMBLY_PATCH_LABEL gPatchMsrIa32MiscEnableSupported; 105 extern UINTN *mPFEntryCount; 106 extern UINT64 (*mLastPFEntryValue)[MAX_PF_ENTRY_COUNT]; 107 extern UINT64 *(*mLastPFEntryPointer)[MAX_PF_ENTRY_COUNT]; 108 109 // 110 // Internal functions 111 // 112 113 /** 114 Update IDT table to replace page fault handler and INT 1 handler. 115 116 **/ 117 VOID 118 InitIdtr ( 119 VOID 120 ); 121 122 /** 123 Check if the memory address will be mapped by 4KB-page. 124 125 @param Address The address of Memory. 126 127 **/ 128 BOOLEAN 129 IsAddressSplit ( 130 IN EFI_PHYSICAL_ADDRESS Address 131 ); 132 133 /** 134 Check if the memory address will be mapped by 4KB-page. 135 136 @param Address The address of Memory. 137 @param Nx The flag indicates if the memory is execute-disable. 138 139 **/ 140 BOOLEAN 141 IsAddressValid ( 142 IN EFI_PHYSICAL_ADDRESS Address, 143 IN BOOLEAN *Nx 144 ); 145 146 /** 147 Page Fault handler for SMM use. 148 149 **/ 150 VOID 151 SmiDefaultPFHandler ( 152 VOID 153 ); 154 155 /** 156 Clear TF in FLAGS. 157 158 @param SystemContext A pointer to the processor context when 159 the interrupt occurred on the processor. 160 161 **/ 162 VOID 163 ClearTrapFlag ( 164 IN OUT EFI_SYSTEM_CONTEXT SystemContext 165 ); 166 167 #endif // _SMM_PROFILE_H_ 168