1 /* 2 * Copyright 2008-2010 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * Version 2 as published by the Free Software Foundation. 7 */ 8 9 #ifndef FSL_DDR_MEMCTL_H 10 #define FSL_DDR_MEMCTL_H 11 12 /* 13 * Pick a basic DDR Technology. 14 */ 15 #include <ddr_spd.h> 16 17 #define SDRAM_TYPE_DDR1 2 18 #define SDRAM_TYPE_DDR2 3 19 #define SDRAM_TYPE_LPDDR1 6 20 #define SDRAM_TYPE_DDR3 7 21 22 #define DDR_BL4 4 /* burst length 4 */ 23 #define DDR_BC4 DDR_BL4 /* burst chop for ddr3 */ 24 #define DDR_OTF 6 /* on-the-fly BC4 and BL8 */ 25 #define DDR_BL8 8 /* burst length 8 */ 26 27 #define DDR3_RTT_60_OHM 1 /* RTT_Nom = RZQ/4 */ 28 #define DDR3_RTT_120_OHM 2 /* RTT_Nom = RZQ/2 */ 29 #define DDR3_RTT_40_OHM 3 /* RTT_Nom = RZQ/6 */ 30 #define DDR3_RTT_20_OHM 4 /* RTT_Nom = RZQ/12 */ 31 #define DDR3_RTT_30_OHM 5 /* RTT_Nom = RZQ/8 */ 32 33 #if defined(CONFIG_FSL_DDR1) 34 #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (1) 35 typedef ddr1_spd_eeprom_t generic_spd_eeprom_t; 36 #ifndef CONFIG_FSL_SDRAM_TYPE 37 #define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR1 38 #endif 39 #elif defined(CONFIG_FSL_DDR2) 40 #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3) 41 typedef ddr2_spd_eeprom_t generic_spd_eeprom_t; 42 #ifndef CONFIG_FSL_SDRAM_TYPE 43 #define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR2 44 #endif 45 #elif defined(CONFIG_FSL_DDR3) 46 #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3) /* FIXME */ 47 typedef ddr3_spd_eeprom_t generic_spd_eeprom_t; 48 #ifndef CONFIG_FSL_SDRAM_TYPE 49 #define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR3 50 #endif 51 #endif /* #if defined(CONFIG_FSL_DDR1) */ 52 53 /* define bank(chip select) interleaving mode */ 54 #define FSL_DDR_CS0_CS1 0x40 55 #define FSL_DDR_CS2_CS3 0x20 56 #define FSL_DDR_CS0_CS1_AND_CS2_CS3 (FSL_DDR_CS0_CS1 | FSL_DDR_CS2_CS3) 57 #define FSL_DDR_CS0_CS1_CS2_CS3 (FSL_DDR_CS0_CS1_AND_CS2_CS3 | 0x04) 58 59 /* define memory controller interleaving mode */ 60 #define FSL_DDR_CACHE_LINE_INTERLEAVING 0x0 61 #define FSL_DDR_PAGE_INTERLEAVING 0x1 62 #define FSL_DDR_BANK_INTERLEAVING 0x2 63 #define FSL_DDR_SUPERBANK_INTERLEAVING 0x3 64 65 /* DDR_SDRAM_CFG - DDR SDRAM Control Configuration 66 */ 67 #define SDRAM_CFG_MEM_EN 0x80000000 68 #define SDRAM_CFG_SREN 0x40000000 69 #define SDRAM_CFG_ECC_EN 0x20000000 70 #define SDRAM_CFG_RD_EN 0x10000000 71 #define SDRAM_CFG_SDRAM_TYPE_DDR1 0x02000000 72 #define SDRAM_CFG_SDRAM_TYPE_DDR2 0x03000000 73 #define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000 74 #define SDRAM_CFG_SDRAM_TYPE_SHIFT 24 75 #define SDRAM_CFG_DYN_PWR 0x00200000 76 #define SDRAM_CFG_32_BE 0x00080000 77 #define SDRAM_CFG_8_BE 0x00040000 78 #define SDRAM_CFG_NCAP 0x00020000 79 #define SDRAM_CFG_2T_EN 0x00008000 80 #define SDRAM_CFG_BI 0x00000001 81 82 #if defined(CONFIG_P4080) 83 #define RD_TO_PRE_MASK 0xf 84 #define RD_TO_PRE_SHIFT 13 85 #define WR_DATA_DELAY_MASK 0xf 86 #define WR_DATA_DELAY_SHIFT 9 87 #else 88 #define RD_TO_PRE_MASK 0x7 89 #define RD_TO_PRE_SHIFT 13 90 #define WR_DATA_DELAY_MASK 0x7 91 #define WR_DATA_DELAY_SHIFT 10 92 #endif 93 94 /* Record of register values computed */ 95 typedef struct fsl_ddr_cfg_regs_s { 96 struct { 97 unsigned int bnds; 98 unsigned int config; 99 unsigned int config_2; 100 } cs[CONFIG_CHIP_SELECTS_PER_CTRL]; 101 unsigned int timing_cfg_3; 102 unsigned int timing_cfg_0; 103 unsigned int timing_cfg_1; 104 unsigned int timing_cfg_2; 105 unsigned int ddr_sdram_cfg; 106 unsigned int ddr_sdram_cfg_2; 107 unsigned int ddr_sdram_mode; 108 unsigned int ddr_sdram_mode_2; 109 unsigned int ddr_sdram_md_cntl; 110 unsigned int ddr_sdram_interval; 111 unsigned int ddr_data_init; 112 unsigned int ddr_sdram_clk_cntl; 113 unsigned int ddr_init_addr; 114 unsigned int ddr_init_ext_addr; 115 unsigned int timing_cfg_4; 116 unsigned int timing_cfg_5; 117 unsigned int ddr_zq_cntl; 118 unsigned int ddr_wrlvl_cntl; 119 unsigned int ddr_sr_cntr; 120 unsigned int ddr_sdram_rcw_1; 121 unsigned int ddr_sdram_rcw_2; 122 } fsl_ddr_cfg_regs_t; 123 124 typedef struct memctl_options_partial_s { 125 unsigned int all_DIMMs_ECC_capable; 126 unsigned int all_DIMMs_tCKmax_ps; 127 unsigned int all_DIMMs_burst_lengths_bitmask; 128 unsigned int all_DIMMs_registered; 129 unsigned int all_DIMMs_unbuffered; 130 /* unsigned int lowest_common_SPD_caslat; */ 131 unsigned int all_DIMMs_minimum_tRCD_ps; 132 } memctl_options_partial_t; 133 134 /* 135 * Generalized parameters for memory controller configuration, 136 * might be a little specific to the FSL memory controller 137 */ 138 typedef struct memctl_options_s { 139 /* 140 * Memory organization parameters 141 * 142 * if DIMM is present in the system 143 * where DIMMs are with respect to chip select 144 * where chip selects are with respect to memory boundaries 145 */ 146 unsigned int registered_dimm_en; /* use registered DIMM support */ 147 148 /* Options local to a Chip Select */ 149 struct cs_local_opts_s { 150 unsigned int auto_precharge; 151 unsigned int odt_rd_cfg; 152 unsigned int odt_wr_cfg; 153 } cs_local_opts[CONFIG_CHIP_SELECTS_PER_CTRL]; 154 155 /* Special configurations for chip select */ 156 unsigned int memctl_interleaving; 157 unsigned int memctl_interleaving_mode; 158 unsigned int ba_intlv_ctl; 159 160 /* Operational mode parameters */ 161 unsigned int ECC_mode; /* Use ECC? */ 162 /* Initialize ECC using memory controller? */ 163 unsigned int ECC_init_using_memctl; 164 unsigned int DQS_config; /* Use DQS? maybe only with DDR2? */ 165 /* SREN - self-refresh during sleep */ 166 unsigned int self_refresh_in_sleep; 167 unsigned int dynamic_power; /* DYN_PWR */ 168 /* memory data width to use (16-bit, 32-bit, 64-bit) */ 169 unsigned int data_bus_width; 170 unsigned int burst_length; /* BL4, OTF and BL8 */ 171 /* On-The-Fly Burst Chop enable */ 172 unsigned int OTF_burst_chop_en; 173 /* mirrior DIMMs for DDR3 */ 174 unsigned int mirrored_dimm; 175 176 /* Global Timing Parameters */ 177 unsigned int cas_latency_override; 178 unsigned int cas_latency_override_value; 179 unsigned int use_derated_caslat; 180 unsigned int additive_latency_override; 181 unsigned int additive_latency_override_value; 182 183 unsigned int clk_adjust; /* */ 184 unsigned int cpo_override; 185 unsigned int write_data_delay; /* DQS adjust */ 186 187 unsigned int wrlvl_override; 188 unsigned int wrlvl_sample; /* Write leveling */ 189 unsigned int wrlvl_start; 190 191 unsigned int half_strength_driver_enable; 192 unsigned int twoT_en; 193 unsigned int threeT_en; 194 unsigned int bstopre; 195 unsigned int tCKE_clock_pulse_width_ps; /* tCKE */ 196 unsigned int tFAW_window_four_activates_ps; /* tFAW -- FOUR_ACT */ 197 198 /* Rtt impedance */ 199 unsigned int rtt_override; /* rtt_override enable */ 200 unsigned int rtt_override_value; /* that is Rtt_Nom for DDR3 */ 201 unsigned int rtt_wr_override_value; /* this is Rtt_WR for DDR3 */ 202 203 /* Automatic self refresh */ 204 unsigned int auto_self_refresh_en; 205 unsigned int sr_it; 206 /* ZQ calibration */ 207 unsigned int zq_en; 208 /* Write leveling */ 209 unsigned int wrlvl_en; 210 } memctl_options_t; 211 212 extern phys_size_t fsl_ddr_sdram(void); 213 #endif 214