1 /* 2 * (C) Copyright 2002 3 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net 4 * 5 * (C) Copyright 2002 6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 7 * Marius Groeger <mgroeger@sysgo.de> 8 * 9 * Configuration settings for the PLEB 2 board. 10 * 11 * See file CREDITS for list of people who contributed to this 12 * project. 13 * 14 * This program is free software; you can redistribute it and/or 15 * modify it under the terms of the GNU General Public License as 16 * published by the Free Software Foundation; either version 2 of 17 * the License, or (at your option) any later version. 18 * 19 * This program is distributed in the hope that it will be useful, 20 * but WITHOUT ANY WARRANTY; without even the implied warranty of 21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22 * GNU General Public License for more details. 23 * 24 * You should have received a copy of the GNU General Public License 25 * along with this program; if not, write to the Free Software 26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 27 * MA 02111-1307 USA 28 */ 29 30 #ifndef __CONFIG_H 31 #define __CONFIG_H 32 33 /* 34 * High Level Configuration Options 35 * (easy to change) 36 */ 37 #define CONFIG_PXA250 1 /* This is an PXA255 CPU */ 38 #define CONFIG_PLEB2 1 /* on an PLEB2 Board */ 39 #undef CONFIG_LCD 40 #undef CONFIG_MMC 41 #define BOARD_LATE_INIT 1 42 43 #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ 44 45 /* we will never enable dcache, because we have to setup MMU first */ 46 #define CONFIG_SYS_NO_DCACHE 47 48 /* 49 * Size of malloc() pool 50 */ 51 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) 52 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ 53 54 /* 55 * Hardware drivers 56 */ 57 58 /* None - PLEB 2 doesn't have any of this. 59 #define CONFIG_NET_MULTI 60 #define CONFIG_LAN91C96 61 #define CONFIG_LAN91C96_BASE 0x0C000000 62 */ 63 64 /* 65 * select serial console configuration 66 */ 67 #define CONFIG_PXA_SERIAL 68 #define CONFIG_FFUART 1 /* we use FFUART on PLEB 2 */ 69 70 /* allow to overwrite serial and ethaddr */ 71 #define CONFIG_ENV_OVERWRITE 72 73 #define CONFIG_BAUDRATE 115200 74 75 76 /* 77 * BOOTP options 78 */ 79 #define CONFIG_BOOTP_BOOTFILESIZE 80 #define CONFIG_BOOTP_BOOTPATH 81 #define CONFIG_BOOTP_GATEWAY 82 #define CONFIG_BOOTP_HOSTNAME 83 84 85 /* 86 * Command line configuration. 87 */ 88 #include <config_cmd_default.h> 89 90 #undef CONFIG_CMD_NET 91 92 93 #define CONFIG_BOOTDELAY 3 94 #define CONFIG_ETHADDR 08:00:3e:26:0a:5b 95 #define CONFIG_NETMASK 255.255.0.0 96 #define CONFIG_IPADDR 192.168.0.21 97 #define CONFIG_SERVERIP 192.168.0.250 98 #define CONFIG_BOOTCOMMAND "bootm 40000" 99 #define CONFIG_BOOTARGS "root=/dev/mtdblock2 prompt_ramdisk=0 load_ramdisk=1 console=ttyS0,115200" 100 101 #define CONFIG_CMDLINE_TAG 102 #define CONFIG_INITRD_TAG 103 #define CONFIG_SETUP_MEMORY_TAGS 104 105 #if defined(CONFIG_CMD_KGDB) 106 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 107 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 108 #endif 109 110 /* 111 * Miscellaneous configurable options 112 */ 113 #define CONFIG_SYS_HUSH_PARSER 1 114 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 115 116 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 117 #ifdef CONFIG_SYS_HUSH_PARSER 118 #define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */ 119 #else 120 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 121 #endif 122 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 123 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 124 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 125 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 126 #define CONFIG_SYS_DEVICE_NULLDEV 1 127 128 #define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ 129 #define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ 130 131 #define CONFIG_SYS_LOAD_ADDR 0xa2000000 /* default load address */ 132 133 #define CONFIG_SYS_HZ 1000 134 #define CONFIG_SYS_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */ 135 136 /* valid baudrates */ 137 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 138 139 #ifdef CONFIG_MMC 140 #define CONFIG_PXA_MMC 141 #define CONFIG_CMD_MMC 142 #endif 143 144 /* 145 * Stack sizes 146 * 147 * The stack sizes are set up in start.S using the settings below 148 */ 149 #define CONFIG_STACKSIZE (128*1024) /* regular stack */ 150 #ifdef CONFIG_USE_IRQ 151 #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ 152 #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ 153 #endif 154 155 /* 156 * Physical Memory Map 157 */ 158 #define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */ 159 #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ 160 #define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ 161 #define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */ 162 #define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */ 163 #define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */ 164 #define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */ 165 #define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */ 166 #define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */ 167 168 #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ 169 #define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */ 170 #define PHYS_FLASH_SIZE 0x00800000 /* 4 MB */ 171 172 /* Not entirely sure about this - DS/CHC */ 173 #define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */ 174 #define PHYS_FLASH_SECT_SIZE 0x00010000 /* 64 KB sectors (x2) */ 175 176 #define CONFIG_SYS_DRAM_BASE PHYS_SDRAM_1 177 #define CONFIG_SYS_DRAM_SIZE PHYS_SDRAM_1_SIZE 178 179 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 180 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 181 182 /* 183 * GPIO settings 184 */ 185 #define CONFIG_SYS_GPSR0_VAL 0x00000000 /* Don't set anything */ 186 #define CONFIG_SYS_GPSR1_VAL 0x00000080 187 #define CONFIG_SYS_GPSR2_VAL 0x00000000 188 189 #define CONFIG_SYS_GPCR0_VAL 0x00000000 /* Don't clear anything */ 190 #define CONFIG_SYS_GPCR1_VAL 0x00000000 191 #define CONFIG_SYS_GPCR2_VAL 0x00000000 192 193 #define CONFIG_SYS_GPDR0_VAL 0x00000000 194 #define CONFIG_SYS_GPDR1_VAL 0x000007C3 195 #define CONFIG_SYS_GPDR2_VAL 0x00000000 196 197 /* Edge detect registers (these are set by the kernel) */ 198 #define CONFIG_SYS_GRER0_VAL 0x00000000 199 #define CONFIG_SYS_GRER1_VAL 0x00000000 200 #define CONFIG_SYS_GRER2_VAL 0x00000000 201 #define CONFIG_SYS_GFER0_VAL 0x00000000 202 #define CONFIG_SYS_GFER1_VAL 0x00000000 203 #define CONFIG_SYS_GFER2_VAL 0x00000000 204 205 #define CONFIG_SYS_GAFR0_L_VAL 0x00000000 206 #define CONFIG_SYS_GAFR0_U_VAL 0x00000000 207 #define CONFIG_SYS_GAFR1_L_VAL 0x00008010 /* Use FF UART Send and Receive */ 208 #define CONFIG_SYS_GAFR1_U_VAL 0x00000000 209 #define CONFIG_SYS_GAFR2_L_VAL 0x00000000 210 #define CONFIG_SYS_GAFR2_U_VAL 0x00000000 211 212 #define CONFIG_SYS_PSSR_VAL 0x20 213 #define CONFIG_SYS_CCCR_VAL 0x00000141 /* 100 MHz memory, 200 MHz CPU */ 214 #define CONFIG_SYS_CKEN_VAL 0x00000060 /* FFUART and STUART enabled */ 215 #define CONFIG_SYS_ICMR_VAL 0x00000000 /* No interrupts enabled */ 216 217 /* 218 * Memory settings 219 */ 220 #define CONFIG_SYS_MSC0_VAL 0x00007FF0 /* Not properly calculated - FIXME (DS) */ 221 #define CONFIG_SYS_MSC1_VAL 0x00000000 222 #define CONFIG_SYS_MSC2_VAL 0x00000000 223 224 #define CONFIG_SYS_MDCNFG_VAL 0x00000aC9 /* Memory timings for the SDRAM. 225 tRP=2, CL=2, tRCD=2, tRAS=5, tRC=8 */ 226 227 #define CONFIG_SYS_MDREFR_VAL 0x00403018 /* Initial setting, individual */ 228 /* bits set in lowlevel_init.S */ 229 #define CONFIG_SYS_MDMRS_VAL 0x00000000 230 231 /* 232 * PCMCIA and CF Interfaces 233 */ 234 #define CONFIG_SYS_MECR_VAL 0x00000000 /* Hangover from Lubbock. 235 Needs calculating. (DS/CHC) */ 236 #define CONFIG_SYS_MCMEM0_VAL 0x00010504 237 #define CONFIG_SYS_MCMEM1_VAL 0x00010504 238 #define CONFIG_SYS_MCATT0_VAL 0x00010504 239 #define CONFIG_SYS_MCATT1_VAL 0x00010504 240 #define CONFIG_SYS_MCIO0_VAL 0x00004715 241 #define CONFIG_SYS_MCIO1_VAL 0x00004715 242 243 /* 244 * FLASH and environment organization 245 */ 246 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 247 #define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ 248 249 /* timeout values are in ticks */ 250 /* FIXME */ 251 #define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ 252 #define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Write */ 253 254 /* Flash protection */ 255 #define CONFIG_SYS_FLASH_PROTECTION 1 256 257 /* FIXME */ 258 #define CONFIG_ENV_IS_IN_FLASH 1 259 #define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x3C000) /* Addr of Environment Sector */ 260 #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment */ 261 #define CONFIG_ENV_SECT_SIZE 0x20000 262 263 /* Option added to get around byte ordering issues in the flash driver */ 264 #define CONFIG_SYS_LITTLE_ENDIAN 1 265 266 #endif /* __CONFIG_H */ 267