1 /*
2 * linux/include/linux/mtd/nand.h
3 *
4 * Copyright (c) 2000 David Woodhouse <dwmw2@infradead.org>
5 * Steven J. Hill <sjhill@realitydiluted.com>
6 * Thomas Gleixner <tglx@linutronix.de>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Info:
13 * Contains standard defines and IDs for NAND flash devices
14 *
15 * Changelog:
16 * See git changelog.
17 */
18 #ifndef __LINUX_MTD_NAND_H
19 #define __LINUX_MTD_NAND_H
20
21 /* XXX U-BOOT XXX */
22 #if 0
23 #include <linux/wait.h>
24 #include <linux/spinlock.h>
25 #include <linux/mtd/mtd.h>
26 #endif
27
28 #include "config.h"
29
30 #include "linux/mtd/compat.h"
31 #include "linux/mtd/mtd.h"
32 #include "linux/mtd/bbm.h"
33
34
35 struct mtd_info;
36 /* Scan and identify a NAND device */
37 extern int nand_scan (struct mtd_info *mtd, int max_chips);
38 /* Separate phases of nand_scan(), allowing board driver to intervene
39 * and override command or ECC setup according to flash type */
40 extern int nand_scan_ident(struct mtd_info *mtd, int max_chips);
41 extern int nand_scan_tail(struct mtd_info *mtd);
42
43 /* Free resources held by the NAND device */
44 extern void nand_release (struct mtd_info *mtd);
45
46 /* Internal helper for board drivers which need to override command function */
47 extern void nand_wait_ready(struct mtd_info *mtd);
48
49 /* This constant declares the max. oobsize / page, which
50 * is supported now. If you add a chip with bigger oobsize/page
51 * adjust this accordingly.
52 */
53 #define NAND_MAX_OOBSIZE 218
54 #define NAND_MAX_PAGESIZE 4096
55
56 /*
57 * Constants for hardware specific CLE/ALE/NCE function
58 *
59 * These are bits which can be or'ed to set/clear multiple
60 * bits in one go.
61 */
62 /* Select the chip by setting nCE to low */
63 #define NAND_NCE 0x01
64 /* Select the command latch by setting CLE to high */
65 #define NAND_CLE 0x02
66 /* Select the address latch by setting ALE to high */
67 #define NAND_ALE 0x04
68
69 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE)
70 #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE)
71 #define NAND_CTRL_CHANGE 0x80
72
73 /*
74 * Standard NAND flash commands
75 */
76 #define NAND_CMD_READ0 0
77 #define NAND_CMD_READ1 1
78 #define NAND_CMD_RNDOUT 5
79 #define NAND_CMD_PAGEPROG 0x10
80 #define NAND_CMD_READOOB 0x50
81 #define NAND_CMD_ERASE1 0x60
82 #define NAND_CMD_STATUS 0x70
83 #define NAND_CMD_STATUS_MULTI 0x71
84 #define NAND_CMD_SEQIN 0x80
85 #define NAND_CMD_RNDIN 0x85
86 #define NAND_CMD_READID 0x90
87 #define NAND_CMD_ERASE2 0xd0
88 #define NAND_CMD_RESET 0xff
89
90 /* Extended commands for large page devices */
91 #define NAND_CMD_READSTART 0x30
92 #define NAND_CMD_RNDOUTSTART 0xE0
93 #define NAND_CMD_CACHEDPROG 0x15
94
95 /* Extended commands for AG-AND device */
96 /*
97 * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but
98 * there is no way to distinguish that from NAND_CMD_READ0
99 * until the remaining sequence of commands has been completed
100 * so add a high order bit and mask it off in the command.
101 */
102 #define NAND_CMD_DEPLETE1 0x100
103 #define NAND_CMD_DEPLETE2 0x38
104 #define NAND_CMD_STATUS_MULTI 0x71
105 #define NAND_CMD_STATUS_ERROR 0x72
106 /* multi-bank error status (banks 0-3) */
107 #define NAND_CMD_STATUS_ERROR0 0x73
108 #define NAND_CMD_STATUS_ERROR1 0x74
109 #define NAND_CMD_STATUS_ERROR2 0x75
110 #define NAND_CMD_STATUS_ERROR3 0x76
111 #define NAND_CMD_STATUS_RESET 0x7f
112 #define NAND_CMD_STATUS_CLEAR 0xff
113
114 #define NAND_CMD_NONE -1
115
116 /* Status bits */
117 #define NAND_STATUS_FAIL 0x01
118 #define NAND_STATUS_FAIL_N1 0x02
119 #define NAND_STATUS_TRUE_READY 0x20
120 #define NAND_STATUS_READY 0x40
121 #define NAND_STATUS_WP 0x80
122
123 /*
124 * Constants for ECC_MODES
125 */
126 typedef enum {
127 NAND_ECC_NONE,
128 NAND_ECC_SOFT,
129 NAND_ECC_HW,
130 NAND_ECC_HW_SYNDROME,
131 NAND_ECC_HW_OOB_FIRST,
132 } nand_ecc_modes_t;
133
134 /*
135 * Constants for Hardware ECC
136 */
137 /* Reset Hardware ECC for read */
138 #define NAND_ECC_READ 0
139 /* Reset Hardware ECC for write */
140 #define NAND_ECC_WRITE 1
141 /* Enable Hardware ECC before syndrom is read back from flash */
142 #define NAND_ECC_READSYN 2
143
144 /* Bit mask for flags passed to do_nand_read_ecc */
145 #define NAND_GET_DEVICE 0x80
146
147
148 /* Option constants for bizarre disfunctionality and real
149 * features
150 */
151 /* Chip can not auto increment pages */
152 #define NAND_NO_AUTOINCR 0x00000001
153 /* Buswitdh is 16 bit */
154 #define NAND_BUSWIDTH_16 0x00000002
155 /* Device supports partial programming without padding */
156 #define NAND_NO_PADDING 0x00000004
157 /* Chip has cache program function */
158 #define NAND_CACHEPRG 0x00000008
159 /* Chip has copy back function */
160 #define NAND_COPYBACK 0x00000010
161 /* AND Chip which has 4 banks and a confusing page / block
162 * assignment. See Renesas datasheet for further information */
163 #define NAND_IS_AND 0x00000020
164 /* Chip has a array of 4 pages which can be read without
165 * additional ready /busy waits */
166 #define NAND_4PAGE_ARRAY 0x00000040
167 /* Chip requires that BBT is periodically rewritten to prevent
168 * bits from adjacent blocks from 'leaking' in altering data.
169 * This happens with the Renesas AG-AND chips, possibly others. */
170 #define BBT_AUTO_REFRESH 0x00000080
171 /* Chip does not require ready check on read. True
172 * for all large page devices, as they do not support
173 * autoincrement.*/
174 #define NAND_NO_READRDY 0x00000100
175 /* Chip does not allow subpage writes */
176 #define NAND_NO_SUBPAGE_WRITE 0x00000200
177
178
179 /* Options valid for Samsung large page devices */
180 #define NAND_SAMSUNG_LP_OPTIONS \
181 (NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK)
182
183 /* Macros to identify the above */
184 #define NAND_CANAUTOINCR(chip) (!(chip->options & NAND_NO_AUTOINCR))
185 #define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING))
186 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
187 #define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK))
188 /* Large page NAND with SOFT_ECC should support subpage reads */
189 #define NAND_SUBPAGE_READ(chip) ((chip->ecc.mode == NAND_ECC_SOFT) \
190 && (chip->page_shift > 9))
191
192 /* Mask to zero out the chip options, which come from the id table */
193 #define NAND_CHIPOPTIONS_MSK (0x0000ffff & ~NAND_NO_AUTOINCR)
194
195 /* Non chip related options */
196 /* Use a flash based bad block table. This option is passed to the
197 * default bad block table function. */
198 #define NAND_USE_FLASH_BBT 0x00010000
199 /* This option skips the bbt scan during initialization. */
200 #define NAND_SKIP_BBTSCAN 0x00020000
201 /* This option is defined if the board driver allocates its own buffers
202 (e.g. because it needs them DMA-coherent */
203 #define NAND_OWN_BUFFERS 0x00040000
204 /* Options set by nand scan */
205 /* bbt has already been read */
206 #define NAND_BBT_SCANNED 0x40000000
207 /* Nand scan has allocated controller struct */
208 #define NAND_CONTROLLER_ALLOC 0x80000000
209
210 /* Cell info constants */
211 #define NAND_CI_CHIPNR_MSK 0x03
212 #define NAND_CI_CELLTYPE_MSK 0x0C
213
214 /* Keep gcc happy */
215 struct nand_chip;
216
217 /**
218 * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices
219 * @lock: protection lock
220 * @active: the mtd device which holds the controller currently
221 * @wq: wait queue to sleep on if a NAND operation is in progress
222 * used instead of the per chip wait queue when a hw controller is available
223 */
224 struct nand_hw_control {
225 /* XXX U-BOOT XXX */
226 #if 0
227 spinlock_t lock;
228 wait_queue_head_t wq;
229 #endif
230 struct nand_chip *active;
231 };
232
233 /**
234 * struct nand_ecc_ctrl - Control structure for ecc
235 * @mode: ecc mode
236 * @steps: number of ecc steps per page
237 * @size: data bytes per ecc step
238 * @bytes: ecc bytes per step
239 * @total: total number of ecc bytes per page
240 * @prepad: padding information for syndrome based ecc generators
241 * @postpad: padding information for syndrome based ecc generators
242 * @layout: ECC layout control struct pointer
243 * @hwctl: function to control hardware ecc generator. Must only
244 * be provided if an hardware ECC is available
245 * @calculate: function for ecc calculation or readback from ecc hardware
246 * @correct: function for ecc correction, matching to ecc generator (sw/hw)
247 * @read_page_raw: function to read a raw page without ECC
248 * @write_page_raw: function to write a raw page without ECC
249 * @read_page: function to read a page according to the ecc generator requirements
250 * @write_page: function to write a page according to the ecc generator requirements
251 * @read_oob: function to read chip OOB data
252 * @write_oob: function to write chip OOB data
253 */
254 struct nand_ecc_ctrl {
255 nand_ecc_modes_t mode;
256 int steps;
257 int size;
258 int bytes;
259 int total;
260 int prepad;
261 int postpad;
262 struct nand_ecclayout *layout;
263 void (*hwctl)(struct mtd_info *mtd, int mode);
264 int (*calculate)(struct mtd_info *mtd,
265 const uint8_t *dat,
266 uint8_t *ecc_code);
267 int (*correct)(struct mtd_info *mtd, uint8_t *dat,
268 uint8_t *read_ecc,
269 uint8_t *calc_ecc);
270 int (*read_page_raw)(struct mtd_info *mtd,
271 struct nand_chip *chip,
272 uint8_t *buf, int page);
273 void (*write_page_raw)(struct mtd_info *mtd,
274 struct nand_chip *chip,
275 const uint8_t *buf);
276 int (*read_page)(struct mtd_info *mtd,
277 struct nand_chip *chip,
278 uint8_t *buf, int page);
279 int (*read_subpage)(struct mtd_info *mtd,
280 struct nand_chip *chip,
281 uint32_t offs, uint32_t len,
282 uint8_t *buf);
283 void (*write_page)(struct mtd_info *mtd,
284 struct nand_chip *chip,
285 const uint8_t *buf);
286 int (*read_oob)(struct mtd_info *mtd,
287 struct nand_chip *chip,
288 int page,
289 int sndcmd);
290 int (*write_oob)(struct mtd_info *mtd,
291 struct nand_chip *chip,
292 int page);
293 };
294
295 /**
296 * struct nand_buffers - buffer structure for read/write
297 * @ecccalc: buffer for calculated ecc
298 * @ecccode: buffer for ecc read from flash
299 * @databuf: buffer for data - dynamically sized
300 *
301 * Do not change the order of buffers. databuf and oobrbuf must be in
302 * consecutive order.
303 */
304 struct nand_buffers {
305 uint8_t ecccalc[NAND_MAX_OOBSIZE];
306 uint8_t ecccode[NAND_MAX_OOBSIZE];
307 uint8_t databuf[NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE];
308 };
309
310 /**
311 * struct nand_chip - NAND Private Flash Chip Data
312 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the flash device
313 * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the flash device
314 * @read_byte: [REPLACEABLE] read one byte from the chip
315 * @read_word: [REPLACEABLE] read one word from the chip
316 * @write_buf: [REPLACEABLE] write data from the buffer to the chip
317 * @read_buf: [REPLACEABLE] read data from the chip into the buffer
318 * @verify_buf: [REPLACEABLE] verify buffer contents against the chip data
319 * @select_chip: [REPLACEABLE] select chip nr
320 * @block_bad: [REPLACEABLE] check, if the block is bad
321 * @block_markbad: [REPLACEABLE] mark the block bad
322 * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific funtion for controlling
323 * ALE/CLE/nCE. Also used to write command and address
324 * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accesing device ready/busy line
325 * If set to NULL no access to ready/busy is available and the ready/busy information
326 * is read from the chip status register
327 * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing commands to the chip
328 * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on ready
329 * @ecc: [BOARDSPECIFIC] ecc control ctructure
330 * @buffers: buffer structure for read/write
331 * @hwcontrol: platform-specific hardware control structure
332 * @ops: oob operation operands
333 * @erase_cmd: [INTERN] erase command write function, selectable due to AND support
334 * @scan_bbt: [REPLACEABLE] function to scan bad block table
335 * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR)
336 * @wq: [INTERN] wait queue to sleep on if a NAND operation is in progress
337 * @state: [INTERN] the current state of the NAND device
338 * @oob_poi: poison value buffer
339 * @page_shift: [INTERN] number of address bits in a page (column address bits)
340 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock
341 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry
342 * @chip_shift: [INTERN] number of address bits in one chip
343 * @datbuf: [INTERN] internal buffer for one page + oob
344 * @oobbuf: [INTERN] oob buffer for one eraseblock
345 * @oobdirty: [INTERN] indicates that oob_buf must be reinitialized
346 * @data_poi: [INTERN] pointer to a data buffer
347 * @options: [BOARDSPECIFIC] various chip options. They can partly be set to inform nand_scan about
348 * special functionality. See the defines for further explanation
349 * @badblockpos: [INTERN] position of the bad block marker in the oob area
350 * @cellinfo: [INTERN] MLC/multichip data from chip ident
351 * @numchips: [INTERN] number of physical chips
352 * @chipsize: [INTERN] the size of one chip for multichip arrays
353 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1
354 * @pagebuf: [INTERN] holds the pagenumber which is currently in data_buf
355 * @subpagesize: [INTERN] holds the subpagesize
356 * @ecclayout: [REPLACEABLE] the default ecc placement scheme
357 * @bbt: [INTERN] bad block table pointer
358 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash lookup
359 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor
360 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial bad block scan
361 * @controller: [REPLACEABLE] a pointer to a hardware controller structure
362 * which is shared among multiple independend devices
363 * @priv: [OPTIONAL] pointer to private chip date
364 * @errstat: [OPTIONAL] hardware specific function to perform additional error status checks
365 * (determine if errors are correctable)
366 * @write_page: [REPLACEABLE] High-level page write function
367 */
368
369 struct nand_chip {
370 void __iomem *IO_ADDR_R;
371 void __iomem *IO_ADDR_W;
372
373 uint8_t (*read_byte)(struct mtd_info *mtd);
374 u16 (*read_word)(struct mtd_info *mtd);
375 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
376 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
377 int (*verify_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
378 void (*select_chip)(struct mtd_info *mtd, int chip);
379 int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip);
380 int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
381 void (*cmd_ctrl)(struct mtd_info *mtd, int dat,
382 unsigned int ctrl);
383 int (*dev_ready)(struct mtd_info *mtd);
384 void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, int page_addr);
385 int (*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
386 void (*erase_cmd)(struct mtd_info *mtd, int page);
387 int (*scan_bbt)(struct mtd_info *mtd);
388 int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state, int status, int page);
389 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
390 const uint8_t *buf, int page, int cached, int raw);
391
392 int chip_delay;
393 unsigned int options;
394
395 int page_shift;
396 int phys_erase_shift;
397 int bbt_erase_shift;
398 int chip_shift;
399 int numchips;
400 uint64_t chipsize;
401 int pagemask;
402 int pagebuf;
403 int subpagesize;
404 uint8_t cellinfo;
405 int badblockpos;
406
407 int state;
408
409 uint8_t *oob_poi;
410 struct nand_hw_control *controller;
411 struct nand_ecclayout *ecclayout;
412
413 struct nand_ecc_ctrl ecc;
414 struct nand_buffers *buffers;
415
416 struct nand_hw_control hwcontrol;
417
418 struct mtd_oob_ops ops;
419
420 uint8_t *bbt;
421 struct nand_bbt_descr *bbt_td;
422 struct nand_bbt_descr *bbt_md;
423
424 struct nand_bbt_descr *badblock_pattern;
425
426 void *priv;
427 };
428
429 /*
430 * NAND Flash Manufacturer ID Codes
431 */
432 #define NAND_MFR_TOSHIBA 0x98
433 #define NAND_MFR_SAMSUNG 0xec
434 #define NAND_MFR_FUJITSU 0x04
435 #define NAND_MFR_NATIONAL 0x8f
436 #define NAND_MFR_RENESAS 0x07
437 #define NAND_MFR_STMICRO 0x20
438 #define NAND_MFR_HYNIX 0xad
439 #define NAND_MFR_MICRON 0x2c
440 #define NAND_MFR_AMD 0x01
441
442 /**
443 * struct nand_flash_dev - NAND Flash Device ID Structure
444 * @name: Identify the device type
445 * @id: device ID code
446 * @pagesize: Pagesize in bytes. Either 256 or 512 or 0
447 * If the pagesize is 0, then the real pagesize
448 * and the eraseize are determined from the
449 * extended id bytes in the chip
450 * @erasesize: Size of an erase block in the flash device.
451 * @chipsize: Total chipsize in Mega Bytes
452 * @options: Bitfield to store chip relevant options
453 */
454 struct nand_flash_dev {
455 char *name;
456 int id;
457 unsigned long pagesize;
458 unsigned long chipsize;
459 unsigned long erasesize;
460 unsigned long options;
461 };
462
463 /**
464 * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
465 * @name: Manufacturer name
466 * @id: manufacturer ID code of device.
467 */
468 struct nand_manufacturers {
469 int id;
470 char * name;
471 };
472
473 extern struct nand_flash_dev nand_flash_ids[];
474 extern struct nand_manufacturers nand_manuf_ids[];
475
476 extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd);
477 extern int nand_update_bbt(struct mtd_info *mtd, loff_t offs);
478 extern int nand_default_bbt(struct mtd_info *mtd);
479 extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
480 extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
481 int allowbbt);
482 extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
483 size_t * retlen, uint8_t * buf);
484
485 /*
486 * Constants for oob configuration
487 */
488 #define NAND_SMALL_BADBLOCK_POS 5
489 #define NAND_LARGE_BADBLOCK_POS 0
490
491 /**
492 * struct platform_nand_chip - chip level device structure
493 * @nr_chips: max. number of chips to scan for
494 * @chip_offset: chip number offset
495 * @nr_partitions: number of partitions pointed to by partitions (or zero)
496 * @partitions: mtd partition list
497 * @chip_delay: R/B delay value in us
498 * @options: Option flags, e.g. 16bit buswidth
499 * @ecclayout: ecc layout info structure
500 * @part_probe_types: NULL-terminated array of probe types
501 * @priv: hardware controller specific settings
502 */
503 struct platform_nand_chip {
504 int nr_chips;
505 int chip_offset;
506 int nr_partitions;
507 struct mtd_partition *partitions;
508 struct nand_ecclayout *ecclayout;
509 int chip_delay;
510 unsigned int options;
511 const char **part_probe_types;
512 void *priv;
513 };
514
515 /**
516 * struct platform_nand_ctrl - controller level device structure
517 * @hwcontrol: platform specific hardware control structure
518 * @dev_ready: platform specific function to read ready/busy pin
519 * @select_chip: platform specific chip select function
520 * @cmd_ctrl: platform specific function for controlling
521 * ALE/CLE/nCE. Also used to write command and address
522 * @priv: private data to transport driver specific settings
523 *
524 * All fields are optional and depend on the hardware driver requirements
525 */
526 struct platform_nand_ctrl {
527 void (*hwcontrol)(struct mtd_info *mtd, int cmd);
528 int (*dev_ready)(struct mtd_info *mtd);
529 void (*select_chip)(struct mtd_info *mtd, int chip);
530 void (*cmd_ctrl)(struct mtd_info *mtd, int dat,
531 unsigned int ctrl);
532 void *priv;
533 };
534
535 /**
536 * struct platform_nand_data - container structure for platform-specific data
537 * @chip: chip level chip structure
538 * @ctrl: controller level device structure
539 */
540 struct platform_nand_data {
541 struct platform_nand_chip chip;
542 struct platform_nand_ctrl ctrl;
543 };
544
545 /* Some helpers to access the data structures */
546 static inline
get_platform_nandchip(struct mtd_info * mtd)547 struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd)
548 {
549 struct nand_chip *chip = mtd->priv;
550
551 return chip->priv;
552 }
553
554 #endif /* __LINUX_MTD_NAND_H */
555