1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2020 MediaTek Inc.
4 *
5 * Author: Weijie Gao <weijie.gao@mediatek.com>
6 */
7
8 #include <common.h>
9 #include <asm/addrspace.h>
10 #include <asm/global_data.h>
11 #include <linux/bitops.h>
12 #include <linux/delay.h>
13 #include <linux/sizes.h>
14 #include <linux/io.h>
15 #include <mach/ddr.h>
16 #include <mach/mc.h>
17 #include "mt7628.h"
18
19 DECLARE_GLOBAL_DATA_PTR;
20
21 /* DDR2 DQ_DLY */
22 #define DDR2_DQ_DLY \
23 ((0x8 << DQ1_DELAY_COARSE_TUNING_S) | \
24 (0x2 << DQ1_DELAY_FINE_TUNING_S) | \
25 (0x8 << DQ0_DELAY_COARSE_TUNING_S) | \
26 (0x2 << DQ0_DELAY_FINE_TUNING_S))
27
28 /* DDR2 DQS_DLY */
29 #define DDR2_DQS_DLY \
30 ((0x8 << DQS1_DELAY_COARSE_TUNING_S) | \
31 (0x3 << DQS1_DELAY_FINE_TUNING_S) | \
32 (0x8 << DQS0_DELAY_COARSE_TUNING_S) | \
33 (0x3 << DQS0_DELAY_FINE_TUNING_S))
34
35 const struct mc_ddr_cfg ddr1_cfgs_200mhz[] = {
36 [DRAM_8MB] = { 0x34A1EB94, 0x20262324, 0x28000033, 0x00000002, 0x00000000 },
37 [DRAM_16MB] = { 0x34A1EB94, 0x202A2324, 0x28000033, 0x00000002, 0x00000000 },
38 [DRAM_32MB] = { 0x34A1E5CA, 0x202E2324, 0x28000033, 0x00000002, 0x00000000 },
39 [DRAM_64MB] = { 0x3421E5CA, 0x20322324, 0x28000033, 0x00000002, 0x00000000 },
40 [DRAM_128MB] = { 0x241B05CA, 0x20362334, 0x28000033, 0x00000002, 0x00000000 },
41 };
42
43 const struct mc_ddr_cfg ddr1_cfgs_160mhz[] = {
44 [DRAM_8MB] = { 0x239964A1, 0x20262323, 0x00000033, 0x00000002, 0x00000000 },
45 [DRAM_16MB] = { 0x239964A1, 0x202A2323, 0x00000033, 0x00000002, 0x00000000 },
46 [DRAM_32MB] = { 0x239964A1, 0x202E2323, 0x00000033, 0x00000002, 0x00000000 },
47 [DRAM_64MB] = { 0x239984A1, 0x20322323, 0x00000033, 0x00000002, 0x00000000 },
48 [DRAM_128MB] = { 0x239AB4A1, 0x20362333, 0x00000033, 0x00000002, 0x00000000 },
49 };
50
51 const struct mc_ddr_cfg ddr2_cfgs_200mhz[] = {
52 [DRAM_32MB] = { 0x2519E2E5, 0x222E2323, 0x68000C43, 0x00000452, 0x0000000A },
53 [DRAM_64MB] = { 0x249AA2E5, 0x22322323, 0x68000C43, 0x00000452, 0x0000000A },
54 [DRAM_128MB] = { 0x249B42E5, 0x22362323, 0x68000C43, 0x00000452, 0x0000000A },
55 [DRAM_256MB] = { 0x249CE2E5, 0x223A2323, 0x68000C43, 0x00000452, 0x0000000A },
56 };
57
58 const struct mc_ddr_cfg ddr2_cfgs_160mhz[] = {
59 [DRAM_32MB] = { 0x23918250, 0x222E2322, 0x40000A43, 0x00000452, 0x00000006 },
60 [DRAM_64MB] = { 0x239A2250, 0x22322322, 0x40000A43, 0x00000452, 0x00000008 },
61 [DRAM_128MB] = { 0x2392A250, 0x22362322, 0x40000A43, 0x00000452, 0x00000008 },
62 [DRAM_256MB] = { 0x24140250, 0x223A2322, 0x40000A43, 0x00000452, 0x00000008 },
63 };
64
mt7628_memc_reset(int assert)65 static void mt7628_memc_reset(int assert)
66 {
67 void __iomem *sysc = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE);
68
69 if (assert)
70 setbits_32(sysc + SYSCTL_RSTCTL_REG, MC_RST);
71 else
72 clrbits_32(sysc + SYSCTL_RSTCTL_REG, MC_RST);
73 }
74
mt7628_ddr_pad_ldo_config(int ddr_type,int pkg_type)75 static void mt7628_ddr_pad_ldo_config(int ddr_type, int pkg_type)
76 {
77 void __iomem *rgc = ioremap_nocache(RGCTL_BASE, RGCTL_SIZE);
78 u32 ck_pad1, cmd_pad1, dq_pad0, dq_pad1, dqs_pad0, dqs_pad1;
79
80 setbits_32(rgc + RGCTL_PMU_G0_REG, PMU_CFG_EN);
81
82 if (ddr_type == DRAM_DDR1)
83 setbits_32(rgc + RGCTL_PMU_G3_REG, RG_DDRLDO_VOSEL);
84 else
85 clrbits_32(rgc + RGCTL_PMU_G3_REG, RG_DDRLDO_VOSEL);
86
87 setbits_32(rgc + RGCTL_PMU_G3_REG, NI_DDRLDO_EN);
88
89 __udelay(250 * 50);
90
91 setbits_32(rgc + RGCTL_PMU_G3_REG, NI_DDRLDO_STB);
92 setbits_32(rgc + RGCTL_PMU_G1_REG, RG_BUCK_FPWM);
93
94 ck_pad1 = readl(rgc + RGCTL_DDR_PAD_CK_G1_REG);
95 cmd_pad1 = readl(rgc + RGCTL_DDR_PAD_CMD_G1_REG);
96 dq_pad0 = readl(rgc + RGCTL_DDR_PAD_DQ_G0_REG);
97 dq_pad1 = readl(rgc + RGCTL_DDR_PAD_DQ_G1_REG);
98 dqs_pad0 = readl(rgc + RGCTL_DDR_PAD_DQS_G0_REG);
99 dqs_pad1 = readl(rgc + RGCTL_DDR_PAD_DQS_G1_REG);
100
101 ck_pad1 &= ~(DRVP_M | DRVN_M);
102 cmd_pad1 &= ~(DRVP_M | DRVN_M);
103 dq_pad0 &= ~RTT_M;
104 dq_pad1 &= ~(DRVP_M | DRVN_M);
105 dqs_pad0 &= ~RTT_M;
106 dqs_pad1 &= ~(DRVP_M | DRVN_M);
107
108 if (pkg_type == PKG_ID_KN) {
109 ck_pad1 |= (3 << DRVP_S) | (3 << DRVN_S);
110 cmd_pad1 |= (3 << DRVP_S) | (3 << DRVN_S);
111 dq_pad1 |= (3 << DRVP_S) | (3 << DRVN_S);
112 dqs_pad1 |= (3 << DRVP_S) | (3 << DRVN_S);
113 } else {
114 ck_pad1 |= (12 << DRVP_S) | (12 << DRVN_S);
115 cmd_pad1 |= (2 << DRVP_S) | (2 << DRVN_S);
116 dqs_pad1 |= (12 << DRVP_S) | (12 << DRVN_S);
117 if (ddr_type == DRAM_DDR1)
118 dq_pad1 |= (7 << DRVP_S) | (7 << DRVN_S);
119 else
120 dq_pad1 |= (4 << DRVP_S) | (4 << DRVN_S);
121 }
122
123 writel(ck_pad1, rgc + RGCTL_DDR_PAD_CK_G1_REG);
124 writel(cmd_pad1, rgc + RGCTL_DDR_PAD_CMD_G1_REG);
125 writel(dq_pad0, rgc + RGCTL_DDR_PAD_DQ_G0_REG);
126 writel(dq_pad1, rgc + RGCTL_DDR_PAD_DQ_G1_REG);
127 writel(dqs_pad0, rgc + RGCTL_DDR_PAD_DQS_G0_REG);
128 writel(dqs_pad1, rgc + RGCTL_DDR_PAD_DQS_G1_REG);
129 }
130
mt7628_ddr_init(void)131 void mt7628_ddr_init(void)
132 {
133 void __iomem *sysc;
134 int ddr_type, pkg_type, lspd;
135 struct mc_ddr_init_param param;
136
137 sysc = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE);
138 ddr_type = readl(sysc + SYSCTL_SYSCFG0_REG) & DRAM_TYPE;
139 pkg_type = !!(readl(sysc + SYSCTL_CHIP_REV_ID_REG) & PKG_ID);
140 lspd = readl(sysc + SYSCTL_CLKCFG0_REG) &
141 (CPU_PLL_FROM_BBP | CPU_PLL_FROM_XTAL);
142
143 if (pkg_type == PKG_ID_KN)
144 ddr_type = DRAM_DDR1;
145
146 mt7628_memc_reset(1);
147 __udelay(200);
148
149 mt7628_ddr_pad_ldo_config(ddr_type, pkg_type);
150
151 param.memc = ioremap_nocache(MEMCTL_BASE, MEMCTL_SIZE);
152 param.dq_dly = DDR2_DQ_DLY;
153 param.dqs_dly = DDR2_DQS_DLY;
154 param.mc_reset = mt7628_memc_reset;
155 param.memsize = 0;
156 param.bus_width = 0;
157
158 if (ddr_type == DRAM_DDR1) {
159 if (lspd)
160 param.cfgs = ddr1_cfgs_160mhz;
161 else
162 param.cfgs = ddr1_cfgs_200mhz;
163 ddr1_init(¶m);
164 } else {
165 if (lspd)
166 param.cfgs = ddr2_cfgs_160mhz;
167 else
168 param.cfgs = ddr2_cfgs_200mhz;
169 ddr2_init(¶m);
170 }
171
172 ddr_calibrate(param.memc, param.memsize, param.bus_width);
173
174 gd->ram_size = param.memsize;
175 }
176