1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2020 Marvell International Ltd. 4 * 5 * Configuration and status register (CSR) type definitions for 6 * Octeon pcieepx. 7 */ 8 9 #ifndef __CVMX_PCIEEPX_DEFS_H__ 10 #define __CVMX_PCIEEPX_DEFS_H__ 11 CVMX_PCIEEPX_CFG000(unsigned long offset)12static inline u64 CVMX_PCIEEPX_CFG000(unsigned long offset) 13 { 14 switch (cvmx_get_octeon_family()) { 15 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 16 return 0x0000030000000000ull; 17 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 18 return 0x0000030000000000ull + (offset) * 0x100000000ull; 19 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 20 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 21 return 0x0000030000000000ull + (offset) * 0x100000000ull; 22 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 23 return 0x0000030000000000ull + (offset) * 0x100000000ull; 24 25 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 26 return 0x0000030000000000ull + (offset) * 0x100000000ull; 27 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 28 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 29 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 30 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 31 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 32 return 0x0000000000000000ull; 33 } 34 return 0x0000030000000000ull; 35 } 36 CVMX_PCIEEPX_CFG001(unsigned long offset)37static inline u64 CVMX_PCIEEPX_CFG001(unsigned long offset) 38 { 39 switch (cvmx_get_octeon_family()) { 40 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 41 return 0x0000030000000004ull; 42 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 43 return 0x0000030000000004ull + (offset) * 0x100000000ull; 44 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 45 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 46 return 0x0000030000000004ull + (offset) * 0x100000000ull; 47 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 48 return 0x0000030000000004ull + (offset) * 0x100000000ull; 49 50 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 51 return 0x0000030000000004ull + (offset) * 0x100000000ull; 52 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 53 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 54 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 55 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 56 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 57 return 0x0000000000000004ull; 58 } 59 return 0x0000030000000004ull; 60 } 61 CVMX_PCIEEPX_CFG002(unsigned long offset)62static inline u64 CVMX_PCIEEPX_CFG002(unsigned long offset) 63 { 64 switch (cvmx_get_octeon_family()) { 65 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 66 return 0x0000030000000008ull; 67 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 68 return 0x0000030000000008ull + (offset) * 0x100000000ull; 69 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 70 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 71 return 0x0000030000000008ull + (offset) * 0x100000000ull; 72 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 73 return 0x0000030000000008ull + (offset) * 0x100000000ull; 74 75 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 76 return 0x0000030000000008ull + (offset) * 0x100000000ull; 77 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 78 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 79 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 80 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 81 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 82 return 0x0000000000000008ull; 83 } 84 return 0x0000030000000008ull; 85 } 86 CVMX_PCIEEPX_CFG003(unsigned long offset)87static inline u64 CVMX_PCIEEPX_CFG003(unsigned long offset) 88 { 89 switch (cvmx_get_octeon_family()) { 90 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 91 return 0x000003000000000Cull; 92 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 93 return 0x000003000000000Cull + (offset) * 0x100000000ull; 94 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 95 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 96 return 0x000003000000000Cull + (offset) * 0x100000000ull; 97 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 98 return 0x000003000000000Cull + (offset) * 0x100000000ull; 99 100 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 101 return 0x000003000000000Cull + (offset) * 0x100000000ull; 102 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 103 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 104 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 105 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 106 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 107 return 0x000000000000000Cull; 108 } 109 return 0x000003000000000Cull; 110 } 111 CVMX_PCIEEPX_CFG004(unsigned long offset)112static inline u64 CVMX_PCIEEPX_CFG004(unsigned long offset) 113 { 114 switch (cvmx_get_octeon_family()) { 115 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 116 return 0x0000030000000010ull; 117 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 118 return 0x0000030000000010ull + (offset) * 0x100000000ull; 119 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 120 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 121 return 0x0000030000000010ull + (offset) * 0x100000000ull; 122 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 123 return 0x0000030000000010ull + (offset) * 0x100000000ull; 124 125 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 126 return 0x0000030000000010ull + (offset) * 0x100000000ull; 127 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 128 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 129 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 130 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 131 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 132 return 0x0000000000000010ull; 133 } 134 return 0x0000030000000010ull; 135 } 136 CVMX_PCIEEPX_CFG004_MASK(unsigned long offset)137static inline u64 CVMX_PCIEEPX_CFG004_MASK(unsigned long offset) 138 { 139 switch (cvmx_get_octeon_family()) { 140 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 141 return 0x0000030080000010ull; 142 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 143 return 0x0000030080000010ull + (offset) * 0x100000000ull; 144 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 145 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 146 return 0x0000030080000010ull + (offset) * 0x100000000ull; 147 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 148 return 0x0000030080000010ull + (offset) * 0x100000000ull; 149 150 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 151 return 0x0000030080000010ull + (offset) * 0x100000000ull; 152 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 153 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 154 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 155 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 156 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 157 return 0x0000000080000010ull; 158 } 159 return 0x0000030080000010ull; 160 } 161 CVMX_PCIEEPX_CFG005(unsigned long offset)162static inline u64 CVMX_PCIEEPX_CFG005(unsigned long offset) 163 { 164 switch (cvmx_get_octeon_family()) { 165 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 166 return 0x0000030000000014ull; 167 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 168 return 0x0000030000000014ull + (offset) * 0x100000000ull; 169 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 170 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 171 return 0x0000030000000014ull + (offset) * 0x100000000ull; 172 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 173 return 0x0000030000000014ull + (offset) * 0x100000000ull; 174 175 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 176 return 0x0000030000000014ull + (offset) * 0x100000000ull; 177 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 178 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 179 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 180 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 181 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 182 return 0x0000000000000014ull; 183 } 184 return 0x0000030000000014ull; 185 } 186 CVMX_PCIEEPX_CFG005_MASK(unsigned long offset)187static inline u64 CVMX_PCIEEPX_CFG005_MASK(unsigned long offset) 188 { 189 switch (cvmx_get_octeon_family()) { 190 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 191 return 0x0000030080000014ull; 192 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 193 return 0x0000030080000014ull + (offset) * 0x100000000ull; 194 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 195 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 196 return 0x0000030080000014ull + (offset) * 0x100000000ull; 197 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 198 return 0x0000030080000014ull + (offset) * 0x100000000ull; 199 200 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 201 return 0x0000030080000014ull + (offset) * 0x100000000ull; 202 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 203 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 204 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 205 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 206 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 207 return 0x0000000080000014ull; 208 } 209 return 0x0000030080000014ull; 210 } 211 CVMX_PCIEEPX_CFG006(unsigned long offset)212static inline u64 CVMX_PCIEEPX_CFG006(unsigned long offset) 213 { 214 switch (cvmx_get_octeon_family()) { 215 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 216 return 0x0000030000000018ull; 217 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 218 return 0x0000030000000018ull + (offset) * 0x100000000ull; 219 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 220 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 221 return 0x0000030000000018ull + (offset) * 0x100000000ull; 222 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 223 return 0x0000030000000018ull + (offset) * 0x100000000ull; 224 225 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 226 return 0x0000030000000018ull + (offset) * 0x100000000ull; 227 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 228 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 229 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 230 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 231 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 232 return 0x0000000000000018ull; 233 } 234 return 0x0000030000000018ull; 235 } 236 CVMX_PCIEEPX_CFG006_MASK(unsigned long offset)237static inline u64 CVMX_PCIEEPX_CFG006_MASK(unsigned long offset) 238 { 239 switch (cvmx_get_octeon_family()) { 240 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 241 return 0x0000030080000018ull; 242 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 243 return 0x0000030080000018ull + (offset) * 0x100000000ull; 244 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 245 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 246 return 0x0000030080000018ull + (offset) * 0x100000000ull; 247 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 248 return 0x0000030080000018ull + (offset) * 0x100000000ull; 249 250 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 251 return 0x0000030080000018ull + (offset) * 0x100000000ull; 252 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 253 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 254 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 255 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 256 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 257 return 0x0000000080000018ull; 258 } 259 return 0x0000030080000018ull; 260 } 261 CVMX_PCIEEPX_CFG007(unsigned long offset)262static inline u64 CVMX_PCIEEPX_CFG007(unsigned long offset) 263 { 264 switch (cvmx_get_octeon_family()) { 265 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 266 return 0x000003000000001Cull; 267 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 268 return 0x000003000000001Cull + (offset) * 0x100000000ull; 269 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 270 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 271 return 0x000003000000001Cull + (offset) * 0x100000000ull; 272 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 273 return 0x000003000000001Cull + (offset) * 0x100000000ull; 274 275 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 276 return 0x000003000000001Cull + (offset) * 0x100000000ull; 277 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 278 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 279 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 280 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 281 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 282 return 0x000000000000001Cull; 283 } 284 return 0x000003000000001Cull; 285 } 286 CVMX_PCIEEPX_CFG007_MASK(unsigned long offset)287static inline u64 CVMX_PCIEEPX_CFG007_MASK(unsigned long offset) 288 { 289 switch (cvmx_get_octeon_family()) { 290 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 291 return 0x000003008000001Cull; 292 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 293 return 0x000003008000001Cull + (offset) * 0x100000000ull; 294 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 295 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 296 return 0x000003008000001Cull + (offset) * 0x100000000ull; 297 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 298 return 0x000003008000001Cull + (offset) * 0x100000000ull; 299 300 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 301 return 0x000003008000001Cull + (offset) * 0x100000000ull; 302 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 303 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 304 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 305 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 306 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 307 return 0x000000008000001Cull; 308 } 309 return 0x000003008000001Cull; 310 } 311 CVMX_PCIEEPX_CFG008(unsigned long offset)312static inline u64 CVMX_PCIEEPX_CFG008(unsigned long offset) 313 { 314 switch (cvmx_get_octeon_family()) { 315 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 316 return 0x0000030000000020ull; 317 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 318 return 0x0000030000000020ull + (offset) * 0x100000000ull; 319 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 320 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 321 return 0x0000030000000020ull + (offset) * 0x100000000ull; 322 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 323 return 0x0000030000000020ull + (offset) * 0x100000000ull; 324 325 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 326 return 0x0000030000000020ull + (offset) * 0x100000000ull; 327 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 328 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 329 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 330 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 331 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 332 return 0x0000000000000020ull; 333 } 334 return 0x0000030000000020ull; 335 } 336 CVMX_PCIEEPX_CFG008_MASK(unsigned long offset)337static inline u64 CVMX_PCIEEPX_CFG008_MASK(unsigned long offset) 338 { 339 switch (cvmx_get_octeon_family()) { 340 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 341 return 0x0000030080000020ull; 342 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 343 return 0x0000030080000020ull + (offset) * 0x100000000ull; 344 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 345 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 346 return 0x0000030080000020ull + (offset) * 0x100000000ull; 347 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 348 return 0x0000030080000020ull + (offset) * 0x100000000ull; 349 350 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 351 return 0x0000030080000020ull + (offset) * 0x100000000ull; 352 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 353 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 354 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 355 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 356 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 357 return 0x0000000080000020ull; 358 } 359 return 0x0000030080000020ull; 360 } 361 CVMX_PCIEEPX_CFG009(unsigned long offset)362static inline u64 CVMX_PCIEEPX_CFG009(unsigned long offset) 363 { 364 switch (cvmx_get_octeon_family()) { 365 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 366 return 0x0000030000000024ull; 367 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 368 return 0x0000030000000024ull + (offset) * 0x100000000ull; 369 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 370 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 371 return 0x0000030000000024ull + (offset) * 0x100000000ull; 372 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 373 return 0x0000030000000024ull + (offset) * 0x100000000ull; 374 375 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 376 return 0x0000030000000024ull + (offset) * 0x100000000ull; 377 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 378 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 379 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 380 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 381 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 382 return 0x0000000000000024ull; 383 } 384 return 0x0000030000000024ull; 385 } 386 CVMX_PCIEEPX_CFG009_MASK(unsigned long offset)387static inline u64 CVMX_PCIEEPX_CFG009_MASK(unsigned long offset) 388 { 389 switch (cvmx_get_octeon_family()) { 390 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 391 return 0x0000030080000024ull; 392 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 393 return 0x0000030080000024ull + (offset) * 0x100000000ull; 394 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 395 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 396 return 0x0000030080000024ull + (offset) * 0x100000000ull; 397 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 398 return 0x0000030080000024ull + (offset) * 0x100000000ull; 399 400 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 401 return 0x0000030080000024ull + (offset) * 0x100000000ull; 402 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 403 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 404 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 405 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 406 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 407 return 0x0000000080000024ull; 408 } 409 return 0x0000030080000024ull; 410 } 411 CVMX_PCIEEPX_CFG010(unsigned long offset)412static inline u64 CVMX_PCIEEPX_CFG010(unsigned long offset) 413 { 414 switch (cvmx_get_octeon_family()) { 415 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 416 return 0x0000030000000028ull; 417 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 418 return 0x0000030000000028ull + (offset) * 0x100000000ull; 419 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 420 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 421 return 0x0000030000000028ull + (offset) * 0x100000000ull; 422 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 423 return 0x0000030000000028ull + (offset) * 0x100000000ull; 424 425 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 426 return 0x0000030000000028ull + (offset) * 0x100000000ull; 427 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 428 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 429 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 430 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 431 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 432 return 0x0000000000000028ull; 433 } 434 return 0x0000030000000028ull; 435 } 436 CVMX_PCIEEPX_CFG011(unsigned long offset)437static inline u64 CVMX_PCIEEPX_CFG011(unsigned long offset) 438 { 439 switch (cvmx_get_octeon_family()) { 440 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 441 return 0x000003000000002Cull; 442 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 443 return 0x000003000000002Cull + (offset) * 0x100000000ull; 444 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 445 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 446 return 0x000003000000002Cull + (offset) * 0x100000000ull; 447 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 448 return 0x000003000000002Cull + (offset) * 0x100000000ull; 449 450 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 451 return 0x000003000000002Cull + (offset) * 0x100000000ull; 452 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 453 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 454 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 455 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 456 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 457 return 0x000000000000002Cull; 458 } 459 return 0x000003000000002Cull; 460 } 461 CVMX_PCIEEPX_CFG012(unsigned long offset)462static inline u64 CVMX_PCIEEPX_CFG012(unsigned long offset) 463 { 464 switch (cvmx_get_octeon_family()) { 465 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 466 return 0x0000030000000030ull; 467 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 468 return 0x0000030000000030ull + (offset) * 0x100000000ull; 469 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 470 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 471 return 0x0000030000000030ull + (offset) * 0x100000000ull; 472 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 473 return 0x0000030000000030ull + (offset) * 0x100000000ull; 474 475 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 476 return 0x0000030000000030ull + (offset) * 0x100000000ull; 477 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 478 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 479 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 480 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 481 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 482 return 0x0000000000000030ull; 483 } 484 return 0x0000030000000030ull; 485 } 486 CVMX_PCIEEPX_CFG012_MASK(unsigned long offset)487static inline u64 CVMX_PCIEEPX_CFG012_MASK(unsigned long offset) 488 { 489 switch (cvmx_get_octeon_family()) { 490 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 491 return 0x0000030080000030ull; 492 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 493 return 0x0000030080000030ull + (offset) * 0x100000000ull; 494 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 495 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 496 return 0x0000030080000030ull + (offset) * 0x100000000ull; 497 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 498 return 0x0000030080000030ull + (offset) * 0x100000000ull; 499 500 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 501 return 0x0000030080000030ull + (offset) * 0x100000000ull; 502 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 503 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 504 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 505 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 506 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 507 return 0x0000000080000030ull; 508 } 509 return 0x0000030080000030ull; 510 } 511 CVMX_PCIEEPX_CFG013(unsigned long offset)512static inline u64 CVMX_PCIEEPX_CFG013(unsigned long offset) 513 { 514 switch (cvmx_get_octeon_family()) { 515 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 516 return 0x0000030000000034ull; 517 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 518 return 0x0000030000000034ull + (offset) * 0x100000000ull; 519 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 520 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 521 return 0x0000030000000034ull + (offset) * 0x100000000ull; 522 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 523 return 0x0000030000000034ull + (offset) * 0x100000000ull; 524 525 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 526 return 0x0000030000000034ull + (offset) * 0x100000000ull; 527 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 528 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 529 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 530 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 531 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 532 return 0x0000000000000034ull; 533 } 534 return 0x0000030000000034ull; 535 } 536 CVMX_PCIEEPX_CFG015(unsigned long offset)537static inline u64 CVMX_PCIEEPX_CFG015(unsigned long offset) 538 { 539 switch (cvmx_get_octeon_family()) { 540 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 541 return 0x000003000000003Cull; 542 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 543 return 0x000003000000003Cull + (offset) * 0x100000000ull; 544 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 545 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 546 return 0x000003000000003Cull + (offset) * 0x100000000ull; 547 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 548 return 0x000003000000003Cull + (offset) * 0x100000000ull; 549 550 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 551 return 0x000003000000003Cull + (offset) * 0x100000000ull; 552 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 553 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 554 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 555 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 556 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 557 return 0x000000000000003Cull; 558 } 559 return 0x000003000000003Cull; 560 } 561 CVMX_PCIEEPX_CFG016(unsigned long offset)562static inline u64 CVMX_PCIEEPX_CFG016(unsigned long offset) 563 { 564 switch (cvmx_get_octeon_family()) { 565 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 566 return 0x0000030000000040ull; 567 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 568 return 0x0000030000000040ull + (offset) * 0x100000000ull; 569 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 570 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 571 return 0x0000030000000040ull + (offset) * 0x100000000ull; 572 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 573 return 0x0000030000000040ull + (offset) * 0x100000000ull; 574 575 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 576 return 0x0000030000000040ull + (offset) * 0x100000000ull; 577 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 578 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 579 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 580 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 581 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 582 return 0x0000000000000040ull; 583 } 584 return 0x0000030000000040ull; 585 } 586 CVMX_PCIEEPX_CFG017(unsigned long offset)587static inline u64 CVMX_PCIEEPX_CFG017(unsigned long offset) 588 { 589 switch (cvmx_get_octeon_family()) { 590 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 591 return 0x0000030000000044ull; 592 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 593 return 0x0000030000000044ull + (offset) * 0x100000000ull; 594 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 595 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 596 return 0x0000030000000044ull + (offset) * 0x100000000ull; 597 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 598 return 0x0000030000000044ull + (offset) * 0x100000000ull; 599 600 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 601 return 0x0000030000000044ull + (offset) * 0x100000000ull; 602 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 603 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 604 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 605 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 606 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 607 return 0x0000000000000044ull; 608 } 609 return 0x0000030000000044ull; 610 } 611 CVMX_PCIEEPX_CFG020(unsigned long offset)612static inline u64 CVMX_PCIEEPX_CFG020(unsigned long offset) 613 { 614 switch (cvmx_get_octeon_family()) { 615 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 616 return 0x0000030000000050ull; 617 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 618 return 0x0000030000000050ull + (offset) * 0x100000000ull; 619 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 620 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 621 return 0x0000030000000050ull + (offset) * 0x100000000ull; 622 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 623 return 0x0000030000000050ull + (offset) * 0x100000000ull; 624 625 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 626 return 0x0000030000000050ull + (offset) * 0x100000000ull; 627 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 628 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 629 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 630 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 631 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 632 return 0x0000000000000050ull; 633 } 634 return 0x0000030000000050ull; 635 } 636 CVMX_PCIEEPX_CFG021(unsigned long offset)637static inline u64 CVMX_PCIEEPX_CFG021(unsigned long offset) 638 { 639 switch (cvmx_get_octeon_family()) { 640 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 641 return 0x0000030000000054ull; 642 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 643 return 0x0000030000000054ull + (offset) * 0x100000000ull; 644 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 645 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 646 return 0x0000030000000054ull + (offset) * 0x100000000ull; 647 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 648 return 0x0000030000000054ull + (offset) * 0x100000000ull; 649 650 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 651 return 0x0000030000000054ull + (offset) * 0x100000000ull; 652 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 653 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 654 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 655 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 656 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 657 return 0x0000000000000054ull; 658 } 659 return 0x0000030000000054ull; 660 } 661 CVMX_PCIEEPX_CFG022(unsigned long offset)662static inline u64 CVMX_PCIEEPX_CFG022(unsigned long offset) 663 { 664 switch (cvmx_get_octeon_family()) { 665 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 666 return 0x0000030000000058ull; 667 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 668 return 0x0000030000000058ull + (offset) * 0x100000000ull; 669 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 670 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 671 return 0x0000030000000058ull + (offset) * 0x100000000ull; 672 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 673 return 0x0000030000000058ull + (offset) * 0x100000000ull; 674 675 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 676 return 0x0000030000000058ull + (offset) * 0x100000000ull; 677 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 678 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 679 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 680 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 681 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 682 return 0x0000000000000058ull; 683 } 684 return 0x0000030000000058ull; 685 } 686 CVMX_PCIEEPX_CFG023(unsigned long offset)687static inline u64 CVMX_PCIEEPX_CFG023(unsigned long offset) 688 { 689 switch (cvmx_get_octeon_family()) { 690 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 691 return 0x000003000000005Cull; 692 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 693 return 0x000003000000005Cull + (offset) * 0x100000000ull; 694 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 695 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 696 return 0x000003000000005Cull + (offset) * 0x100000000ull; 697 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 698 return 0x000003000000005Cull + (offset) * 0x100000000ull; 699 700 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 701 return 0x000003000000005Cull + (offset) * 0x100000000ull; 702 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 703 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 704 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 705 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 706 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 707 return 0x000000000000005Cull; 708 } 709 return 0x000003000000005Cull; 710 } 711 CVMX_PCIEEPX_CFG024(unsigned long offset)712static inline u64 CVMX_PCIEEPX_CFG024(unsigned long offset) 713 { 714 switch (cvmx_get_octeon_family()) { 715 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 716 return 0x0000030000000060ull; 717 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 718 return 0x0000030000000060ull + (offset) * 0x100000000ull; 719 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 720 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 721 return 0x0000030000000060ull + (offset) * 0x100000000ull; 722 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 723 return 0x0000030000000060ull + (offset) * 0x100000000ull; 724 725 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 726 return 0x0000030000000060ull + (offset) * 0x100000000ull; 727 } 728 return 0x0000030000000060ull; 729 } 730 CVMX_PCIEEPX_CFG025(unsigned long offset)731static inline u64 CVMX_PCIEEPX_CFG025(unsigned long offset) 732 { 733 switch (cvmx_get_octeon_family()) { 734 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 735 return 0x0000030000000064ull; 736 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 737 return 0x0000030000000064ull + (offset) * 0x100000000ull; 738 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 739 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 740 return 0x0000030000000064ull + (offset) * 0x100000000ull; 741 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 742 return 0x0000030000000064ull + (offset) * 0x100000000ull; 743 744 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 745 return 0x0000030000000064ull + (offset) * 0x100000000ull; 746 } 747 return 0x0000030000000064ull; 748 } 749 CVMX_PCIEEPX_CFG028(unsigned long offset)750static inline u64 CVMX_PCIEEPX_CFG028(unsigned long offset) 751 { 752 switch (cvmx_get_octeon_family()) { 753 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 754 return 0x0000030000000070ull; 755 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 756 return 0x0000030000000070ull + (offset) * 0x100000000ull; 757 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 758 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 759 return 0x0000030000000070ull + (offset) * 0x100000000ull; 760 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 761 return 0x0000030000000070ull + (offset) * 0x100000000ull; 762 763 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 764 return 0x0000030000000070ull + (offset) * 0x100000000ull; 765 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 766 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 767 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 768 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 769 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 770 return 0x0000000000000070ull; 771 } 772 return 0x0000030000000070ull; 773 } 774 CVMX_PCIEEPX_CFG029(unsigned long offset)775static inline u64 CVMX_PCIEEPX_CFG029(unsigned long offset) 776 { 777 switch (cvmx_get_octeon_family()) { 778 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 779 return 0x0000030000000074ull; 780 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 781 return 0x0000030000000074ull + (offset) * 0x100000000ull; 782 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 783 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 784 return 0x0000030000000074ull + (offset) * 0x100000000ull; 785 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 786 return 0x0000030000000074ull + (offset) * 0x100000000ull; 787 788 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 789 return 0x0000030000000074ull + (offset) * 0x100000000ull; 790 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 791 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 792 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 793 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 794 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 795 return 0x0000000000000074ull; 796 } 797 return 0x0000030000000074ull; 798 } 799 CVMX_PCIEEPX_CFG030(unsigned long offset)800static inline u64 CVMX_PCIEEPX_CFG030(unsigned long offset) 801 { 802 switch (cvmx_get_octeon_family()) { 803 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 804 return 0x0000030000000078ull; 805 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 806 return 0x0000030000000078ull + (offset) * 0x100000000ull; 807 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 808 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 809 return 0x0000030000000078ull + (offset) * 0x100000000ull; 810 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 811 return 0x0000030000000078ull + (offset) * 0x100000000ull; 812 813 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 814 return 0x0000030000000078ull + (offset) * 0x100000000ull; 815 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 816 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 817 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 818 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 819 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 820 return 0x0000000000000078ull; 821 } 822 return 0x0000030000000078ull; 823 } 824 CVMX_PCIEEPX_CFG031(unsigned long offset)825static inline u64 CVMX_PCIEEPX_CFG031(unsigned long offset) 826 { 827 switch (cvmx_get_octeon_family()) { 828 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 829 return 0x000003000000007Cull; 830 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 831 return 0x000003000000007Cull + (offset) * 0x100000000ull; 832 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 833 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 834 return 0x000003000000007Cull + (offset) * 0x100000000ull; 835 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 836 return 0x000003000000007Cull + (offset) * 0x100000000ull; 837 838 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 839 return 0x000003000000007Cull + (offset) * 0x100000000ull; 840 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 841 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 842 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 843 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 844 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 845 return 0x000000000000007Cull; 846 } 847 return 0x000003000000007Cull; 848 } 849 CVMX_PCIEEPX_CFG032(unsigned long offset)850static inline u64 CVMX_PCIEEPX_CFG032(unsigned long offset) 851 { 852 switch (cvmx_get_octeon_family()) { 853 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 854 return 0x0000030000000080ull; 855 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 856 return 0x0000030000000080ull + (offset) * 0x100000000ull; 857 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 858 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 859 return 0x0000030000000080ull + (offset) * 0x100000000ull; 860 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 861 return 0x0000030000000080ull + (offset) * 0x100000000ull; 862 863 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 864 return 0x0000030000000080ull + (offset) * 0x100000000ull; 865 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 866 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 867 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 868 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 869 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 870 return 0x0000000000000080ull; 871 } 872 return 0x0000030000000080ull; 873 } 874 875 #define CVMX_PCIEEPX_CFG033(offset) (0x0000000000000084ull) 876 #define CVMX_PCIEEPX_CFG034(offset) (0x0000000000000088ull) CVMX_PCIEEPX_CFG037(unsigned long offset)877static inline u64 CVMX_PCIEEPX_CFG037(unsigned long offset) 878 { 879 switch (cvmx_get_octeon_family()) { 880 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 881 return 0x0000030000000094ull; 882 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 883 return 0x0000030000000094ull + (offset) * 0x100000000ull; 884 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 885 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 886 return 0x0000030000000094ull + (offset) * 0x100000000ull; 887 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 888 return 0x0000030000000094ull + (offset) * 0x100000000ull; 889 890 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 891 return 0x0000030000000094ull + (offset) * 0x100000000ull; 892 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 893 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 894 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 895 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 896 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 897 return 0x0000000000000094ull; 898 } 899 return 0x0000030000000094ull; 900 } 901 CVMX_PCIEEPX_CFG038(unsigned long offset)902static inline u64 CVMX_PCIEEPX_CFG038(unsigned long offset) 903 { 904 switch (cvmx_get_octeon_family()) { 905 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 906 return 0x0000030000000098ull; 907 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 908 return 0x0000030000000098ull + (offset) * 0x100000000ull; 909 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 910 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 911 return 0x0000030000000098ull + (offset) * 0x100000000ull; 912 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 913 return 0x0000030000000098ull + (offset) * 0x100000000ull; 914 915 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 916 return 0x0000030000000098ull + (offset) * 0x100000000ull; 917 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 918 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 919 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 920 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 921 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 922 return 0x0000000000000098ull; 923 } 924 return 0x0000030000000098ull; 925 } 926 CVMX_PCIEEPX_CFG039(unsigned long offset)927static inline u64 CVMX_PCIEEPX_CFG039(unsigned long offset) 928 { 929 switch (cvmx_get_octeon_family()) { 930 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 931 return 0x000003000000009Cull; 932 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 933 return 0x000003000000009Cull + (offset) * 0x100000000ull; 934 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 935 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 936 return 0x000003000000009Cull + (offset) * 0x100000000ull; 937 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 938 return 0x000003000000009Cull + (offset) * 0x100000000ull; 939 940 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 941 return 0x000003000000009Cull + (offset) * 0x100000000ull; 942 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 943 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 944 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 945 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 946 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 947 return 0x000000000000009Cull; 948 } 949 return 0x000003000000009Cull; 950 } 951 CVMX_PCIEEPX_CFG040(unsigned long offset)952static inline u64 CVMX_PCIEEPX_CFG040(unsigned long offset) 953 { 954 switch (cvmx_get_octeon_family()) { 955 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 956 return 0x00000300000000A0ull; 957 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 958 return 0x00000300000000A0ull + (offset) * 0x100000000ull; 959 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 960 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 961 return 0x00000300000000A0ull + (offset) * 0x100000000ull; 962 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 963 return 0x00000300000000A0ull + (offset) * 0x100000000ull; 964 965 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 966 return 0x00000300000000A0ull + (offset) * 0x100000000ull; 967 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 968 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 969 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 970 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 971 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 972 return 0x00000000000000A0ull; 973 } 974 return 0x00000300000000A0ull; 975 } 976 977 #define CVMX_PCIEEPX_CFG041(offset) (0x00000000000000A4ull) 978 #define CVMX_PCIEEPX_CFG042(offset) (0x00000000000000A8ull) CVMX_PCIEEPX_CFG044(unsigned long offset)979static inline u64 CVMX_PCIEEPX_CFG044(unsigned long offset) 980 { 981 switch (cvmx_get_octeon_family()) { 982 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 983 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 984 return 0x00000300000000B0ull + (offset) * 0x100000000ull; 985 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 986 return 0x00000300000000B0ull + (offset) * 0x100000000ull; 987 988 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 989 return 0x00000300000000B0ull + (offset) * 0x100000000ull; 990 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 991 return 0x00000300000000B0ull; 992 } 993 return 0x00000300000000B0ull; 994 } 995 CVMX_PCIEEPX_CFG045(unsigned long offset)996static inline u64 CVMX_PCIEEPX_CFG045(unsigned long offset) 997 { 998 switch (cvmx_get_octeon_family()) { 999 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 1000 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 1001 return 0x00000300000000B4ull + (offset) * 0x100000000ull; 1002 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 1003 return 0x00000300000000B4ull + (offset) * 0x100000000ull; 1004 1005 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 1006 return 0x00000300000000B4ull + (offset) * 0x100000000ull; 1007 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 1008 return 0x00000300000000B4ull; 1009 } 1010 return 0x00000300000000B4ull; 1011 } 1012 CVMX_PCIEEPX_CFG046(unsigned long offset)1013static inline u64 CVMX_PCIEEPX_CFG046(unsigned long offset) 1014 { 1015 switch (cvmx_get_octeon_family()) { 1016 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 1017 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 1018 return 0x00000300000000B8ull + (offset) * 0x100000000ull; 1019 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 1020 return 0x00000300000000B8ull + (offset) * 0x100000000ull; 1021 1022 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 1023 return 0x00000300000000B8ull + (offset) * 0x100000000ull; 1024 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 1025 return 0x00000300000000B8ull; 1026 } 1027 return 0x00000300000000B8ull; 1028 } 1029 CVMX_PCIEEPX_CFG064(unsigned long offset)1030static inline u64 CVMX_PCIEEPX_CFG064(unsigned long offset) 1031 { 1032 switch (cvmx_get_octeon_family()) { 1033 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 1034 return 0x0000030000000100ull; 1035 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 1036 return 0x0000030000000100ull + (offset) * 0x100000000ull; 1037 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 1038 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 1039 return 0x0000030000000100ull + (offset) * 0x100000000ull; 1040 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 1041 return 0x0000030000000100ull + (offset) * 0x100000000ull; 1042 1043 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 1044 return 0x0000030000000100ull + (offset) * 0x100000000ull; 1045 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1046 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1047 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1048 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1049 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1050 return 0x0000000000000100ull; 1051 } 1052 return 0x0000030000000100ull; 1053 } 1054 CVMX_PCIEEPX_CFG065(unsigned long offset)1055static inline u64 CVMX_PCIEEPX_CFG065(unsigned long offset) 1056 { 1057 switch (cvmx_get_octeon_family()) { 1058 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 1059 return 0x0000030000000104ull; 1060 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 1061 return 0x0000030000000104ull + (offset) * 0x100000000ull; 1062 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 1063 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 1064 return 0x0000030000000104ull + (offset) * 0x100000000ull; 1065 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 1066 return 0x0000030000000104ull + (offset) * 0x100000000ull; 1067 1068 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 1069 return 0x0000030000000104ull + (offset) * 0x100000000ull; 1070 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1071 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1072 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1073 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1074 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1075 return 0x0000000000000104ull; 1076 } 1077 return 0x0000030000000104ull; 1078 } 1079 CVMX_PCIEEPX_CFG066(unsigned long offset)1080static inline u64 CVMX_PCIEEPX_CFG066(unsigned long offset) 1081 { 1082 switch (cvmx_get_octeon_family()) { 1083 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 1084 return 0x0000030000000108ull; 1085 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 1086 return 0x0000030000000108ull + (offset) * 0x100000000ull; 1087 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 1088 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 1089 return 0x0000030000000108ull + (offset) * 0x100000000ull; 1090 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 1091 return 0x0000030000000108ull + (offset) * 0x100000000ull; 1092 1093 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 1094 return 0x0000030000000108ull + (offset) * 0x100000000ull; 1095 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1096 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1097 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1098 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1099 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1100 return 0x0000000000000108ull; 1101 } 1102 return 0x0000030000000108ull; 1103 } 1104 CVMX_PCIEEPX_CFG067(unsigned long offset)1105static inline u64 CVMX_PCIEEPX_CFG067(unsigned long offset) 1106 { 1107 switch (cvmx_get_octeon_family()) { 1108 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 1109 return 0x000003000000010Cull; 1110 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 1111 return 0x000003000000010Cull + (offset) * 0x100000000ull; 1112 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 1113 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 1114 return 0x000003000000010Cull + (offset) * 0x100000000ull; 1115 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 1116 return 0x000003000000010Cull + (offset) * 0x100000000ull; 1117 1118 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 1119 return 0x000003000000010Cull + (offset) * 0x100000000ull; 1120 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1121 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1122 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1123 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1124 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1125 return 0x000000000000010Cull; 1126 } 1127 return 0x000003000000010Cull; 1128 } 1129 CVMX_PCIEEPX_CFG068(unsigned long offset)1130static inline u64 CVMX_PCIEEPX_CFG068(unsigned long offset) 1131 { 1132 switch (cvmx_get_octeon_family()) { 1133 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 1134 return 0x0000030000000110ull; 1135 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 1136 return 0x0000030000000110ull + (offset) * 0x100000000ull; 1137 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 1138 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 1139 return 0x0000030000000110ull + (offset) * 0x100000000ull; 1140 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 1141 return 0x0000030000000110ull + (offset) * 0x100000000ull; 1142 1143 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 1144 return 0x0000030000000110ull + (offset) * 0x100000000ull; 1145 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1146 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1147 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1148 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1149 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1150 return 0x0000000000000110ull; 1151 } 1152 return 0x0000030000000110ull; 1153 } 1154 CVMX_PCIEEPX_CFG069(unsigned long offset)1155static inline u64 CVMX_PCIEEPX_CFG069(unsigned long offset) 1156 { 1157 switch (cvmx_get_octeon_family()) { 1158 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 1159 return 0x0000030000000114ull; 1160 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 1161 return 0x0000030000000114ull + (offset) * 0x100000000ull; 1162 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 1163 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 1164 return 0x0000030000000114ull + (offset) * 0x100000000ull; 1165 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 1166 return 0x0000030000000114ull + (offset) * 0x100000000ull; 1167 1168 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 1169 return 0x0000030000000114ull + (offset) * 0x100000000ull; 1170 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1171 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1172 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1173 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1174 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1175 return 0x0000000000000114ull; 1176 } 1177 return 0x0000030000000114ull; 1178 } 1179 CVMX_PCIEEPX_CFG070(unsigned long offset)1180static inline u64 CVMX_PCIEEPX_CFG070(unsigned long offset) 1181 { 1182 switch (cvmx_get_octeon_family()) { 1183 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 1184 return 0x0000030000000118ull; 1185 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 1186 return 0x0000030000000118ull + (offset) * 0x100000000ull; 1187 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 1188 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 1189 return 0x0000030000000118ull + (offset) * 0x100000000ull; 1190 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 1191 return 0x0000030000000118ull + (offset) * 0x100000000ull; 1192 1193 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 1194 return 0x0000030000000118ull + (offset) * 0x100000000ull; 1195 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1196 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1197 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1198 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1199 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1200 return 0x0000000000000118ull; 1201 } 1202 return 0x0000030000000118ull; 1203 } 1204 CVMX_PCIEEPX_CFG071(unsigned long offset)1205static inline u64 CVMX_PCIEEPX_CFG071(unsigned long offset) 1206 { 1207 switch (cvmx_get_octeon_family()) { 1208 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 1209 return 0x000003000000011Cull; 1210 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 1211 return 0x000003000000011Cull + (offset) * 0x100000000ull; 1212 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 1213 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 1214 return 0x000003000000011Cull + (offset) * 0x100000000ull; 1215 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 1216 return 0x000003000000011Cull + (offset) * 0x100000000ull; 1217 1218 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 1219 return 0x000003000000011Cull + (offset) * 0x100000000ull; 1220 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1221 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1222 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1223 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1224 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1225 return 0x000000000000011Cull; 1226 } 1227 return 0x000003000000011Cull; 1228 } 1229 CVMX_PCIEEPX_CFG072(unsigned long offset)1230static inline u64 CVMX_PCIEEPX_CFG072(unsigned long offset) 1231 { 1232 switch (cvmx_get_octeon_family()) { 1233 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 1234 return 0x0000030000000120ull; 1235 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 1236 return 0x0000030000000120ull + (offset) * 0x100000000ull; 1237 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 1238 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 1239 return 0x0000030000000120ull + (offset) * 0x100000000ull; 1240 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 1241 return 0x0000030000000120ull + (offset) * 0x100000000ull; 1242 1243 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 1244 return 0x0000030000000120ull + (offset) * 0x100000000ull; 1245 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1246 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1247 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1248 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1249 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1250 return 0x0000000000000120ull; 1251 } 1252 return 0x0000030000000120ull; 1253 } 1254 CVMX_PCIEEPX_CFG073(unsigned long offset)1255static inline u64 CVMX_PCIEEPX_CFG073(unsigned long offset) 1256 { 1257 switch (cvmx_get_octeon_family()) { 1258 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 1259 return 0x0000030000000124ull; 1260 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 1261 return 0x0000030000000124ull + (offset) * 0x100000000ull; 1262 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 1263 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 1264 return 0x0000030000000124ull + (offset) * 0x100000000ull; 1265 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 1266 return 0x0000030000000124ull + (offset) * 0x100000000ull; 1267 1268 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 1269 return 0x0000030000000124ull + (offset) * 0x100000000ull; 1270 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1271 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1272 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1273 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1274 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1275 return 0x0000000000000124ull; 1276 } 1277 return 0x0000030000000124ull; 1278 } 1279 CVMX_PCIEEPX_CFG074(unsigned long offset)1280static inline u64 CVMX_PCIEEPX_CFG074(unsigned long offset) 1281 { 1282 switch (cvmx_get_octeon_family()) { 1283 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 1284 return 0x0000030000000128ull; 1285 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 1286 return 0x0000030000000128ull + (offset) * 0x100000000ull; 1287 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 1288 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 1289 return 0x0000030000000128ull + (offset) * 0x100000000ull; 1290 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 1291 return 0x0000030000000128ull + (offset) * 0x100000000ull; 1292 1293 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 1294 return 0x0000030000000128ull + (offset) * 0x100000000ull; 1295 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1296 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1297 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1298 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1299 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1300 return 0x0000000000000128ull; 1301 } 1302 return 0x0000030000000128ull; 1303 } 1304 CVMX_PCIEEPX_CFG078(unsigned long offset)1305static inline u64 CVMX_PCIEEPX_CFG078(unsigned long offset) 1306 { 1307 switch (cvmx_get_octeon_family()) { 1308 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 1309 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 1310 return 0x0000030000000138ull + (offset) * 0x100000000ull; 1311 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 1312 return 0x0000030000000138ull + (offset) * 0x100000000ull; 1313 1314 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 1315 return 0x0000030000000138ull + (offset) * 0x100000000ull; 1316 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 1317 return 0x0000030000000138ull; 1318 } 1319 return 0x0000030000000138ull; 1320 } 1321 CVMX_PCIEEPX_CFG082(unsigned long offset)1322static inline u64 CVMX_PCIEEPX_CFG082(unsigned long offset) 1323 { 1324 switch (cvmx_get_octeon_family()) { 1325 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 1326 return 0x0000030000000148ull; 1327 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 1328 return 0x0000030000000148ull + (offset) * 0x100000000ull; 1329 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 1330 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 1331 return 0x0000030000000148ull + (offset) * 0x100000000ull; 1332 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 1333 return 0x0000030000000148ull + (offset) * 0x100000000ull; 1334 1335 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 1336 return 0x0000030000000148ull + (offset) * 0x100000000ull; 1337 } 1338 return 0x0000030000000148ull; 1339 } 1340 CVMX_PCIEEPX_CFG083(unsigned long offset)1341static inline u64 CVMX_PCIEEPX_CFG083(unsigned long offset) 1342 { 1343 switch (cvmx_get_octeon_family()) { 1344 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 1345 return 0x000003000000014Cull; 1346 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 1347 return 0x000003000000014Cull + (offset) * 0x100000000ull; 1348 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 1349 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 1350 return 0x000003000000014Cull + (offset) * 0x100000000ull; 1351 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 1352 return 0x000003000000014Cull + (offset) * 0x100000000ull; 1353 1354 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 1355 return 0x000003000000014Cull + (offset) * 0x100000000ull; 1356 } 1357 return 0x000003000000014Cull; 1358 } 1359 1360 #define CVMX_PCIEEPX_CFG084(offset) (0x0000030000000150ull + ((offset) & 3) * 0x100000000ull) CVMX_PCIEEPX_CFG086(unsigned long offset)1361static inline u64 CVMX_PCIEEPX_CFG086(unsigned long offset) 1362 { 1363 switch (cvmx_get_octeon_family()) { 1364 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 1365 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 1366 return 0x0000030000000158ull + (offset) * 0x100000000ull; 1367 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 1368 return 0x0000030000000158ull + (offset) * 0x100000000ull; 1369 1370 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 1371 return 0x0000030000000158ull + (offset) * 0x100000000ull; 1372 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 1373 return 0x0000030000000158ull; 1374 } 1375 return 0x0000030000000158ull; 1376 } 1377 CVMX_PCIEEPX_CFG087(unsigned long offset)1378static inline u64 CVMX_PCIEEPX_CFG087(unsigned long offset) 1379 { 1380 switch (cvmx_get_octeon_family()) { 1381 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 1382 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 1383 return 0x000003000000015Cull + (offset) * 0x100000000ull; 1384 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 1385 return 0x000003000000015Cull + (offset) * 0x100000000ull; 1386 1387 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 1388 return 0x000003000000015Cull + (offset) * 0x100000000ull; 1389 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 1390 return 0x000003000000015Cull; 1391 } 1392 return 0x000003000000015Cull; 1393 } 1394 CVMX_PCIEEPX_CFG088(unsigned long offset)1395static inline u64 CVMX_PCIEEPX_CFG088(unsigned long offset) 1396 { 1397 switch (cvmx_get_octeon_family()) { 1398 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 1399 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 1400 return 0x0000030000000160ull + (offset) * 0x100000000ull; 1401 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 1402 return 0x0000030000000160ull + (offset) * 0x100000000ull; 1403 1404 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 1405 return 0x0000030000000160ull + (offset) * 0x100000000ull; 1406 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 1407 return 0x0000030000000160ull; 1408 } 1409 return 0x0000030000000160ull; 1410 } 1411 CVMX_PCIEEPX_CFG089(unsigned long offset)1412static inline u64 CVMX_PCIEEPX_CFG089(unsigned long offset) 1413 { 1414 switch (cvmx_get_octeon_family()) { 1415 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 1416 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 1417 return 0x0000030000000164ull + (offset) * 0x100000000ull; 1418 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 1419 return 0x0000030000000164ull + (offset) * 0x100000000ull; 1420 1421 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 1422 return 0x0000030000000164ull + (offset) * 0x100000000ull; 1423 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 1424 return 0x0000030000000164ull; 1425 } 1426 return 0x0000030000000164ull; 1427 } 1428 CVMX_PCIEEPX_CFG090(unsigned long offset)1429static inline u64 CVMX_PCIEEPX_CFG090(unsigned long offset) 1430 { 1431 switch (cvmx_get_octeon_family()) { 1432 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 1433 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 1434 return 0x0000030000000168ull + (offset) * 0x100000000ull; 1435 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 1436 return 0x0000030000000168ull + (offset) * 0x100000000ull; 1437 1438 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 1439 return 0x0000030000000168ull + (offset) * 0x100000000ull; 1440 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 1441 return 0x0000030000000168ull; 1442 } 1443 return 0x0000030000000168ull; 1444 } 1445 CVMX_PCIEEPX_CFG091(unsigned long offset)1446static inline u64 CVMX_PCIEEPX_CFG091(unsigned long offset) 1447 { 1448 switch (cvmx_get_octeon_family()) { 1449 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 1450 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 1451 return 0x000003000000016Cull + (offset) * 0x100000000ull; 1452 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 1453 return 0x000003000000016Cull + (offset) * 0x100000000ull; 1454 1455 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 1456 return 0x000003000000016Cull + (offset) * 0x100000000ull; 1457 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 1458 return 0x000003000000016Cull; 1459 } 1460 return 0x000003000000016Cull; 1461 } 1462 CVMX_PCIEEPX_CFG092(unsigned long offset)1463static inline u64 CVMX_PCIEEPX_CFG092(unsigned long offset) 1464 { 1465 switch (cvmx_get_octeon_family()) { 1466 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 1467 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 1468 return 0x0000030000000170ull + (offset) * 0x100000000ull; 1469 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 1470 return 0x0000030000000170ull + (offset) * 0x100000000ull; 1471 1472 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 1473 return 0x0000030000000170ull + (offset) * 0x100000000ull; 1474 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 1475 return 0x0000030000000170ull; 1476 } 1477 return 0x0000030000000170ull; 1478 } 1479 CVMX_PCIEEPX_CFG094(unsigned long offset)1480static inline u64 CVMX_PCIEEPX_CFG094(unsigned long offset) 1481 { 1482 switch (cvmx_get_octeon_family()) { 1483 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 1484 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 1485 return 0x0000030000000178ull + (offset) * 0x100000000ull; 1486 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 1487 return 0x0000030000000178ull + (offset) * 0x100000000ull; 1488 1489 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 1490 return 0x0000030000000178ull + (offset) * 0x100000000ull; 1491 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 1492 return 0x0000030000000178ull; 1493 } 1494 return 0x0000030000000178ull; 1495 } 1496 CVMX_PCIEEPX_CFG095(unsigned long offset)1497static inline u64 CVMX_PCIEEPX_CFG095(unsigned long offset) 1498 { 1499 switch (cvmx_get_octeon_family()) { 1500 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 1501 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 1502 return 0x000003000000017Cull + (offset) * 0x100000000ull; 1503 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 1504 return 0x000003000000017Cull + (offset) * 0x100000000ull; 1505 1506 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 1507 return 0x000003000000017Cull + (offset) * 0x100000000ull; 1508 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 1509 return 0x000003000000017Cull; 1510 } 1511 return 0x000003000000017Cull; 1512 } 1513 CVMX_PCIEEPX_CFG096(unsigned long offset)1514static inline u64 CVMX_PCIEEPX_CFG096(unsigned long offset) 1515 { 1516 switch (cvmx_get_octeon_family()) { 1517 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 1518 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 1519 return 0x0000030000000180ull + (offset) * 0x100000000ull; 1520 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 1521 return 0x0000030000000180ull + (offset) * 0x100000000ull; 1522 1523 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 1524 return 0x0000030000000180ull + (offset) * 0x100000000ull; 1525 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 1526 return 0x0000030000000180ull; 1527 } 1528 return 0x0000030000000180ull; 1529 } 1530 CVMX_PCIEEPX_CFG097(unsigned long offset)1531static inline u64 CVMX_PCIEEPX_CFG097(unsigned long offset) 1532 { 1533 switch (cvmx_get_octeon_family()) { 1534 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 1535 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 1536 return 0x0000030000000184ull + (offset) * 0x100000000ull; 1537 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 1538 return 0x0000030000000184ull + (offset) * 0x100000000ull; 1539 1540 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 1541 return 0x0000030000000184ull + (offset) * 0x100000000ull; 1542 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 1543 return 0x0000030000000184ull; 1544 } 1545 return 0x0000030000000184ull; 1546 } 1547 CVMX_PCIEEPX_CFG098(unsigned long offset)1548static inline u64 CVMX_PCIEEPX_CFG098(unsigned long offset) 1549 { 1550 switch (cvmx_get_octeon_family()) { 1551 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 1552 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 1553 return 0x0000030000000188ull + (offset) * 0x100000000ull; 1554 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 1555 return 0x0000030000000188ull + (offset) * 0x100000000ull; 1556 1557 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 1558 return 0x0000030000000188ull + (offset) * 0x100000000ull; 1559 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 1560 return 0x0000030000000188ull; 1561 } 1562 return 0x0000030000000188ull; 1563 } 1564 CVMX_PCIEEPX_CFG099(unsigned long offset)1565static inline u64 CVMX_PCIEEPX_CFG099(unsigned long offset) 1566 { 1567 switch (cvmx_get_octeon_family()) { 1568 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 1569 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 1570 return 0x000003000000018Cull + (offset) * 0x100000000ull; 1571 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 1572 return 0x000003000000018Cull + (offset) * 0x100000000ull; 1573 1574 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 1575 return 0x000003000000018Cull + (offset) * 0x100000000ull; 1576 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 1577 return 0x000003000000018Cull; 1578 } 1579 return 0x000003000000018Cull; 1580 } 1581 CVMX_PCIEEPX_CFG100(unsigned long offset)1582static inline u64 CVMX_PCIEEPX_CFG100(unsigned long offset) 1583 { 1584 switch (cvmx_get_octeon_family()) { 1585 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 1586 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 1587 return 0x0000030000000190ull + (offset) * 0x100000000ull; 1588 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 1589 return 0x0000030000000190ull + (offset) * 0x100000000ull; 1590 1591 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 1592 return 0x0000030000000190ull + (offset) * 0x100000000ull; 1593 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 1594 return 0x0000030000000190ull; 1595 } 1596 return 0x0000030000000190ull; 1597 } 1598 CVMX_PCIEEPX_CFG101(unsigned long offset)1599static inline u64 CVMX_PCIEEPX_CFG101(unsigned long offset) 1600 { 1601 switch (cvmx_get_octeon_family()) { 1602 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 1603 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 1604 return 0x0000030000000194ull + (offset) * 0x100000000ull; 1605 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 1606 return 0x0000030000000194ull + (offset) * 0x100000000ull; 1607 1608 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 1609 return 0x0000030000000194ull + (offset) * 0x100000000ull; 1610 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 1611 return 0x0000030000000194ull; 1612 } 1613 return 0x0000030000000194ull; 1614 } 1615 CVMX_PCIEEPX_CFG102(unsigned long offset)1616static inline u64 CVMX_PCIEEPX_CFG102(unsigned long offset) 1617 { 1618 switch (cvmx_get_octeon_family()) { 1619 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 1620 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 1621 return 0x0000030000000198ull + (offset) * 0x100000000ull; 1622 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 1623 return 0x0000030000000198ull + (offset) * 0x100000000ull; 1624 1625 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 1626 return 0x0000030000000198ull + (offset) * 0x100000000ull; 1627 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 1628 return 0x0000030000000198ull; 1629 } 1630 return 0x0000030000000198ull; 1631 } 1632 CVMX_PCIEEPX_CFG103(unsigned long offset)1633static inline u64 CVMX_PCIEEPX_CFG103(unsigned long offset) 1634 { 1635 switch (cvmx_get_octeon_family()) { 1636 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 1637 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 1638 return 0x000003000000019Cull + (offset) * 0x100000000ull; 1639 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 1640 return 0x000003000000019Cull + (offset) * 0x100000000ull; 1641 1642 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 1643 return 0x000003000000019Cull + (offset) * 0x100000000ull; 1644 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 1645 return 0x000003000000019Cull; 1646 } 1647 return 0x000003000000019Cull; 1648 } 1649 CVMX_PCIEEPX_CFG104(unsigned long offset)1650static inline u64 CVMX_PCIEEPX_CFG104(unsigned long offset) 1651 { 1652 switch (cvmx_get_octeon_family()) { 1653 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 1654 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 1655 return 0x00000300000001A0ull + (offset) * 0x100000000ull; 1656 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 1657 return 0x00000300000001A0ull + (offset) * 0x100000000ull; 1658 1659 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 1660 return 0x00000300000001A0ull + (offset) * 0x100000000ull; 1661 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 1662 return 0x00000300000001A0ull; 1663 } 1664 return 0x00000300000001A0ull; 1665 } 1666 CVMX_PCIEEPX_CFG105(unsigned long offset)1667static inline u64 CVMX_PCIEEPX_CFG105(unsigned long offset) 1668 { 1669 switch (cvmx_get_octeon_family()) { 1670 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 1671 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 1672 return 0x00000300000001A4ull + (offset) * 0x100000000ull; 1673 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 1674 return 0x00000300000001A4ull + (offset) * 0x100000000ull; 1675 1676 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 1677 return 0x00000300000001A4ull + (offset) * 0x100000000ull; 1678 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 1679 return 0x00000300000001A4ull; 1680 } 1681 return 0x00000300000001A4ull; 1682 } 1683 CVMX_PCIEEPX_CFG106(unsigned long offset)1684static inline u64 CVMX_PCIEEPX_CFG106(unsigned long offset) 1685 { 1686 switch (cvmx_get_octeon_family()) { 1687 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 1688 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 1689 return 0x00000300000001A8ull + (offset) * 0x100000000ull; 1690 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 1691 return 0x00000300000001A8ull + (offset) * 0x100000000ull; 1692 1693 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 1694 return 0x00000300000001A8ull + (offset) * 0x100000000ull; 1695 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 1696 return 0x00000300000001A8ull; 1697 } 1698 return 0x00000300000001A8ull; 1699 } 1700 CVMX_PCIEEPX_CFG107(unsigned long offset)1701static inline u64 CVMX_PCIEEPX_CFG107(unsigned long offset) 1702 { 1703 switch (cvmx_get_octeon_family()) { 1704 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 1705 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 1706 return 0x00000300000001ACull + (offset) * 0x100000000ull; 1707 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 1708 return 0x00000300000001ACull + (offset) * 0x100000000ull; 1709 1710 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 1711 return 0x00000300000001ACull + (offset) * 0x100000000ull; 1712 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 1713 return 0x00000300000001ACull; 1714 } 1715 return 0x00000300000001ACull; 1716 } 1717 CVMX_PCIEEPX_CFG108(unsigned long offset)1718static inline u64 CVMX_PCIEEPX_CFG108(unsigned long offset) 1719 { 1720 switch (cvmx_get_octeon_family()) { 1721 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 1722 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 1723 return 0x00000300000001B0ull + (offset) * 0x100000000ull; 1724 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 1725 return 0x00000300000001B0ull + (offset) * 0x100000000ull; 1726 1727 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 1728 return 0x00000300000001B0ull + (offset) * 0x100000000ull; 1729 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 1730 return 0x00000300000001B0ull; 1731 } 1732 return 0x00000300000001B0ull; 1733 } 1734 CVMX_PCIEEPX_CFG109(unsigned long offset)1735static inline u64 CVMX_PCIEEPX_CFG109(unsigned long offset) 1736 { 1737 switch (cvmx_get_octeon_family()) { 1738 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 1739 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 1740 return 0x00000300000001B4ull + (offset) * 0x100000000ull; 1741 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 1742 return 0x00000300000001B4ull + (offset) * 0x100000000ull; 1743 1744 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 1745 return 0x00000300000001B4ull + (offset) * 0x100000000ull; 1746 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 1747 return 0x00000300000001B4ull; 1748 } 1749 return 0x00000300000001B4ull; 1750 } 1751 CVMX_PCIEEPX_CFG110(unsigned long offset)1752static inline u64 CVMX_PCIEEPX_CFG110(unsigned long offset) 1753 { 1754 switch (cvmx_get_octeon_family()) { 1755 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 1756 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 1757 return 0x00000300000001B8ull + (offset) * 0x100000000ull; 1758 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 1759 return 0x00000300000001B8ull + (offset) * 0x100000000ull; 1760 1761 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 1762 return 0x00000300000001B8ull + (offset) * 0x100000000ull; 1763 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 1764 return 0x00000300000001B8ull; 1765 } 1766 return 0x00000300000001B8ull; 1767 } 1768 CVMX_PCIEEPX_CFG111(unsigned long offset)1769static inline u64 CVMX_PCIEEPX_CFG111(unsigned long offset) 1770 { 1771 switch (cvmx_get_octeon_family()) { 1772 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 1773 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 1774 return 0x00000300000001BCull + (offset) * 0x100000000ull; 1775 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 1776 return 0x00000300000001BCull + (offset) * 0x100000000ull; 1777 1778 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 1779 return 0x00000300000001BCull + (offset) * 0x100000000ull; 1780 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 1781 return 0x00000300000001BCull; 1782 } 1783 return 0x00000300000001BCull; 1784 } 1785 CVMX_PCIEEPX_CFG112(unsigned long offset)1786static inline u64 CVMX_PCIEEPX_CFG112(unsigned long offset) 1787 { 1788 switch (cvmx_get_octeon_family()) { 1789 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 1790 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 1791 return 0x00000300000001C0ull + (offset) * 0x100000000ull; 1792 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 1793 return 0x00000300000001C0ull + (offset) * 0x100000000ull; 1794 1795 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 1796 return 0x00000300000001C0ull + (offset) * 0x100000000ull; 1797 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 1798 return 0x00000300000001C0ull; 1799 } 1800 return 0x00000300000001C0ull; 1801 } 1802 CVMX_PCIEEPX_CFG448(unsigned long offset)1803static inline u64 CVMX_PCIEEPX_CFG448(unsigned long offset) 1804 { 1805 switch (cvmx_get_octeon_family()) { 1806 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 1807 return 0x0000030000000700ull; 1808 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 1809 return 0x0000030000000700ull + (offset) * 0x100000000ull; 1810 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 1811 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 1812 return 0x0000030000000700ull + (offset) * 0x100000000ull; 1813 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 1814 return 0x0000030000000700ull + (offset) * 0x100000000ull; 1815 1816 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 1817 return 0x0000030000000700ull + (offset) * 0x100000000ull; 1818 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1819 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1820 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1821 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1822 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1823 return 0x0000000000000700ull; 1824 } 1825 return 0x0000030000000700ull; 1826 } 1827 CVMX_PCIEEPX_CFG449(unsigned long offset)1828static inline u64 CVMX_PCIEEPX_CFG449(unsigned long offset) 1829 { 1830 switch (cvmx_get_octeon_family()) { 1831 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 1832 return 0x0000030000000704ull; 1833 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 1834 return 0x0000030000000704ull + (offset) * 0x100000000ull; 1835 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 1836 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 1837 return 0x0000030000000704ull + (offset) * 0x100000000ull; 1838 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 1839 return 0x0000030000000704ull + (offset) * 0x100000000ull; 1840 1841 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 1842 return 0x0000030000000704ull + (offset) * 0x100000000ull; 1843 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1844 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1845 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1846 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1847 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1848 return 0x0000000000000704ull; 1849 } 1850 return 0x0000030000000704ull; 1851 } 1852 CVMX_PCIEEPX_CFG450(unsigned long offset)1853static inline u64 CVMX_PCIEEPX_CFG450(unsigned long offset) 1854 { 1855 switch (cvmx_get_octeon_family()) { 1856 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 1857 return 0x0000030000000708ull; 1858 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 1859 return 0x0000030000000708ull + (offset) * 0x100000000ull; 1860 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 1861 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 1862 return 0x0000030000000708ull + (offset) * 0x100000000ull; 1863 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 1864 return 0x0000030000000708ull + (offset) * 0x100000000ull; 1865 1866 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 1867 return 0x0000030000000708ull + (offset) * 0x100000000ull; 1868 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1869 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1870 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1871 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1872 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1873 return 0x0000000000000708ull; 1874 } 1875 return 0x0000030000000708ull; 1876 } 1877 CVMX_PCIEEPX_CFG451(unsigned long offset)1878static inline u64 CVMX_PCIEEPX_CFG451(unsigned long offset) 1879 { 1880 switch (cvmx_get_octeon_family()) { 1881 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 1882 return 0x000003000000070Cull; 1883 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 1884 return 0x000003000000070Cull + (offset) * 0x100000000ull; 1885 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 1886 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 1887 return 0x000003000000070Cull + (offset) * 0x100000000ull; 1888 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 1889 return 0x000003000000070Cull + (offset) * 0x100000000ull; 1890 1891 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 1892 return 0x000003000000070Cull + (offset) * 0x100000000ull; 1893 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1894 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1895 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1896 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1897 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1898 return 0x000000000000070Cull; 1899 } 1900 return 0x000003000000070Cull; 1901 } 1902 CVMX_PCIEEPX_CFG452(unsigned long offset)1903static inline u64 CVMX_PCIEEPX_CFG452(unsigned long offset) 1904 { 1905 switch (cvmx_get_octeon_family()) { 1906 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 1907 return 0x0000030000000710ull; 1908 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 1909 return 0x0000030000000710ull + (offset) * 0x100000000ull; 1910 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 1911 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 1912 return 0x0000030000000710ull + (offset) * 0x100000000ull; 1913 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 1914 return 0x0000030000000710ull + (offset) * 0x100000000ull; 1915 1916 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 1917 return 0x0000030000000710ull + (offset) * 0x100000000ull; 1918 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1919 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1920 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1921 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1922 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1923 return 0x0000000000000710ull; 1924 } 1925 return 0x0000030000000710ull; 1926 } 1927 CVMX_PCIEEPX_CFG453(unsigned long offset)1928static inline u64 CVMX_PCIEEPX_CFG453(unsigned long offset) 1929 { 1930 switch (cvmx_get_octeon_family()) { 1931 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 1932 return 0x0000030000000714ull; 1933 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 1934 return 0x0000030000000714ull + (offset) * 0x100000000ull; 1935 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 1936 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 1937 return 0x0000030000000714ull + (offset) * 0x100000000ull; 1938 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 1939 return 0x0000030000000714ull + (offset) * 0x100000000ull; 1940 1941 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 1942 return 0x0000030000000714ull + (offset) * 0x100000000ull; 1943 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1944 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1945 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1946 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1947 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1948 return 0x0000000000000714ull; 1949 } 1950 return 0x0000030000000714ull; 1951 } 1952 CVMX_PCIEEPX_CFG454(unsigned long offset)1953static inline u64 CVMX_PCIEEPX_CFG454(unsigned long offset) 1954 { 1955 switch (cvmx_get_octeon_family()) { 1956 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 1957 return 0x0000030000000718ull; 1958 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 1959 return 0x0000030000000718ull + (offset) * 0x100000000ull; 1960 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 1961 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 1962 return 0x0000030000000718ull + (offset) * 0x100000000ull; 1963 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 1964 return 0x0000030000000718ull + (offset) * 0x100000000ull; 1965 1966 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 1967 return 0x0000030000000718ull + (offset) * 0x100000000ull; 1968 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1969 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1970 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1971 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1972 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1973 return 0x0000000000000718ull; 1974 } 1975 return 0x0000030000000718ull; 1976 } 1977 CVMX_PCIEEPX_CFG455(unsigned long offset)1978static inline u64 CVMX_PCIEEPX_CFG455(unsigned long offset) 1979 { 1980 switch (cvmx_get_octeon_family()) { 1981 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 1982 return 0x000003000000071Cull; 1983 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 1984 return 0x000003000000071Cull + (offset) * 0x100000000ull; 1985 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 1986 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 1987 return 0x000003000000071Cull + (offset) * 0x100000000ull; 1988 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 1989 return 0x000003000000071Cull + (offset) * 0x100000000ull; 1990 1991 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 1992 return 0x000003000000071Cull + (offset) * 0x100000000ull; 1993 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1994 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1995 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1996 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1997 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1998 return 0x000000000000071Cull; 1999 } 2000 return 0x000003000000071Cull; 2001 } 2002 CVMX_PCIEEPX_CFG456(unsigned long offset)2003static inline u64 CVMX_PCIEEPX_CFG456(unsigned long offset) 2004 { 2005 switch (cvmx_get_octeon_family()) { 2006 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 2007 return 0x0000030000000720ull; 2008 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 2009 return 0x0000030000000720ull + (offset) * 0x100000000ull; 2010 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 2011 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 2012 return 0x0000030000000720ull + (offset) * 0x100000000ull; 2013 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 2014 return 0x0000030000000720ull + (offset) * 0x100000000ull; 2015 2016 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 2017 return 0x0000030000000720ull + (offset) * 0x100000000ull; 2018 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 2019 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 2020 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 2021 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 2022 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 2023 return 0x0000000000000720ull; 2024 } 2025 return 0x0000030000000720ull; 2026 } 2027 CVMX_PCIEEPX_CFG458(unsigned long offset)2028static inline u64 CVMX_PCIEEPX_CFG458(unsigned long offset) 2029 { 2030 switch (cvmx_get_octeon_family()) { 2031 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 2032 return 0x0000030000000728ull; 2033 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 2034 return 0x0000030000000728ull + (offset) * 0x100000000ull; 2035 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 2036 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 2037 return 0x0000030000000728ull + (offset) * 0x100000000ull; 2038 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 2039 return 0x0000030000000728ull + (offset) * 0x100000000ull; 2040 2041 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 2042 return 0x0000030000000728ull + (offset) * 0x100000000ull; 2043 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 2044 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 2045 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 2046 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 2047 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 2048 return 0x0000000000000728ull; 2049 } 2050 return 0x0000030000000728ull; 2051 } 2052 CVMX_PCIEEPX_CFG459(unsigned long offset)2053static inline u64 CVMX_PCIEEPX_CFG459(unsigned long offset) 2054 { 2055 switch (cvmx_get_octeon_family()) { 2056 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 2057 return 0x000003000000072Cull; 2058 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 2059 return 0x000003000000072Cull + (offset) * 0x100000000ull; 2060 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 2061 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 2062 return 0x000003000000072Cull + (offset) * 0x100000000ull; 2063 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 2064 return 0x000003000000072Cull + (offset) * 0x100000000ull; 2065 2066 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 2067 return 0x000003000000072Cull + (offset) * 0x100000000ull; 2068 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 2069 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 2070 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 2071 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 2072 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 2073 return 0x000000000000072Cull; 2074 } 2075 return 0x000003000000072Cull; 2076 } 2077 CVMX_PCIEEPX_CFG460(unsigned long offset)2078static inline u64 CVMX_PCIEEPX_CFG460(unsigned long offset) 2079 { 2080 switch (cvmx_get_octeon_family()) { 2081 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 2082 return 0x0000030000000730ull; 2083 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 2084 return 0x0000030000000730ull + (offset) * 0x100000000ull; 2085 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 2086 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 2087 return 0x0000030000000730ull + (offset) * 0x100000000ull; 2088 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 2089 return 0x0000030000000730ull + (offset) * 0x100000000ull; 2090 2091 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 2092 return 0x0000030000000730ull + (offset) * 0x100000000ull; 2093 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 2094 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 2095 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 2096 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 2097 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 2098 return 0x0000000000000730ull; 2099 } 2100 return 0x0000030000000730ull; 2101 } 2102 CVMX_PCIEEPX_CFG461(unsigned long offset)2103static inline u64 CVMX_PCIEEPX_CFG461(unsigned long offset) 2104 { 2105 switch (cvmx_get_octeon_family()) { 2106 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 2107 return 0x0000030000000734ull; 2108 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 2109 return 0x0000030000000734ull + (offset) * 0x100000000ull; 2110 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 2111 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 2112 return 0x0000030000000734ull + (offset) * 0x100000000ull; 2113 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 2114 return 0x0000030000000734ull + (offset) * 0x100000000ull; 2115 2116 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 2117 return 0x0000030000000734ull + (offset) * 0x100000000ull; 2118 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 2119 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 2120 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 2121 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 2122 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 2123 return 0x0000000000000734ull; 2124 } 2125 return 0x0000030000000734ull; 2126 } 2127 CVMX_PCIEEPX_CFG462(unsigned long offset)2128static inline u64 CVMX_PCIEEPX_CFG462(unsigned long offset) 2129 { 2130 switch (cvmx_get_octeon_family()) { 2131 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 2132 return 0x0000030000000738ull; 2133 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 2134 return 0x0000030000000738ull + (offset) * 0x100000000ull; 2135 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 2136 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 2137 return 0x0000030000000738ull + (offset) * 0x100000000ull; 2138 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 2139 return 0x0000030000000738ull + (offset) * 0x100000000ull; 2140 2141 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 2142 return 0x0000030000000738ull + (offset) * 0x100000000ull; 2143 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 2144 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 2145 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 2146 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 2147 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 2148 return 0x0000000000000738ull; 2149 } 2150 return 0x0000030000000738ull; 2151 } 2152 CVMX_PCIEEPX_CFG463(unsigned long offset)2153static inline u64 CVMX_PCIEEPX_CFG463(unsigned long offset) 2154 { 2155 switch (cvmx_get_octeon_family()) { 2156 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 2157 return 0x000003000000073Cull; 2158 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 2159 return 0x000003000000073Cull + (offset) * 0x100000000ull; 2160 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 2161 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 2162 return 0x000003000000073Cull + (offset) * 0x100000000ull; 2163 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 2164 return 0x000003000000073Cull + (offset) * 0x100000000ull; 2165 2166 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 2167 return 0x000003000000073Cull + (offset) * 0x100000000ull; 2168 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 2169 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 2170 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 2171 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 2172 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 2173 return 0x000000000000073Cull; 2174 } 2175 return 0x000003000000073Cull; 2176 } 2177 CVMX_PCIEEPX_CFG464(unsigned long offset)2178static inline u64 CVMX_PCIEEPX_CFG464(unsigned long offset) 2179 { 2180 switch (cvmx_get_octeon_family()) { 2181 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 2182 return 0x0000030000000740ull; 2183 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 2184 return 0x0000030000000740ull + (offset) * 0x100000000ull; 2185 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 2186 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 2187 return 0x0000030000000740ull + (offset) * 0x100000000ull; 2188 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 2189 return 0x0000030000000740ull + (offset) * 0x100000000ull; 2190 2191 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 2192 return 0x0000030000000740ull + (offset) * 0x100000000ull; 2193 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 2194 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 2195 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 2196 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 2197 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 2198 return 0x0000000000000740ull; 2199 } 2200 return 0x0000030000000740ull; 2201 } 2202 CVMX_PCIEEPX_CFG465(unsigned long offset)2203static inline u64 CVMX_PCIEEPX_CFG465(unsigned long offset) 2204 { 2205 switch (cvmx_get_octeon_family()) { 2206 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 2207 return 0x0000030000000744ull; 2208 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 2209 return 0x0000030000000744ull + (offset) * 0x100000000ull; 2210 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 2211 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 2212 return 0x0000030000000744ull + (offset) * 0x100000000ull; 2213 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 2214 return 0x0000030000000744ull + (offset) * 0x100000000ull; 2215 2216 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 2217 return 0x0000030000000744ull + (offset) * 0x100000000ull; 2218 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 2219 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 2220 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 2221 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 2222 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 2223 return 0x0000000000000744ull; 2224 } 2225 return 0x0000030000000744ull; 2226 } 2227 CVMX_PCIEEPX_CFG466(unsigned long offset)2228static inline u64 CVMX_PCIEEPX_CFG466(unsigned long offset) 2229 { 2230 switch (cvmx_get_octeon_family()) { 2231 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 2232 return 0x0000030000000748ull; 2233 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 2234 return 0x0000030000000748ull + (offset) * 0x100000000ull; 2235 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 2236 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 2237 return 0x0000030000000748ull + (offset) * 0x100000000ull; 2238 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 2239 return 0x0000030000000748ull + (offset) * 0x100000000ull; 2240 2241 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 2242 return 0x0000030000000748ull + (offset) * 0x100000000ull; 2243 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 2244 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 2245 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 2246 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 2247 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 2248 return 0x0000000000000748ull; 2249 } 2250 return 0x0000030000000748ull; 2251 } 2252 CVMX_PCIEEPX_CFG467(unsigned long offset)2253static inline u64 CVMX_PCIEEPX_CFG467(unsigned long offset) 2254 { 2255 switch (cvmx_get_octeon_family()) { 2256 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 2257 return 0x000003000000074Cull; 2258 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 2259 return 0x000003000000074Cull + (offset) * 0x100000000ull; 2260 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 2261 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 2262 return 0x000003000000074Cull + (offset) * 0x100000000ull; 2263 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 2264 return 0x000003000000074Cull + (offset) * 0x100000000ull; 2265 2266 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 2267 return 0x000003000000074Cull + (offset) * 0x100000000ull; 2268 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 2269 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 2270 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 2271 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 2272 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 2273 return 0x000000000000074Cull; 2274 } 2275 return 0x000003000000074Cull; 2276 } 2277 CVMX_PCIEEPX_CFG468(unsigned long offset)2278static inline u64 CVMX_PCIEEPX_CFG468(unsigned long offset) 2279 { 2280 switch (cvmx_get_octeon_family()) { 2281 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 2282 return 0x0000030000000750ull; 2283 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 2284 return 0x0000030000000750ull + (offset) * 0x100000000ull; 2285 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 2286 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 2287 return 0x0000030000000750ull + (offset) * 0x100000000ull; 2288 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 2289 return 0x0000030000000750ull + (offset) * 0x100000000ull; 2290 2291 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 2292 return 0x0000030000000750ull + (offset) * 0x100000000ull; 2293 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 2294 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 2295 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 2296 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 2297 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 2298 return 0x0000000000000750ull; 2299 } 2300 return 0x0000030000000750ull; 2301 } 2302 CVMX_PCIEEPX_CFG490(unsigned long offset)2303static inline u64 CVMX_PCIEEPX_CFG490(unsigned long offset) 2304 { 2305 switch (cvmx_get_octeon_family()) { 2306 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 2307 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 2308 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 2309 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 2310 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 2311 return 0x00000000000007A8ull; 2312 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 2313 return 0x00000300000007A8ull + (offset) * 0x100000000ull; 2314 } 2315 return 0x00000000000007A8ull; 2316 } 2317 CVMX_PCIEEPX_CFG491(unsigned long offset)2318static inline u64 CVMX_PCIEEPX_CFG491(unsigned long offset) 2319 { 2320 switch (cvmx_get_octeon_family()) { 2321 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 2322 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 2323 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 2324 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 2325 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 2326 return 0x00000000000007ACull; 2327 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 2328 return 0x00000300000007ACull + (offset) * 0x100000000ull; 2329 } 2330 return 0x00000000000007ACull; 2331 } 2332 CVMX_PCIEEPX_CFG492(unsigned long offset)2333static inline u64 CVMX_PCIEEPX_CFG492(unsigned long offset) 2334 { 2335 switch (cvmx_get_octeon_family()) { 2336 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 2337 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 2338 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 2339 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 2340 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 2341 return 0x00000000000007B0ull; 2342 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 2343 return 0x00000300000007B0ull + (offset) * 0x100000000ull; 2344 } 2345 return 0x00000000000007B0ull; 2346 } 2347 CVMX_PCIEEPX_CFG515(unsigned long offset)2348static inline u64 CVMX_PCIEEPX_CFG515(unsigned long offset) 2349 { 2350 switch (cvmx_get_octeon_family()) { 2351 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 2352 return 0x000003000000080Cull + (offset) * 0x100000000ull; 2353 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 2354 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 2355 return 0x000003000000080Cull + (offset) * 0x100000000ull; 2356 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 2357 return 0x000003000000080Cull + (offset) * 0x100000000ull; 2358 2359 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 2360 return 0x000003000000080Cull + (offset) * 0x100000000ull; 2361 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 2362 return 0x000003000000080Cull; 2363 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 2364 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 2365 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 2366 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 2367 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 2368 return 0x000000000000080Cull; 2369 } 2370 return 0x000003000000080Cull; 2371 } 2372 CVMX_PCIEEPX_CFG516(unsigned long offset)2373static inline u64 CVMX_PCIEEPX_CFG516(unsigned long offset) 2374 { 2375 switch (cvmx_get_octeon_family()) { 2376 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 2377 return 0x0000030000000810ull; 2378 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 2379 return 0x0000030000000810ull + (offset) * 0x100000000ull; 2380 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 2381 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 2382 return 0x0000030000000810ull + (offset) * 0x100000000ull; 2383 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 2384 return 0x0000030000000810ull + (offset) * 0x100000000ull; 2385 2386 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 2387 return 0x0000030000000810ull + (offset) * 0x100000000ull; 2388 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 2389 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 2390 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 2391 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 2392 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 2393 return 0x0000000000000810ull; 2394 } 2395 return 0x0000030000000810ull; 2396 } 2397 CVMX_PCIEEPX_CFG517(unsigned long offset)2398static inline u64 CVMX_PCIEEPX_CFG517(unsigned long offset) 2399 { 2400 switch (cvmx_get_octeon_family()) { 2401 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 2402 return 0x0000030000000814ull; 2403 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 2404 return 0x0000030000000814ull + (offset) * 0x100000000ull; 2405 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 2406 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 2407 return 0x0000030000000814ull + (offset) * 0x100000000ull; 2408 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 2409 return 0x0000030000000814ull + (offset) * 0x100000000ull; 2410 2411 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 2412 return 0x0000030000000814ull + (offset) * 0x100000000ull; 2413 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 2414 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 2415 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 2416 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 2417 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 2418 return 0x0000000000000814ull; 2419 } 2420 return 0x0000030000000814ull; 2421 } 2422 CVMX_PCIEEPX_CFG548(unsigned long offset)2423static inline u64 CVMX_PCIEEPX_CFG548(unsigned long offset) 2424 { 2425 switch (cvmx_get_octeon_family()) { 2426 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 2427 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 2428 return 0x0000030000000890ull + (offset) * 0x100000000ull; 2429 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 2430 return 0x0000030000000890ull + (offset) * 0x100000000ull; 2431 2432 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 2433 return 0x0000030000000890ull + (offset) * 0x100000000ull; 2434 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 2435 return 0x0000030000000890ull; 2436 } 2437 return 0x0000030000000890ull; 2438 } 2439 CVMX_PCIEEPX_CFG554(unsigned long offset)2440static inline u64 CVMX_PCIEEPX_CFG554(unsigned long offset) 2441 { 2442 switch (cvmx_get_octeon_family()) { 2443 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 2444 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 2445 return 0x00000300000008A8ull + (offset) * 0x100000000ull; 2446 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 2447 return 0x00000300000008A8ull + (offset) * 0x100000000ull; 2448 2449 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 2450 return 0x00000300000008A8ull + (offset) * 0x100000000ull; 2451 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 2452 return 0x00000300000008A8ull; 2453 } 2454 return 0x00000300000008A8ull; 2455 } 2456 CVMX_PCIEEPX_CFG558(unsigned long offset)2457static inline u64 CVMX_PCIEEPX_CFG558(unsigned long offset) 2458 { 2459 switch (cvmx_get_octeon_family()) { 2460 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 2461 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 2462 return 0x00000300000008B8ull + (offset) * 0x100000000ull; 2463 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 2464 return 0x00000300000008B8ull + (offset) * 0x100000000ull; 2465 2466 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 2467 return 0x00000300000008B8ull + (offset) * 0x100000000ull; 2468 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 2469 return 0x00000300000008B8ull; 2470 } 2471 return 0x00000300000008B8ull; 2472 } 2473 CVMX_PCIEEPX_CFG559(unsigned long offset)2474static inline u64 CVMX_PCIEEPX_CFG559(unsigned long offset) 2475 { 2476 switch (cvmx_get_octeon_family()) { 2477 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 2478 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 2479 return 0x00000300000008BCull + (offset) * 0x100000000ull; 2480 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 2481 return 0x00000300000008BCull + (offset) * 0x100000000ull; 2482 2483 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 2484 return 0x00000300000008BCull + (offset) * 0x100000000ull; 2485 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 2486 return 0x00000300000008BCull; 2487 } 2488 return 0x00000300000008BCull; 2489 } 2490 2491 /** 2492 * cvmx_pcieep#_cfg000 2493 * 2494 * This register contains the first 32-bits of PCIe type 0 configuration space. 2495 * 2496 */ 2497 union cvmx_pcieepx_cfg000 { 2498 u32 u32; 2499 struct cvmx_pcieepx_cfg000_s { 2500 u32 devid : 16; 2501 u32 vendid : 16; 2502 } s; 2503 struct cvmx_pcieepx_cfg000_s cn52xx; 2504 struct cvmx_pcieepx_cfg000_s cn52xxp1; 2505 struct cvmx_pcieepx_cfg000_s cn56xx; 2506 struct cvmx_pcieepx_cfg000_s cn56xxp1; 2507 struct cvmx_pcieepx_cfg000_s cn61xx; 2508 struct cvmx_pcieepx_cfg000_s cn63xx; 2509 struct cvmx_pcieepx_cfg000_s cn63xxp1; 2510 struct cvmx_pcieepx_cfg000_s cn66xx; 2511 struct cvmx_pcieepx_cfg000_s cn68xx; 2512 struct cvmx_pcieepx_cfg000_s cn68xxp1; 2513 struct cvmx_pcieepx_cfg000_s cn70xx; 2514 struct cvmx_pcieepx_cfg000_s cn70xxp1; 2515 struct cvmx_pcieepx_cfg000_s cn73xx; 2516 struct cvmx_pcieepx_cfg000_s cn78xx; 2517 struct cvmx_pcieepx_cfg000_s cn78xxp1; 2518 struct cvmx_pcieepx_cfg000_s cnf71xx; 2519 struct cvmx_pcieepx_cfg000_s cnf75xx; 2520 }; 2521 2522 typedef union cvmx_pcieepx_cfg000 cvmx_pcieepx_cfg000_t; 2523 2524 /** 2525 * cvmx_pcieep#_cfg001 2526 * 2527 * This register contains the second 32-bits of PCIe type 0 configuration space. 2528 * 2529 */ 2530 union cvmx_pcieepx_cfg001 { 2531 u32 u32; 2532 struct cvmx_pcieepx_cfg001_s { 2533 u32 dpe : 1; 2534 u32 sse : 1; 2535 u32 rma : 1; 2536 u32 rta : 1; 2537 u32 sta : 1; 2538 u32 devt : 2; 2539 u32 mdpe : 1; 2540 u32 fbb : 1; 2541 u32 reserved_22_22 : 1; 2542 u32 m66 : 1; 2543 u32 cl : 1; 2544 u32 i_stat : 1; 2545 u32 reserved_11_18 : 8; 2546 u32 i_dis : 1; 2547 u32 fbbe : 1; 2548 u32 see : 1; 2549 u32 ids_wcc : 1; 2550 u32 per : 1; 2551 u32 vps : 1; 2552 u32 mwice : 1; 2553 u32 scse : 1; 2554 u32 me : 1; 2555 u32 msae : 1; 2556 u32 isae : 1; 2557 } s; 2558 struct cvmx_pcieepx_cfg001_s cn52xx; 2559 struct cvmx_pcieepx_cfg001_s cn52xxp1; 2560 struct cvmx_pcieepx_cfg001_s cn56xx; 2561 struct cvmx_pcieepx_cfg001_s cn56xxp1; 2562 struct cvmx_pcieepx_cfg001_s cn61xx; 2563 struct cvmx_pcieepx_cfg001_s cn63xx; 2564 struct cvmx_pcieepx_cfg001_s cn63xxp1; 2565 struct cvmx_pcieepx_cfg001_s cn66xx; 2566 struct cvmx_pcieepx_cfg001_s cn68xx; 2567 struct cvmx_pcieepx_cfg001_s cn68xxp1; 2568 struct cvmx_pcieepx_cfg001_s cn70xx; 2569 struct cvmx_pcieepx_cfg001_s cn70xxp1; 2570 struct cvmx_pcieepx_cfg001_s cn73xx; 2571 struct cvmx_pcieepx_cfg001_s cn78xx; 2572 struct cvmx_pcieepx_cfg001_s cn78xxp1; 2573 struct cvmx_pcieepx_cfg001_s cnf71xx; 2574 struct cvmx_pcieepx_cfg001_s cnf75xx; 2575 }; 2576 2577 typedef union cvmx_pcieepx_cfg001 cvmx_pcieepx_cfg001_t; 2578 2579 /** 2580 * cvmx_pcieep#_cfg002 2581 * 2582 * This register contains the third 32-bits of PCIe type 0 configuration space. 2583 * 2584 */ 2585 union cvmx_pcieepx_cfg002 { 2586 u32 u32; 2587 struct cvmx_pcieepx_cfg002_s { 2588 u32 bcc : 8; 2589 u32 sc : 8; 2590 u32 pi : 8; 2591 u32 rid : 8; 2592 } s; 2593 struct cvmx_pcieepx_cfg002_s cn52xx; 2594 struct cvmx_pcieepx_cfg002_s cn52xxp1; 2595 struct cvmx_pcieepx_cfg002_s cn56xx; 2596 struct cvmx_pcieepx_cfg002_s cn56xxp1; 2597 struct cvmx_pcieepx_cfg002_s cn61xx; 2598 struct cvmx_pcieepx_cfg002_s cn63xx; 2599 struct cvmx_pcieepx_cfg002_s cn63xxp1; 2600 struct cvmx_pcieepx_cfg002_s cn66xx; 2601 struct cvmx_pcieepx_cfg002_s cn68xx; 2602 struct cvmx_pcieepx_cfg002_s cn68xxp1; 2603 struct cvmx_pcieepx_cfg002_s cn70xx; 2604 struct cvmx_pcieepx_cfg002_s cn70xxp1; 2605 struct cvmx_pcieepx_cfg002_s cn73xx; 2606 struct cvmx_pcieepx_cfg002_s cn78xx; 2607 struct cvmx_pcieepx_cfg002_s cn78xxp1; 2608 struct cvmx_pcieepx_cfg002_s cnf71xx; 2609 struct cvmx_pcieepx_cfg002_s cnf75xx; 2610 }; 2611 2612 typedef union cvmx_pcieepx_cfg002 cvmx_pcieepx_cfg002_t; 2613 2614 /** 2615 * cvmx_pcieep#_cfg003 2616 * 2617 * This register contains the fourth 32-bits of PCIe type 0 configuration space. 2618 * 2619 */ 2620 union cvmx_pcieepx_cfg003 { 2621 u32 u32; 2622 struct cvmx_pcieepx_cfg003_s { 2623 u32 bist : 8; 2624 u32 mfd : 1; 2625 u32 chf : 7; 2626 u32 lt : 8; 2627 u32 cls : 8; 2628 } s; 2629 struct cvmx_pcieepx_cfg003_s cn52xx; 2630 struct cvmx_pcieepx_cfg003_s cn52xxp1; 2631 struct cvmx_pcieepx_cfg003_s cn56xx; 2632 struct cvmx_pcieepx_cfg003_s cn56xxp1; 2633 struct cvmx_pcieepx_cfg003_s cn61xx; 2634 struct cvmx_pcieepx_cfg003_s cn63xx; 2635 struct cvmx_pcieepx_cfg003_s cn63xxp1; 2636 struct cvmx_pcieepx_cfg003_s cn66xx; 2637 struct cvmx_pcieepx_cfg003_s cn68xx; 2638 struct cvmx_pcieepx_cfg003_s cn68xxp1; 2639 struct cvmx_pcieepx_cfg003_s cn70xx; 2640 struct cvmx_pcieepx_cfg003_s cn70xxp1; 2641 struct cvmx_pcieepx_cfg003_s cn73xx; 2642 struct cvmx_pcieepx_cfg003_s cn78xx; 2643 struct cvmx_pcieepx_cfg003_s cn78xxp1; 2644 struct cvmx_pcieepx_cfg003_s cnf71xx; 2645 struct cvmx_pcieepx_cfg003_s cnf75xx; 2646 }; 2647 2648 typedef union cvmx_pcieepx_cfg003 cvmx_pcieepx_cfg003_t; 2649 2650 /** 2651 * cvmx_pcieep#_cfg004 2652 * 2653 * This register contains the fifth 32-bits of PCIe type 0 configuration space. 2654 * 2655 */ 2656 union cvmx_pcieepx_cfg004 { 2657 u32 u32; 2658 struct cvmx_pcieepx_cfg004_s { 2659 u32 reserved_4_31 : 28; 2660 u32 pf : 1; 2661 u32 typ : 2; 2662 u32 mspc : 1; 2663 } s; 2664 struct cvmx_pcieepx_cfg004_cn52xx { 2665 u32 lbab : 18; 2666 u32 reserved_4_13 : 10; 2667 u32 pf : 1; 2668 u32 typ : 2; 2669 u32 mspc : 1; 2670 } cn52xx; 2671 struct cvmx_pcieepx_cfg004_cn52xx cn52xxp1; 2672 struct cvmx_pcieepx_cfg004_cn52xx cn56xx; 2673 struct cvmx_pcieepx_cfg004_cn52xx cn56xxp1; 2674 struct cvmx_pcieepx_cfg004_cn52xx cn61xx; 2675 struct cvmx_pcieepx_cfg004_cn52xx cn63xx; 2676 struct cvmx_pcieepx_cfg004_cn52xx cn63xxp1; 2677 struct cvmx_pcieepx_cfg004_cn52xx cn66xx; 2678 struct cvmx_pcieepx_cfg004_cn52xx cn68xx; 2679 struct cvmx_pcieepx_cfg004_cn52xx cn68xxp1; 2680 struct cvmx_pcieepx_cfg004_cn52xx cn70xx; 2681 struct cvmx_pcieepx_cfg004_cn52xx cn70xxp1; 2682 struct cvmx_pcieepx_cfg004_cn73xx { 2683 u32 lbab : 9; 2684 u32 reserved_4_22 : 19; 2685 u32 pf : 1; 2686 u32 typ : 2; 2687 u32 mspc : 1; 2688 } cn73xx; 2689 struct cvmx_pcieepx_cfg004_cn73xx cn78xx; 2690 struct cvmx_pcieepx_cfg004_cn78xxp1 { 2691 u32 lbab : 17; 2692 u32 reserved_4_14 : 11; 2693 u32 pf : 1; 2694 u32 typ : 2; 2695 u32 mspc : 1; 2696 } cn78xxp1; 2697 struct cvmx_pcieepx_cfg004_cn52xx cnf71xx; 2698 struct cvmx_pcieepx_cfg004_cn73xx cnf75xx; 2699 }; 2700 2701 typedef union cvmx_pcieepx_cfg004 cvmx_pcieepx_cfg004_t; 2702 2703 /** 2704 * cvmx_pcieep#_cfg004_mask 2705 * 2706 * The BAR 0 mask register is invisible to host software and not readable from the application. 2707 * The BAR 0 mask register is only writable through PEM()_CFG_WR. 2708 */ 2709 union cvmx_pcieepx_cfg004_mask { 2710 u32 u32; 2711 struct cvmx_pcieepx_cfg004_mask_s { 2712 u32 lmask : 31; 2713 u32 enb : 1; 2714 } s; 2715 struct cvmx_pcieepx_cfg004_mask_s cn52xx; 2716 struct cvmx_pcieepx_cfg004_mask_s cn52xxp1; 2717 struct cvmx_pcieepx_cfg004_mask_s cn56xx; 2718 struct cvmx_pcieepx_cfg004_mask_s cn56xxp1; 2719 struct cvmx_pcieepx_cfg004_mask_s cn61xx; 2720 struct cvmx_pcieepx_cfg004_mask_s cn63xx; 2721 struct cvmx_pcieepx_cfg004_mask_s cn63xxp1; 2722 struct cvmx_pcieepx_cfg004_mask_s cn66xx; 2723 struct cvmx_pcieepx_cfg004_mask_s cn68xx; 2724 struct cvmx_pcieepx_cfg004_mask_s cn68xxp1; 2725 struct cvmx_pcieepx_cfg004_mask_s cn70xx; 2726 struct cvmx_pcieepx_cfg004_mask_s cn70xxp1; 2727 struct cvmx_pcieepx_cfg004_mask_s cn73xx; 2728 struct cvmx_pcieepx_cfg004_mask_s cn78xx; 2729 struct cvmx_pcieepx_cfg004_mask_s cn78xxp1; 2730 struct cvmx_pcieepx_cfg004_mask_s cnf71xx; 2731 struct cvmx_pcieepx_cfg004_mask_s cnf75xx; 2732 }; 2733 2734 typedef union cvmx_pcieepx_cfg004_mask cvmx_pcieepx_cfg004_mask_t; 2735 2736 /** 2737 * cvmx_pcieep#_cfg005 2738 * 2739 * This register contains the sixth 32-bits of PCIe type 0 configuration space. 2740 * 2741 */ 2742 union cvmx_pcieepx_cfg005 { 2743 u32 u32; 2744 struct cvmx_pcieepx_cfg005_s { 2745 u32 ubab : 32; 2746 } s; 2747 struct cvmx_pcieepx_cfg005_s cn52xx; 2748 struct cvmx_pcieepx_cfg005_s cn52xxp1; 2749 struct cvmx_pcieepx_cfg005_s cn56xx; 2750 struct cvmx_pcieepx_cfg005_s cn56xxp1; 2751 struct cvmx_pcieepx_cfg005_s cn61xx; 2752 struct cvmx_pcieepx_cfg005_s cn63xx; 2753 struct cvmx_pcieepx_cfg005_s cn63xxp1; 2754 struct cvmx_pcieepx_cfg005_s cn66xx; 2755 struct cvmx_pcieepx_cfg005_s cn68xx; 2756 struct cvmx_pcieepx_cfg005_s cn68xxp1; 2757 struct cvmx_pcieepx_cfg005_s cn70xx; 2758 struct cvmx_pcieepx_cfg005_s cn70xxp1; 2759 struct cvmx_pcieepx_cfg005_s cn73xx; 2760 struct cvmx_pcieepx_cfg005_s cn78xx; 2761 struct cvmx_pcieepx_cfg005_s cn78xxp1; 2762 struct cvmx_pcieepx_cfg005_s cnf71xx; 2763 struct cvmx_pcieepx_cfg005_s cnf75xx; 2764 }; 2765 2766 typedef union cvmx_pcieepx_cfg005 cvmx_pcieepx_cfg005_t; 2767 2768 /** 2769 * cvmx_pcieep#_cfg005_mask 2770 * 2771 * The BAR 0 mask register is invisible to host software and not readable from the application. 2772 * The BAR 0 mask register is only writable through PEM()_CFG_WR. 2773 */ 2774 union cvmx_pcieepx_cfg005_mask { 2775 u32 u32; 2776 struct cvmx_pcieepx_cfg005_mask_s { 2777 u32 umask : 32; 2778 } s; 2779 struct cvmx_pcieepx_cfg005_mask_s cn52xx; 2780 struct cvmx_pcieepx_cfg005_mask_s cn52xxp1; 2781 struct cvmx_pcieepx_cfg005_mask_s cn56xx; 2782 struct cvmx_pcieepx_cfg005_mask_s cn56xxp1; 2783 struct cvmx_pcieepx_cfg005_mask_s cn61xx; 2784 struct cvmx_pcieepx_cfg005_mask_s cn63xx; 2785 struct cvmx_pcieepx_cfg005_mask_s cn63xxp1; 2786 struct cvmx_pcieepx_cfg005_mask_s cn66xx; 2787 struct cvmx_pcieepx_cfg005_mask_s cn68xx; 2788 struct cvmx_pcieepx_cfg005_mask_s cn68xxp1; 2789 struct cvmx_pcieepx_cfg005_mask_s cn70xx; 2790 struct cvmx_pcieepx_cfg005_mask_s cn70xxp1; 2791 struct cvmx_pcieepx_cfg005_mask_s cn73xx; 2792 struct cvmx_pcieepx_cfg005_mask_s cn78xx; 2793 struct cvmx_pcieepx_cfg005_mask_s cn78xxp1; 2794 struct cvmx_pcieepx_cfg005_mask_s cnf71xx; 2795 struct cvmx_pcieepx_cfg005_mask_s cnf75xx; 2796 }; 2797 2798 typedef union cvmx_pcieepx_cfg005_mask cvmx_pcieepx_cfg005_mask_t; 2799 2800 /** 2801 * cvmx_pcieep#_cfg006 2802 * 2803 * This register contains the seventh 32-bits of PCIe type 0 configuration space. 2804 * 2805 */ 2806 union cvmx_pcieepx_cfg006 { 2807 u32 u32; 2808 struct cvmx_pcieepx_cfg006_s { 2809 u32 lbab : 6; 2810 u32 reserved_4_25 : 22; 2811 u32 pf : 1; 2812 u32 typ : 2; 2813 u32 mspc : 1; 2814 } s; 2815 struct cvmx_pcieepx_cfg006_s cn52xx; 2816 struct cvmx_pcieepx_cfg006_s cn52xxp1; 2817 struct cvmx_pcieepx_cfg006_s cn56xx; 2818 struct cvmx_pcieepx_cfg006_s cn56xxp1; 2819 struct cvmx_pcieepx_cfg006_s cn61xx; 2820 struct cvmx_pcieepx_cfg006_s cn63xx; 2821 struct cvmx_pcieepx_cfg006_s cn63xxp1; 2822 struct cvmx_pcieepx_cfg006_s cn66xx; 2823 struct cvmx_pcieepx_cfg006_s cn68xx; 2824 struct cvmx_pcieepx_cfg006_s cn68xxp1; 2825 struct cvmx_pcieepx_cfg006_s cn70xx; 2826 struct cvmx_pcieepx_cfg006_s cn70xxp1; 2827 struct cvmx_pcieepx_cfg006_s cn73xx; 2828 struct cvmx_pcieepx_cfg006_s cn78xx; 2829 struct cvmx_pcieepx_cfg006_s cn78xxp1; 2830 struct cvmx_pcieepx_cfg006_s cnf71xx; 2831 struct cvmx_pcieepx_cfg006_s cnf75xx; 2832 }; 2833 2834 typedef union cvmx_pcieepx_cfg006 cvmx_pcieepx_cfg006_t; 2835 2836 /** 2837 * cvmx_pcieep#_cfg006_mask 2838 * 2839 * The BAR 1 mask register is invisible to host software and not readable from the application. 2840 * The BAR 1 mask register is only writable through PEM()_CFG_WR. 2841 */ 2842 union cvmx_pcieepx_cfg006_mask { 2843 u32 u32; 2844 struct cvmx_pcieepx_cfg006_mask_s { 2845 u32 lmask : 31; 2846 u32 enb : 1; 2847 } s; 2848 struct cvmx_pcieepx_cfg006_mask_s cn52xx; 2849 struct cvmx_pcieepx_cfg006_mask_s cn52xxp1; 2850 struct cvmx_pcieepx_cfg006_mask_s cn56xx; 2851 struct cvmx_pcieepx_cfg006_mask_s cn56xxp1; 2852 struct cvmx_pcieepx_cfg006_mask_s cn61xx; 2853 struct cvmx_pcieepx_cfg006_mask_s cn63xx; 2854 struct cvmx_pcieepx_cfg006_mask_s cn63xxp1; 2855 struct cvmx_pcieepx_cfg006_mask_s cn66xx; 2856 struct cvmx_pcieepx_cfg006_mask_s cn68xx; 2857 struct cvmx_pcieepx_cfg006_mask_s cn68xxp1; 2858 struct cvmx_pcieepx_cfg006_mask_s cn70xx; 2859 struct cvmx_pcieepx_cfg006_mask_s cn70xxp1; 2860 struct cvmx_pcieepx_cfg006_mask_s cn73xx; 2861 struct cvmx_pcieepx_cfg006_mask_s cn78xx; 2862 struct cvmx_pcieepx_cfg006_mask_s cn78xxp1; 2863 struct cvmx_pcieepx_cfg006_mask_s cnf71xx; 2864 struct cvmx_pcieepx_cfg006_mask_s cnf75xx; 2865 }; 2866 2867 typedef union cvmx_pcieepx_cfg006_mask cvmx_pcieepx_cfg006_mask_t; 2868 2869 /** 2870 * cvmx_pcieep#_cfg007 2871 * 2872 * This register contains the eighth 32-bits of PCIe type 0 configuration space. 2873 * 2874 */ 2875 union cvmx_pcieepx_cfg007 { 2876 u32 u32; 2877 struct cvmx_pcieepx_cfg007_s { 2878 u32 ubab : 32; 2879 } s; 2880 struct cvmx_pcieepx_cfg007_s cn52xx; 2881 struct cvmx_pcieepx_cfg007_s cn52xxp1; 2882 struct cvmx_pcieepx_cfg007_s cn56xx; 2883 struct cvmx_pcieepx_cfg007_s cn56xxp1; 2884 struct cvmx_pcieepx_cfg007_s cn61xx; 2885 struct cvmx_pcieepx_cfg007_s cn63xx; 2886 struct cvmx_pcieepx_cfg007_s cn63xxp1; 2887 struct cvmx_pcieepx_cfg007_s cn66xx; 2888 struct cvmx_pcieepx_cfg007_s cn68xx; 2889 struct cvmx_pcieepx_cfg007_s cn68xxp1; 2890 struct cvmx_pcieepx_cfg007_s cn70xx; 2891 struct cvmx_pcieepx_cfg007_s cn70xxp1; 2892 struct cvmx_pcieepx_cfg007_s cn73xx; 2893 struct cvmx_pcieepx_cfg007_s cn78xx; 2894 struct cvmx_pcieepx_cfg007_s cn78xxp1; 2895 struct cvmx_pcieepx_cfg007_s cnf71xx; 2896 struct cvmx_pcieepx_cfg007_s cnf75xx; 2897 }; 2898 2899 typedef union cvmx_pcieepx_cfg007 cvmx_pcieepx_cfg007_t; 2900 2901 /** 2902 * cvmx_pcieep#_cfg007_mask 2903 * 2904 * The BAR 1 mask register is invisible to host software and not readable from the application. 2905 * The BAR 1 mask register is only writable through PEM()_CFG_WR. 2906 */ 2907 union cvmx_pcieepx_cfg007_mask { 2908 u32 u32; 2909 struct cvmx_pcieepx_cfg007_mask_s { 2910 u32 umask : 32; 2911 } s; 2912 struct cvmx_pcieepx_cfg007_mask_s cn52xx; 2913 struct cvmx_pcieepx_cfg007_mask_s cn52xxp1; 2914 struct cvmx_pcieepx_cfg007_mask_s cn56xx; 2915 struct cvmx_pcieepx_cfg007_mask_s cn56xxp1; 2916 struct cvmx_pcieepx_cfg007_mask_s cn61xx; 2917 struct cvmx_pcieepx_cfg007_mask_s cn63xx; 2918 struct cvmx_pcieepx_cfg007_mask_s cn63xxp1; 2919 struct cvmx_pcieepx_cfg007_mask_s cn66xx; 2920 struct cvmx_pcieepx_cfg007_mask_s cn68xx; 2921 struct cvmx_pcieepx_cfg007_mask_s cn68xxp1; 2922 struct cvmx_pcieepx_cfg007_mask_s cn70xx; 2923 struct cvmx_pcieepx_cfg007_mask_s cn70xxp1; 2924 struct cvmx_pcieepx_cfg007_mask_s cn73xx; 2925 struct cvmx_pcieepx_cfg007_mask_s cn78xx; 2926 struct cvmx_pcieepx_cfg007_mask_s cn78xxp1; 2927 struct cvmx_pcieepx_cfg007_mask_s cnf71xx; 2928 struct cvmx_pcieepx_cfg007_mask_s cnf75xx; 2929 }; 2930 2931 typedef union cvmx_pcieepx_cfg007_mask cvmx_pcieepx_cfg007_mask_t; 2932 2933 /** 2934 * cvmx_pcieep#_cfg008 2935 * 2936 * This register contains the ninth 32-bits of PCIe type 0 configuration space. 2937 * 2938 */ 2939 union cvmx_pcieepx_cfg008 { 2940 u32 u32; 2941 struct cvmx_pcieepx_cfg008_s { 2942 u32 lbab : 12; 2943 u32 reserved_4_19 : 16; 2944 u32 pf : 1; 2945 u32 typ : 2; 2946 u32 mspc : 1; 2947 } s; 2948 struct cvmx_pcieepx_cfg008_cn52xx { 2949 u32 reserved_4_31 : 28; 2950 u32 pf : 1; 2951 u32 typ : 2; 2952 u32 mspc : 1; 2953 } cn52xx; 2954 struct cvmx_pcieepx_cfg008_cn52xx cn52xxp1; 2955 struct cvmx_pcieepx_cfg008_cn52xx cn56xx; 2956 struct cvmx_pcieepx_cfg008_cn52xx cn56xxp1; 2957 struct cvmx_pcieepx_cfg008_cn52xx cn61xx; 2958 struct cvmx_pcieepx_cfg008_cn52xx cn63xx; 2959 struct cvmx_pcieepx_cfg008_cn52xx cn63xxp1; 2960 struct cvmx_pcieepx_cfg008_cn52xx cn66xx; 2961 struct cvmx_pcieepx_cfg008_cn52xx cn68xx; 2962 struct cvmx_pcieepx_cfg008_cn52xx cn68xxp1; 2963 struct cvmx_pcieepx_cfg008_s cn70xx; 2964 struct cvmx_pcieepx_cfg008_s cn70xxp1; 2965 struct cvmx_pcieepx_cfg008_s cn73xx; 2966 struct cvmx_pcieepx_cfg008_s cn78xx; 2967 struct cvmx_pcieepx_cfg008_s cn78xxp1; 2968 struct cvmx_pcieepx_cfg008_cn52xx cnf71xx; 2969 struct cvmx_pcieepx_cfg008_s cnf75xx; 2970 }; 2971 2972 typedef union cvmx_pcieepx_cfg008 cvmx_pcieepx_cfg008_t; 2973 2974 /** 2975 * cvmx_pcieep#_cfg008_mask 2976 * 2977 * The BAR 2 mask register is invisible to host software and not readable from the application. 2978 * The BAR 2 mask register is only writable through PEM()_CFG_WR. 2979 */ 2980 union cvmx_pcieepx_cfg008_mask { 2981 u32 u32; 2982 struct cvmx_pcieepx_cfg008_mask_s { 2983 u32 lmask : 31; 2984 u32 enb : 1; 2985 } s; 2986 struct cvmx_pcieepx_cfg008_mask_s cn52xx; 2987 struct cvmx_pcieepx_cfg008_mask_s cn52xxp1; 2988 struct cvmx_pcieepx_cfg008_mask_s cn56xx; 2989 struct cvmx_pcieepx_cfg008_mask_s cn56xxp1; 2990 struct cvmx_pcieepx_cfg008_mask_s cn61xx; 2991 struct cvmx_pcieepx_cfg008_mask_s cn63xx; 2992 struct cvmx_pcieepx_cfg008_mask_s cn63xxp1; 2993 struct cvmx_pcieepx_cfg008_mask_s cn66xx; 2994 struct cvmx_pcieepx_cfg008_mask_s cn68xx; 2995 struct cvmx_pcieepx_cfg008_mask_s cn68xxp1; 2996 struct cvmx_pcieepx_cfg008_mask_s cn70xx; 2997 struct cvmx_pcieepx_cfg008_mask_s cn70xxp1; 2998 struct cvmx_pcieepx_cfg008_mask_s cn73xx; 2999 struct cvmx_pcieepx_cfg008_mask_s cn78xx; 3000 struct cvmx_pcieepx_cfg008_mask_s cn78xxp1; 3001 struct cvmx_pcieepx_cfg008_mask_s cnf71xx; 3002 struct cvmx_pcieepx_cfg008_mask_s cnf75xx; 3003 }; 3004 3005 typedef union cvmx_pcieepx_cfg008_mask cvmx_pcieepx_cfg008_mask_t; 3006 3007 /** 3008 * cvmx_pcieep#_cfg009 3009 * 3010 * This register contains the tenth 32-bits of PCIe type 0 configuration space. 3011 * 3012 */ 3013 union cvmx_pcieepx_cfg009 { 3014 u32 u32; 3015 struct cvmx_pcieepx_cfg009_s { 3016 u32 reserved_0_31 : 32; 3017 } s; 3018 struct cvmx_pcieepx_cfg009_cn52xx { 3019 u32 ubab : 25; 3020 u32 reserved_0_6 : 7; 3021 } cn52xx; 3022 struct cvmx_pcieepx_cfg009_cn52xx cn52xxp1; 3023 struct cvmx_pcieepx_cfg009_cn52xx cn56xx; 3024 struct cvmx_pcieepx_cfg009_cn52xx cn56xxp1; 3025 struct cvmx_pcieepx_cfg009_cn61xx { 3026 u32 ubab : 23; 3027 u32 reserved_0_8 : 9; 3028 } cn61xx; 3029 struct cvmx_pcieepx_cfg009_cn61xx cn63xx; 3030 struct cvmx_pcieepx_cfg009_cn61xx cn63xxp1; 3031 struct cvmx_pcieepx_cfg009_cn61xx cn66xx; 3032 struct cvmx_pcieepx_cfg009_cn61xx cn68xx; 3033 struct cvmx_pcieepx_cfg009_cn61xx cn68xxp1; 3034 struct cvmx_pcieepx_cfg009_cn70xx { 3035 u32 ubab : 32; 3036 } cn70xx; 3037 struct cvmx_pcieepx_cfg009_cn70xx cn70xxp1; 3038 struct cvmx_pcieepx_cfg009_cn70xx cn73xx; 3039 struct cvmx_pcieepx_cfg009_cn70xx cn78xx; 3040 struct cvmx_pcieepx_cfg009_cn70xx cn78xxp1; 3041 struct cvmx_pcieepx_cfg009_cn61xx cnf71xx; 3042 struct cvmx_pcieepx_cfg009_cn70xx cnf75xx; 3043 }; 3044 3045 typedef union cvmx_pcieepx_cfg009 cvmx_pcieepx_cfg009_t; 3046 3047 /** 3048 * cvmx_pcieep#_cfg009_mask 3049 * 3050 * The BAR 2 mask register is invisible to host software and not readable from the application. 3051 * The BAR 2 mask register is only writable through PEM()_CFG_WR. 3052 */ 3053 union cvmx_pcieepx_cfg009_mask { 3054 u32 u32; 3055 struct cvmx_pcieepx_cfg009_mask_s { 3056 u32 umask : 32; 3057 } s; 3058 struct cvmx_pcieepx_cfg009_mask_s cn52xx; 3059 struct cvmx_pcieepx_cfg009_mask_s cn52xxp1; 3060 struct cvmx_pcieepx_cfg009_mask_s cn56xx; 3061 struct cvmx_pcieepx_cfg009_mask_s cn56xxp1; 3062 struct cvmx_pcieepx_cfg009_mask_s cn61xx; 3063 struct cvmx_pcieepx_cfg009_mask_s cn63xx; 3064 struct cvmx_pcieepx_cfg009_mask_s cn63xxp1; 3065 struct cvmx_pcieepx_cfg009_mask_s cn66xx; 3066 struct cvmx_pcieepx_cfg009_mask_s cn68xx; 3067 struct cvmx_pcieepx_cfg009_mask_s cn68xxp1; 3068 struct cvmx_pcieepx_cfg009_mask_s cn70xx; 3069 struct cvmx_pcieepx_cfg009_mask_s cn70xxp1; 3070 struct cvmx_pcieepx_cfg009_mask_s cn73xx; 3071 struct cvmx_pcieepx_cfg009_mask_s cn78xx; 3072 struct cvmx_pcieepx_cfg009_mask_s cn78xxp1; 3073 struct cvmx_pcieepx_cfg009_mask_s cnf71xx; 3074 struct cvmx_pcieepx_cfg009_mask_s cnf75xx; 3075 }; 3076 3077 typedef union cvmx_pcieepx_cfg009_mask cvmx_pcieepx_cfg009_mask_t; 3078 3079 /** 3080 * cvmx_pcieep#_cfg010 3081 * 3082 * This register contains the eleventh 32-bits of PCIe type 0 configuration space. 3083 * 3084 */ 3085 union cvmx_pcieepx_cfg010 { 3086 u32 u32; 3087 struct cvmx_pcieepx_cfg010_s { 3088 u32 cisp : 32; 3089 } s; 3090 struct cvmx_pcieepx_cfg010_s cn52xx; 3091 struct cvmx_pcieepx_cfg010_s cn52xxp1; 3092 struct cvmx_pcieepx_cfg010_s cn56xx; 3093 struct cvmx_pcieepx_cfg010_s cn56xxp1; 3094 struct cvmx_pcieepx_cfg010_s cn61xx; 3095 struct cvmx_pcieepx_cfg010_s cn63xx; 3096 struct cvmx_pcieepx_cfg010_s cn63xxp1; 3097 struct cvmx_pcieepx_cfg010_s cn66xx; 3098 struct cvmx_pcieepx_cfg010_s cn68xx; 3099 struct cvmx_pcieepx_cfg010_s cn68xxp1; 3100 struct cvmx_pcieepx_cfg010_s cn70xx; 3101 struct cvmx_pcieepx_cfg010_s cn70xxp1; 3102 struct cvmx_pcieepx_cfg010_s cn73xx; 3103 struct cvmx_pcieepx_cfg010_s cn78xx; 3104 struct cvmx_pcieepx_cfg010_s cn78xxp1; 3105 struct cvmx_pcieepx_cfg010_s cnf71xx; 3106 struct cvmx_pcieepx_cfg010_s cnf75xx; 3107 }; 3108 3109 typedef union cvmx_pcieepx_cfg010 cvmx_pcieepx_cfg010_t; 3110 3111 /** 3112 * cvmx_pcieep#_cfg011 3113 * 3114 * This register contains the twelfth 32-bits of PCIe type 0 configuration space. 3115 * 3116 */ 3117 union cvmx_pcieepx_cfg011 { 3118 u32 u32; 3119 struct cvmx_pcieepx_cfg011_s { 3120 u32 ssid : 16; 3121 u32 ssvid : 16; 3122 } s; 3123 struct cvmx_pcieepx_cfg011_s cn52xx; 3124 struct cvmx_pcieepx_cfg011_s cn52xxp1; 3125 struct cvmx_pcieepx_cfg011_s cn56xx; 3126 struct cvmx_pcieepx_cfg011_s cn56xxp1; 3127 struct cvmx_pcieepx_cfg011_s cn61xx; 3128 struct cvmx_pcieepx_cfg011_s cn63xx; 3129 struct cvmx_pcieepx_cfg011_s cn63xxp1; 3130 struct cvmx_pcieepx_cfg011_s cn66xx; 3131 struct cvmx_pcieepx_cfg011_s cn68xx; 3132 struct cvmx_pcieepx_cfg011_s cn68xxp1; 3133 struct cvmx_pcieepx_cfg011_s cn70xx; 3134 struct cvmx_pcieepx_cfg011_s cn70xxp1; 3135 struct cvmx_pcieepx_cfg011_s cn73xx; 3136 struct cvmx_pcieepx_cfg011_s cn78xx; 3137 struct cvmx_pcieepx_cfg011_s cn78xxp1; 3138 struct cvmx_pcieepx_cfg011_s cnf71xx; 3139 struct cvmx_pcieepx_cfg011_s cnf75xx; 3140 }; 3141 3142 typedef union cvmx_pcieepx_cfg011 cvmx_pcieepx_cfg011_t; 3143 3144 /** 3145 * cvmx_pcieep#_cfg012 3146 * 3147 * This register contains the thirteenth 32-bits of PCIe type 0 configuration space. 3148 * 3149 */ 3150 union cvmx_pcieepx_cfg012 { 3151 u32 u32; 3152 struct cvmx_pcieepx_cfg012_s { 3153 u32 eraddr : 16; 3154 u32 reserved_1_15 : 15; 3155 u32 er_en : 1; 3156 } s; 3157 struct cvmx_pcieepx_cfg012_s cn52xx; 3158 struct cvmx_pcieepx_cfg012_s cn52xxp1; 3159 struct cvmx_pcieepx_cfg012_s cn56xx; 3160 struct cvmx_pcieepx_cfg012_s cn56xxp1; 3161 struct cvmx_pcieepx_cfg012_s cn61xx; 3162 struct cvmx_pcieepx_cfg012_s cn63xx; 3163 struct cvmx_pcieepx_cfg012_s cn63xxp1; 3164 struct cvmx_pcieepx_cfg012_s cn66xx; 3165 struct cvmx_pcieepx_cfg012_s cn68xx; 3166 struct cvmx_pcieepx_cfg012_s cn68xxp1; 3167 struct cvmx_pcieepx_cfg012_s cn70xx; 3168 struct cvmx_pcieepx_cfg012_s cn70xxp1; 3169 struct cvmx_pcieepx_cfg012_s cn73xx; 3170 struct cvmx_pcieepx_cfg012_s cn78xx; 3171 struct cvmx_pcieepx_cfg012_s cn78xxp1; 3172 struct cvmx_pcieepx_cfg012_s cnf71xx; 3173 struct cvmx_pcieepx_cfg012_s cnf75xx; 3174 }; 3175 3176 typedef union cvmx_pcieepx_cfg012 cvmx_pcieepx_cfg012_t; 3177 3178 /** 3179 * cvmx_pcieep#_cfg012_mask 3180 * 3181 * The ROM mask register is invisible to host software and not readable from the application. The 3182 * ROM mask register is only writable through PEM()_CFG_WR. 3183 */ 3184 union cvmx_pcieepx_cfg012_mask { 3185 u32 u32; 3186 struct cvmx_pcieepx_cfg012_mask_s { 3187 u32 mask : 31; 3188 u32 enb : 1; 3189 } s; 3190 struct cvmx_pcieepx_cfg012_mask_s cn52xx; 3191 struct cvmx_pcieepx_cfg012_mask_s cn52xxp1; 3192 struct cvmx_pcieepx_cfg012_mask_s cn56xx; 3193 struct cvmx_pcieepx_cfg012_mask_s cn56xxp1; 3194 struct cvmx_pcieepx_cfg012_mask_s cn61xx; 3195 struct cvmx_pcieepx_cfg012_mask_s cn63xx; 3196 struct cvmx_pcieepx_cfg012_mask_s cn63xxp1; 3197 struct cvmx_pcieepx_cfg012_mask_s cn66xx; 3198 struct cvmx_pcieepx_cfg012_mask_s cn68xx; 3199 struct cvmx_pcieepx_cfg012_mask_s cn68xxp1; 3200 struct cvmx_pcieepx_cfg012_mask_s cn70xx; 3201 struct cvmx_pcieepx_cfg012_mask_s cn70xxp1; 3202 struct cvmx_pcieepx_cfg012_mask_s cn73xx; 3203 struct cvmx_pcieepx_cfg012_mask_s cn78xx; 3204 struct cvmx_pcieepx_cfg012_mask_s cn78xxp1; 3205 struct cvmx_pcieepx_cfg012_mask_s cnf71xx; 3206 struct cvmx_pcieepx_cfg012_mask_s cnf75xx; 3207 }; 3208 3209 typedef union cvmx_pcieepx_cfg012_mask cvmx_pcieepx_cfg012_mask_t; 3210 3211 /** 3212 * cvmx_pcieep#_cfg013 3213 * 3214 * This register contains the fourteenth 32-bits of PCIe type 0 configuration space. 3215 * 3216 */ 3217 union cvmx_pcieepx_cfg013 { 3218 u32 u32; 3219 struct cvmx_pcieepx_cfg013_s { 3220 u32 reserved_8_31 : 24; 3221 u32 cp : 8; 3222 } s; 3223 struct cvmx_pcieepx_cfg013_s cn52xx; 3224 struct cvmx_pcieepx_cfg013_s cn52xxp1; 3225 struct cvmx_pcieepx_cfg013_s cn56xx; 3226 struct cvmx_pcieepx_cfg013_s cn56xxp1; 3227 struct cvmx_pcieepx_cfg013_s cn61xx; 3228 struct cvmx_pcieepx_cfg013_s cn63xx; 3229 struct cvmx_pcieepx_cfg013_s cn63xxp1; 3230 struct cvmx_pcieepx_cfg013_s cn66xx; 3231 struct cvmx_pcieepx_cfg013_s cn68xx; 3232 struct cvmx_pcieepx_cfg013_s cn68xxp1; 3233 struct cvmx_pcieepx_cfg013_s cn70xx; 3234 struct cvmx_pcieepx_cfg013_s cn70xxp1; 3235 struct cvmx_pcieepx_cfg013_s cn73xx; 3236 struct cvmx_pcieepx_cfg013_s cn78xx; 3237 struct cvmx_pcieepx_cfg013_s cn78xxp1; 3238 struct cvmx_pcieepx_cfg013_s cnf71xx; 3239 struct cvmx_pcieepx_cfg013_s cnf75xx; 3240 }; 3241 3242 typedef union cvmx_pcieepx_cfg013 cvmx_pcieepx_cfg013_t; 3243 3244 /** 3245 * cvmx_pcieep#_cfg015 3246 * 3247 * This register contains the sixteenth 32-bits of PCIe type 0 configuration space. 3248 * 3249 */ 3250 union cvmx_pcieepx_cfg015 { 3251 u32 u32; 3252 struct cvmx_pcieepx_cfg015_s { 3253 u32 ml : 8; 3254 u32 mg : 8; 3255 u32 inta : 8; 3256 u32 il : 8; 3257 } s; 3258 struct cvmx_pcieepx_cfg015_s cn52xx; 3259 struct cvmx_pcieepx_cfg015_s cn52xxp1; 3260 struct cvmx_pcieepx_cfg015_s cn56xx; 3261 struct cvmx_pcieepx_cfg015_s cn56xxp1; 3262 struct cvmx_pcieepx_cfg015_s cn61xx; 3263 struct cvmx_pcieepx_cfg015_s cn63xx; 3264 struct cvmx_pcieepx_cfg015_s cn63xxp1; 3265 struct cvmx_pcieepx_cfg015_s cn66xx; 3266 struct cvmx_pcieepx_cfg015_s cn68xx; 3267 struct cvmx_pcieepx_cfg015_s cn68xxp1; 3268 struct cvmx_pcieepx_cfg015_s cn70xx; 3269 struct cvmx_pcieepx_cfg015_s cn70xxp1; 3270 struct cvmx_pcieepx_cfg015_s cn73xx; 3271 struct cvmx_pcieepx_cfg015_s cn78xx; 3272 struct cvmx_pcieepx_cfg015_s cn78xxp1; 3273 struct cvmx_pcieepx_cfg015_s cnf71xx; 3274 struct cvmx_pcieepx_cfg015_s cnf75xx; 3275 }; 3276 3277 typedef union cvmx_pcieepx_cfg015 cvmx_pcieepx_cfg015_t; 3278 3279 /** 3280 * cvmx_pcieep#_cfg016 3281 * 3282 * This register contains the seventeenth 32-bits of PCIe type 0 configuration space. 3283 * 3284 */ 3285 union cvmx_pcieepx_cfg016 { 3286 u32 u32; 3287 struct cvmx_pcieepx_cfg016_s { 3288 u32 pmes : 5; 3289 u32 d2s : 1; 3290 u32 d1s : 1; 3291 u32 auxc : 3; 3292 u32 dsi : 1; 3293 u32 reserved_20_20 : 1; 3294 u32 pme_clock : 1; 3295 u32 pmsv : 3; 3296 u32 ncp : 8; 3297 u32 pmcid : 8; 3298 } s; 3299 struct cvmx_pcieepx_cfg016_s cn52xx; 3300 struct cvmx_pcieepx_cfg016_s cn52xxp1; 3301 struct cvmx_pcieepx_cfg016_s cn56xx; 3302 struct cvmx_pcieepx_cfg016_s cn56xxp1; 3303 struct cvmx_pcieepx_cfg016_s cn61xx; 3304 struct cvmx_pcieepx_cfg016_s cn63xx; 3305 struct cvmx_pcieepx_cfg016_s cn63xxp1; 3306 struct cvmx_pcieepx_cfg016_s cn66xx; 3307 struct cvmx_pcieepx_cfg016_s cn68xx; 3308 struct cvmx_pcieepx_cfg016_s cn68xxp1; 3309 struct cvmx_pcieepx_cfg016_s cn70xx; 3310 struct cvmx_pcieepx_cfg016_s cn70xxp1; 3311 struct cvmx_pcieepx_cfg016_s cn73xx; 3312 struct cvmx_pcieepx_cfg016_s cn78xx; 3313 struct cvmx_pcieepx_cfg016_s cn78xxp1; 3314 struct cvmx_pcieepx_cfg016_s cnf71xx; 3315 struct cvmx_pcieepx_cfg016_s cnf75xx; 3316 }; 3317 3318 typedef union cvmx_pcieepx_cfg016 cvmx_pcieepx_cfg016_t; 3319 3320 /** 3321 * cvmx_pcieep#_cfg017 3322 * 3323 * This register contains the eighteenth 32-bits of PCIe type 0 configuration space. 3324 * 3325 */ 3326 union cvmx_pcieepx_cfg017 { 3327 u32 u32; 3328 struct cvmx_pcieepx_cfg017_s { 3329 u32 pmdia : 8; 3330 u32 bpccee : 1; 3331 u32 bd3h : 1; 3332 u32 reserved_16_21 : 6; 3333 u32 pmess : 1; 3334 u32 pmedsia : 2; 3335 u32 pmds : 4; 3336 u32 pmeens : 1; 3337 u32 reserved_4_7 : 4; 3338 u32 nsr : 1; 3339 u32 reserved_2_2 : 1; 3340 u32 ps : 2; 3341 } s; 3342 struct cvmx_pcieepx_cfg017_s cn52xx; 3343 struct cvmx_pcieepx_cfg017_s cn52xxp1; 3344 struct cvmx_pcieepx_cfg017_s cn56xx; 3345 struct cvmx_pcieepx_cfg017_s cn56xxp1; 3346 struct cvmx_pcieepx_cfg017_s cn61xx; 3347 struct cvmx_pcieepx_cfg017_s cn63xx; 3348 struct cvmx_pcieepx_cfg017_s cn63xxp1; 3349 struct cvmx_pcieepx_cfg017_s cn66xx; 3350 struct cvmx_pcieepx_cfg017_s cn68xx; 3351 struct cvmx_pcieepx_cfg017_s cn68xxp1; 3352 struct cvmx_pcieepx_cfg017_s cn70xx; 3353 struct cvmx_pcieepx_cfg017_s cn70xxp1; 3354 struct cvmx_pcieepx_cfg017_s cn73xx; 3355 struct cvmx_pcieepx_cfg017_s cn78xx; 3356 struct cvmx_pcieepx_cfg017_s cn78xxp1; 3357 struct cvmx_pcieepx_cfg017_s cnf71xx; 3358 struct cvmx_pcieepx_cfg017_s cnf75xx; 3359 }; 3360 3361 typedef union cvmx_pcieepx_cfg017 cvmx_pcieepx_cfg017_t; 3362 3363 /** 3364 * cvmx_pcieep#_cfg020 3365 * 3366 * This register contains the twenty-first 32-bits of PCIe type 0 configuration space. 3367 * 3368 */ 3369 union cvmx_pcieepx_cfg020 { 3370 u32 u32; 3371 struct cvmx_pcieepx_cfg020_s { 3372 u32 reserved_25_31 : 7; 3373 u32 pvm : 1; 3374 u32 m64 : 1; 3375 u32 mme : 3; 3376 u32 mmc : 3; 3377 u32 msien : 1; 3378 u32 ncp : 8; 3379 u32 msicid : 8; 3380 } s; 3381 struct cvmx_pcieepx_cfg020_cn52xx { 3382 u32 reserved_24_31 : 8; 3383 u32 m64 : 1; 3384 u32 mme : 3; 3385 u32 mmc : 3; 3386 u32 msien : 1; 3387 u32 ncp : 8; 3388 u32 msicid : 8; 3389 } cn52xx; 3390 struct cvmx_pcieepx_cfg020_cn52xx cn52xxp1; 3391 struct cvmx_pcieepx_cfg020_cn52xx cn56xx; 3392 struct cvmx_pcieepx_cfg020_cn52xx cn56xxp1; 3393 struct cvmx_pcieepx_cfg020_s cn61xx; 3394 struct cvmx_pcieepx_cfg020_cn52xx cn63xx; 3395 struct cvmx_pcieepx_cfg020_cn52xx cn63xxp1; 3396 struct cvmx_pcieepx_cfg020_s cn66xx; 3397 struct cvmx_pcieepx_cfg020_s cn68xx; 3398 struct cvmx_pcieepx_cfg020_s cn68xxp1; 3399 struct cvmx_pcieepx_cfg020_s cn70xx; 3400 struct cvmx_pcieepx_cfg020_s cn70xxp1; 3401 struct cvmx_pcieepx_cfg020_s cn73xx; 3402 struct cvmx_pcieepx_cfg020_s cn78xx; 3403 struct cvmx_pcieepx_cfg020_s cn78xxp1; 3404 struct cvmx_pcieepx_cfg020_s cnf71xx; 3405 struct cvmx_pcieepx_cfg020_s cnf75xx; 3406 }; 3407 3408 typedef union cvmx_pcieepx_cfg020 cvmx_pcieepx_cfg020_t; 3409 3410 /** 3411 * cvmx_pcieep#_cfg021 3412 * 3413 * This register contains the twenty-second 32-bits of PCIe type 0 configuration space. 3414 * 3415 */ 3416 union cvmx_pcieepx_cfg021 { 3417 u32 u32; 3418 struct cvmx_pcieepx_cfg021_s { 3419 u32 lmsi : 30; 3420 u32 reserved_0_1 : 2; 3421 } s; 3422 struct cvmx_pcieepx_cfg021_s cn52xx; 3423 struct cvmx_pcieepx_cfg021_s cn52xxp1; 3424 struct cvmx_pcieepx_cfg021_s cn56xx; 3425 struct cvmx_pcieepx_cfg021_s cn56xxp1; 3426 struct cvmx_pcieepx_cfg021_s cn61xx; 3427 struct cvmx_pcieepx_cfg021_s cn63xx; 3428 struct cvmx_pcieepx_cfg021_s cn63xxp1; 3429 struct cvmx_pcieepx_cfg021_s cn66xx; 3430 struct cvmx_pcieepx_cfg021_s cn68xx; 3431 struct cvmx_pcieepx_cfg021_s cn68xxp1; 3432 struct cvmx_pcieepx_cfg021_s cn70xx; 3433 struct cvmx_pcieepx_cfg021_s cn70xxp1; 3434 struct cvmx_pcieepx_cfg021_s cn73xx; 3435 struct cvmx_pcieepx_cfg021_s cn78xx; 3436 struct cvmx_pcieepx_cfg021_s cn78xxp1; 3437 struct cvmx_pcieepx_cfg021_s cnf71xx; 3438 struct cvmx_pcieepx_cfg021_s cnf75xx; 3439 }; 3440 3441 typedef union cvmx_pcieepx_cfg021 cvmx_pcieepx_cfg021_t; 3442 3443 /** 3444 * cvmx_pcieep#_cfg022 3445 * 3446 * This register contains the twenty-third 32-bits of PCIe type 0 configuration space. 3447 * 3448 */ 3449 union cvmx_pcieepx_cfg022 { 3450 u32 u32; 3451 struct cvmx_pcieepx_cfg022_s { 3452 u32 umsi : 32; 3453 } s; 3454 struct cvmx_pcieepx_cfg022_s cn52xx; 3455 struct cvmx_pcieepx_cfg022_s cn52xxp1; 3456 struct cvmx_pcieepx_cfg022_s cn56xx; 3457 struct cvmx_pcieepx_cfg022_s cn56xxp1; 3458 struct cvmx_pcieepx_cfg022_s cn61xx; 3459 struct cvmx_pcieepx_cfg022_s cn63xx; 3460 struct cvmx_pcieepx_cfg022_s cn63xxp1; 3461 struct cvmx_pcieepx_cfg022_s cn66xx; 3462 struct cvmx_pcieepx_cfg022_s cn68xx; 3463 struct cvmx_pcieepx_cfg022_s cn68xxp1; 3464 struct cvmx_pcieepx_cfg022_s cn70xx; 3465 struct cvmx_pcieepx_cfg022_s cn70xxp1; 3466 struct cvmx_pcieepx_cfg022_s cn73xx; 3467 struct cvmx_pcieepx_cfg022_s cn78xx; 3468 struct cvmx_pcieepx_cfg022_s cn78xxp1; 3469 struct cvmx_pcieepx_cfg022_s cnf71xx; 3470 struct cvmx_pcieepx_cfg022_s cnf75xx; 3471 }; 3472 3473 typedef union cvmx_pcieepx_cfg022 cvmx_pcieepx_cfg022_t; 3474 3475 /** 3476 * cvmx_pcieep#_cfg023 3477 * 3478 * This register contains the twenty-fourth 32-bits of PCIe type 0 configuration space. 3479 * 3480 */ 3481 union cvmx_pcieepx_cfg023 { 3482 u32 u32; 3483 struct cvmx_pcieepx_cfg023_s { 3484 u32 reserved_16_31 : 16; 3485 u32 msimd : 16; 3486 } s; 3487 struct cvmx_pcieepx_cfg023_s cn52xx; 3488 struct cvmx_pcieepx_cfg023_s cn52xxp1; 3489 struct cvmx_pcieepx_cfg023_s cn56xx; 3490 struct cvmx_pcieepx_cfg023_s cn56xxp1; 3491 struct cvmx_pcieepx_cfg023_s cn61xx; 3492 struct cvmx_pcieepx_cfg023_s cn63xx; 3493 struct cvmx_pcieepx_cfg023_s cn63xxp1; 3494 struct cvmx_pcieepx_cfg023_s cn66xx; 3495 struct cvmx_pcieepx_cfg023_s cn68xx; 3496 struct cvmx_pcieepx_cfg023_s cn68xxp1; 3497 struct cvmx_pcieepx_cfg023_s cn70xx; 3498 struct cvmx_pcieepx_cfg023_s cn70xxp1; 3499 struct cvmx_pcieepx_cfg023_s cn73xx; 3500 struct cvmx_pcieepx_cfg023_s cn78xx; 3501 struct cvmx_pcieepx_cfg023_s cn78xxp1; 3502 struct cvmx_pcieepx_cfg023_s cnf71xx; 3503 struct cvmx_pcieepx_cfg023_s cnf75xx; 3504 }; 3505 3506 typedef union cvmx_pcieepx_cfg023 cvmx_pcieepx_cfg023_t; 3507 3508 /** 3509 * cvmx_pcieep#_cfg024 3510 * 3511 * This register contains the twenty-fifth 32-bits of PCIe type 0 configuration space. 3512 * 3513 */ 3514 union cvmx_pcieepx_cfg024 { 3515 u32 u32; 3516 struct cvmx_pcieepx_cfg024_s { 3517 u32 msimm : 32; 3518 } s; 3519 struct cvmx_pcieepx_cfg024_s cn70xx; 3520 struct cvmx_pcieepx_cfg024_s cn70xxp1; 3521 struct cvmx_pcieepx_cfg024_s cn73xx; 3522 struct cvmx_pcieepx_cfg024_s cn78xx; 3523 struct cvmx_pcieepx_cfg024_s cn78xxp1; 3524 struct cvmx_pcieepx_cfg024_s cnf75xx; 3525 }; 3526 3527 typedef union cvmx_pcieepx_cfg024 cvmx_pcieepx_cfg024_t; 3528 3529 /** 3530 * cvmx_pcieep#_cfg025 3531 * 3532 * This register contains the twenty-sixth 32-bits of PCIe type 0 configuration space. 3533 * 3534 */ 3535 union cvmx_pcieepx_cfg025 { 3536 u32 u32; 3537 struct cvmx_pcieepx_cfg025_s { 3538 u32 msimp : 32; 3539 } s; 3540 struct cvmx_pcieepx_cfg025_s cn70xx; 3541 struct cvmx_pcieepx_cfg025_s cn70xxp1; 3542 struct cvmx_pcieepx_cfg025_s cn73xx; 3543 struct cvmx_pcieepx_cfg025_s cn78xx; 3544 struct cvmx_pcieepx_cfg025_s cn78xxp1; 3545 struct cvmx_pcieepx_cfg025_s cnf75xx; 3546 }; 3547 3548 typedef union cvmx_pcieepx_cfg025 cvmx_pcieepx_cfg025_t; 3549 3550 /** 3551 * cvmx_pcieep#_cfg028 3552 * 3553 * This register contains the twenty-ninth 32-bits of PCIe type 0 configuration space. 3554 * 3555 */ 3556 union cvmx_pcieepx_cfg028 { 3557 u32 u32; 3558 struct cvmx_pcieepx_cfg028_s { 3559 u32 reserved_30_31 : 2; 3560 u32 imn : 5; 3561 u32 si : 1; 3562 u32 dpt : 4; 3563 u32 pciecv : 4; 3564 u32 ncp : 8; 3565 u32 pcieid : 8; 3566 } s; 3567 struct cvmx_pcieepx_cfg028_s cn52xx; 3568 struct cvmx_pcieepx_cfg028_s cn52xxp1; 3569 struct cvmx_pcieepx_cfg028_s cn56xx; 3570 struct cvmx_pcieepx_cfg028_s cn56xxp1; 3571 struct cvmx_pcieepx_cfg028_s cn61xx; 3572 struct cvmx_pcieepx_cfg028_s cn63xx; 3573 struct cvmx_pcieepx_cfg028_s cn63xxp1; 3574 struct cvmx_pcieepx_cfg028_s cn66xx; 3575 struct cvmx_pcieepx_cfg028_s cn68xx; 3576 struct cvmx_pcieepx_cfg028_s cn68xxp1; 3577 struct cvmx_pcieepx_cfg028_s cn70xx; 3578 struct cvmx_pcieepx_cfg028_s cn70xxp1; 3579 struct cvmx_pcieepx_cfg028_s cn73xx; 3580 struct cvmx_pcieepx_cfg028_s cn78xx; 3581 struct cvmx_pcieepx_cfg028_s cn78xxp1; 3582 struct cvmx_pcieepx_cfg028_s cnf71xx; 3583 struct cvmx_pcieepx_cfg028_s cnf75xx; 3584 }; 3585 3586 typedef union cvmx_pcieepx_cfg028 cvmx_pcieepx_cfg028_t; 3587 3588 /** 3589 * cvmx_pcieep#_cfg029 3590 * 3591 * This register contains the thirtieth 32-bits of PCIe type 0 configuration space. 3592 * 3593 */ 3594 union cvmx_pcieepx_cfg029 { 3595 u32 u32; 3596 struct cvmx_pcieepx_cfg029_s { 3597 u32 reserved_28_31 : 4; 3598 u32 cspls : 2; 3599 u32 csplv : 8; 3600 u32 reserved_16_17 : 2; 3601 u32 rber : 1; 3602 u32 reserved_12_14 : 3; 3603 u32 el1al : 3; 3604 u32 el0al : 3; 3605 u32 etfs : 1; 3606 u32 pfs : 2; 3607 u32 mpss : 3; 3608 } s; 3609 struct cvmx_pcieepx_cfg029_s cn52xx; 3610 struct cvmx_pcieepx_cfg029_s cn52xxp1; 3611 struct cvmx_pcieepx_cfg029_s cn56xx; 3612 struct cvmx_pcieepx_cfg029_s cn56xxp1; 3613 struct cvmx_pcieepx_cfg029_cn61xx { 3614 u32 reserved_29_31 : 3; 3615 u32 flr_cap : 1; 3616 u32 cspls : 2; 3617 u32 csplv : 8; 3618 u32 reserved_16_17 : 2; 3619 u32 rber : 1; 3620 u32 reserved_12_14 : 3; 3621 u32 el1al : 3; 3622 u32 el0al : 3; 3623 u32 etfs : 1; 3624 u32 pfs : 2; 3625 u32 mpss : 3; 3626 } cn61xx; 3627 struct cvmx_pcieepx_cfg029_s cn63xx; 3628 struct cvmx_pcieepx_cfg029_s cn63xxp1; 3629 struct cvmx_pcieepx_cfg029_cn66xx { 3630 u32 reserved_29_31 : 3; 3631 u32 flr : 1; 3632 u32 cspls : 2; 3633 u32 csplv : 8; 3634 u32 reserved_16_17 : 2; 3635 u32 rber : 1; 3636 u32 reserved_12_14 : 3; 3637 u32 el1al : 3; 3638 u32 el0al : 3; 3639 u32 etfs : 1; 3640 u32 pfs : 2; 3641 u32 mpss : 3; 3642 } cn66xx; 3643 struct cvmx_pcieepx_cfg029_cn66xx cn68xx; 3644 struct cvmx_pcieepx_cfg029_cn66xx cn68xxp1; 3645 struct cvmx_pcieepx_cfg029_cn61xx cn70xx; 3646 struct cvmx_pcieepx_cfg029_cn61xx cn70xxp1; 3647 struct cvmx_pcieepx_cfg029_cn61xx cn73xx; 3648 struct cvmx_pcieepx_cfg029_cn61xx cn78xx; 3649 struct cvmx_pcieepx_cfg029_cn61xx cn78xxp1; 3650 struct cvmx_pcieepx_cfg029_cn61xx cnf71xx; 3651 struct cvmx_pcieepx_cfg029_cn61xx cnf75xx; 3652 }; 3653 3654 typedef union cvmx_pcieepx_cfg029 cvmx_pcieepx_cfg029_t; 3655 3656 /** 3657 * cvmx_pcieep#_cfg030 3658 * 3659 * This register contains the thirty-first 32-bits of PCIe type 0 configuration space. 3660 * 3661 */ 3662 union cvmx_pcieepx_cfg030 { 3663 u32 u32; 3664 struct cvmx_pcieepx_cfg030_s { 3665 u32 reserved_22_31 : 10; 3666 u32 tp : 1; 3667 u32 ap_d : 1; 3668 u32 ur_d : 1; 3669 u32 fe_d : 1; 3670 u32 nfe_d : 1; 3671 u32 ce_d : 1; 3672 u32 i_flr : 1; 3673 u32 mrrs : 3; 3674 u32 ns_en : 1; 3675 u32 ap_en : 1; 3676 u32 pf_en : 1; 3677 u32 etf_en : 1; 3678 u32 mps : 3; 3679 u32 ro_en : 1; 3680 u32 ur_en : 1; 3681 u32 fe_en : 1; 3682 u32 nfe_en : 1; 3683 u32 ce_en : 1; 3684 } s; 3685 struct cvmx_pcieepx_cfg030_cn52xx { 3686 u32 reserved_22_31 : 10; 3687 u32 tp : 1; 3688 u32 ap_d : 1; 3689 u32 ur_d : 1; 3690 u32 fe_d : 1; 3691 u32 nfe_d : 1; 3692 u32 ce_d : 1; 3693 u32 reserved_15_15 : 1; 3694 u32 mrrs : 3; 3695 u32 ns_en : 1; 3696 u32 ap_en : 1; 3697 u32 pf_en : 1; 3698 u32 etf_en : 1; 3699 u32 mps : 3; 3700 u32 ro_en : 1; 3701 u32 ur_en : 1; 3702 u32 fe_en : 1; 3703 u32 nfe_en : 1; 3704 u32 ce_en : 1; 3705 } cn52xx; 3706 struct cvmx_pcieepx_cfg030_cn52xx cn52xxp1; 3707 struct cvmx_pcieepx_cfg030_cn52xx cn56xx; 3708 struct cvmx_pcieepx_cfg030_cn52xx cn56xxp1; 3709 struct cvmx_pcieepx_cfg030_s cn61xx; 3710 struct cvmx_pcieepx_cfg030_cn52xx cn63xx; 3711 struct cvmx_pcieepx_cfg030_cn52xx cn63xxp1; 3712 struct cvmx_pcieepx_cfg030_s cn66xx; 3713 struct cvmx_pcieepx_cfg030_s cn68xx; 3714 struct cvmx_pcieepx_cfg030_s cn68xxp1; 3715 struct cvmx_pcieepx_cfg030_s cn70xx; 3716 struct cvmx_pcieepx_cfg030_s cn70xxp1; 3717 struct cvmx_pcieepx_cfg030_s cn73xx; 3718 struct cvmx_pcieepx_cfg030_s cn78xx; 3719 struct cvmx_pcieepx_cfg030_s cn78xxp1; 3720 struct cvmx_pcieepx_cfg030_s cnf71xx; 3721 struct cvmx_pcieepx_cfg030_s cnf75xx; 3722 }; 3723 3724 typedef union cvmx_pcieepx_cfg030 cvmx_pcieepx_cfg030_t; 3725 3726 /** 3727 * cvmx_pcieep#_cfg031 3728 * 3729 * This register contains the thirty-second 32-bits of PCIe type 0 configuration space. 3730 * 3731 */ 3732 union cvmx_pcieepx_cfg031 { 3733 u32 u32; 3734 struct cvmx_pcieepx_cfg031_s { 3735 u32 pnum : 8; 3736 u32 reserved_23_23 : 1; 3737 u32 aspm : 1; 3738 u32 lbnc : 1; 3739 u32 dllarc : 1; 3740 u32 sderc : 1; 3741 u32 cpm : 1; 3742 u32 l1el : 3; 3743 u32 l0el : 3; 3744 u32 aslpms : 2; 3745 u32 mlw : 6; 3746 u32 mls : 4; 3747 } s; 3748 struct cvmx_pcieepx_cfg031_cn52xx { 3749 u32 pnum : 8; 3750 u32 reserved_22_23 : 2; 3751 u32 lbnc : 1; 3752 u32 dllarc : 1; 3753 u32 sderc : 1; 3754 u32 cpm : 1; 3755 u32 l1el : 3; 3756 u32 l0el : 3; 3757 u32 aslpms : 2; 3758 u32 mlw : 6; 3759 u32 mls : 4; 3760 } cn52xx; 3761 struct cvmx_pcieepx_cfg031_cn52xx cn52xxp1; 3762 struct cvmx_pcieepx_cfg031_cn52xx cn56xx; 3763 struct cvmx_pcieepx_cfg031_cn52xx cn56xxp1; 3764 struct cvmx_pcieepx_cfg031_s cn61xx; 3765 struct cvmx_pcieepx_cfg031_cn52xx cn63xx; 3766 struct cvmx_pcieepx_cfg031_cn52xx cn63xxp1; 3767 struct cvmx_pcieepx_cfg031_s cn66xx; 3768 struct cvmx_pcieepx_cfg031_s cn68xx; 3769 struct cvmx_pcieepx_cfg031_cn52xx cn68xxp1; 3770 struct cvmx_pcieepx_cfg031_s cn70xx; 3771 struct cvmx_pcieepx_cfg031_s cn70xxp1; 3772 struct cvmx_pcieepx_cfg031_s cn73xx; 3773 struct cvmx_pcieepx_cfg031_s cn78xx; 3774 struct cvmx_pcieepx_cfg031_s cn78xxp1; 3775 struct cvmx_pcieepx_cfg031_s cnf71xx; 3776 struct cvmx_pcieepx_cfg031_s cnf75xx; 3777 }; 3778 3779 typedef union cvmx_pcieepx_cfg031 cvmx_pcieepx_cfg031_t; 3780 3781 /** 3782 * cvmx_pcieep#_cfg032 3783 * 3784 * This register contains the thirty-third 32-bits of PCIe type 0 configuration space. 3785 * 3786 */ 3787 union cvmx_pcieepx_cfg032 { 3788 u32 u32; 3789 struct cvmx_pcieepx_cfg032_s { 3790 u32 lab : 1; 3791 u32 lbm : 1; 3792 u32 dlla : 1; 3793 u32 scc : 1; 3794 u32 lt : 1; 3795 u32 reserved_26_26 : 1; 3796 u32 nlw : 6; 3797 u32 ls : 4; 3798 u32 reserved_12_15 : 4; 3799 u32 lab_int_enb : 1; 3800 u32 lbm_int_enb : 1; 3801 u32 hawd : 1; 3802 u32 ecpm : 1; 3803 u32 es : 1; 3804 u32 ccc : 1; 3805 u32 rl : 1; 3806 u32 ld : 1; 3807 u32 rcb : 1; 3808 u32 reserved_2_2 : 1; 3809 u32 aslpc : 2; 3810 } s; 3811 struct cvmx_pcieepx_cfg032_cn52xx { 3812 u32 reserved_30_31 : 2; 3813 u32 dlla : 1; 3814 u32 scc : 1; 3815 u32 lt : 1; 3816 u32 reserved_26_26 : 1; 3817 u32 nlw : 6; 3818 u32 ls : 4; 3819 u32 reserved_10_15 : 6; 3820 u32 hawd : 1; 3821 u32 ecpm : 1; 3822 u32 es : 1; 3823 u32 ccc : 1; 3824 u32 rl : 1; 3825 u32 ld : 1; 3826 u32 rcb : 1; 3827 u32 reserved_2_2 : 1; 3828 u32 aslpc : 2; 3829 } cn52xx; 3830 struct cvmx_pcieepx_cfg032_cn52xx cn52xxp1; 3831 struct cvmx_pcieepx_cfg032_cn52xx cn56xx; 3832 struct cvmx_pcieepx_cfg032_cn52xx cn56xxp1; 3833 struct cvmx_pcieepx_cfg032_s cn61xx; 3834 struct cvmx_pcieepx_cfg032_cn52xx cn63xx; 3835 struct cvmx_pcieepx_cfg032_cn52xx cn63xxp1; 3836 struct cvmx_pcieepx_cfg032_s cn66xx; 3837 struct cvmx_pcieepx_cfg032_s cn68xx; 3838 struct cvmx_pcieepx_cfg032_cn68xxp1 { 3839 u32 reserved_30_31 : 2; 3840 u32 dlla : 1; 3841 u32 scc : 1; 3842 u32 lt : 1; 3843 u32 reserved_26_26 : 1; 3844 u32 nlw : 6; 3845 u32 ls : 4; 3846 u32 reserved_12_15 : 4; 3847 u32 lab_int_enb : 1; 3848 u32 lbm_int_enb : 1; 3849 u32 hawd : 1; 3850 u32 ecpm : 1; 3851 u32 es : 1; 3852 u32 ccc : 1; 3853 u32 rl : 1; 3854 u32 ld : 1; 3855 u32 rcb : 1; 3856 u32 reserved_2_2 : 1; 3857 u32 aslpc : 2; 3858 } cn68xxp1; 3859 struct cvmx_pcieepx_cfg032_s cn70xx; 3860 struct cvmx_pcieepx_cfg032_s cn70xxp1; 3861 struct cvmx_pcieepx_cfg032_s cn73xx; 3862 struct cvmx_pcieepx_cfg032_s cn78xx; 3863 struct cvmx_pcieepx_cfg032_s cn78xxp1; 3864 struct cvmx_pcieepx_cfg032_s cnf71xx; 3865 struct cvmx_pcieepx_cfg032_s cnf75xx; 3866 }; 3867 3868 typedef union cvmx_pcieepx_cfg032 cvmx_pcieepx_cfg032_t; 3869 3870 /** 3871 * cvmx_pcieep#_cfg033 3872 * 3873 * PCIE_CFG033 = Thirty-fourth 32-bits of PCIE type 0 config space 3874 * (Slot Capabilities Register) 3875 */ 3876 union cvmx_pcieepx_cfg033 { 3877 u32 u32; 3878 struct cvmx_pcieepx_cfg033_s { 3879 u32 ps_num : 13; 3880 u32 nccs : 1; 3881 u32 emip : 1; 3882 u32 sp_ls : 2; 3883 u32 sp_lv : 8; 3884 u32 hp_c : 1; 3885 u32 hp_s : 1; 3886 u32 pip : 1; 3887 u32 aip : 1; 3888 u32 mrlsp : 1; 3889 u32 pcp : 1; 3890 u32 abp : 1; 3891 } s; 3892 struct cvmx_pcieepx_cfg033_s cn52xx; 3893 struct cvmx_pcieepx_cfg033_s cn52xxp1; 3894 struct cvmx_pcieepx_cfg033_s cn56xx; 3895 struct cvmx_pcieepx_cfg033_s cn56xxp1; 3896 struct cvmx_pcieepx_cfg033_s cn63xx; 3897 struct cvmx_pcieepx_cfg033_s cn63xxp1; 3898 }; 3899 3900 typedef union cvmx_pcieepx_cfg033 cvmx_pcieepx_cfg033_t; 3901 3902 /** 3903 * cvmx_pcieep#_cfg034 3904 * 3905 * PCIE_CFG034 = Thirty-fifth 32-bits of PCIE type 0 config space 3906 * (Slot Control Register/Slot Status Register) 3907 */ 3908 union cvmx_pcieepx_cfg034 { 3909 u32 u32; 3910 struct cvmx_pcieepx_cfg034_s { 3911 u32 reserved_25_31 : 7; 3912 u32 dlls_c : 1; 3913 u32 emis : 1; 3914 u32 pds : 1; 3915 u32 mrlss : 1; 3916 u32 ccint_d : 1; 3917 u32 pd_c : 1; 3918 u32 mrls_c : 1; 3919 u32 pf_d : 1; 3920 u32 abp_d : 1; 3921 u32 reserved_13_15 : 3; 3922 u32 dlls_en : 1; 3923 u32 emic : 1; 3924 u32 pcc : 1; 3925 u32 pic : 2; 3926 u32 aic : 2; 3927 u32 hpint_en : 1; 3928 u32 ccint_en : 1; 3929 u32 pd_en : 1; 3930 u32 mrls_en : 1; 3931 u32 pf_en : 1; 3932 u32 abp_en : 1; 3933 } s; 3934 struct cvmx_pcieepx_cfg034_s cn52xx; 3935 struct cvmx_pcieepx_cfg034_s cn52xxp1; 3936 struct cvmx_pcieepx_cfg034_s cn56xx; 3937 struct cvmx_pcieepx_cfg034_s cn56xxp1; 3938 struct cvmx_pcieepx_cfg034_s cn63xx; 3939 struct cvmx_pcieepx_cfg034_s cn63xxp1; 3940 }; 3941 3942 typedef union cvmx_pcieepx_cfg034 cvmx_pcieepx_cfg034_t; 3943 3944 /** 3945 * cvmx_pcieep#_cfg037 3946 * 3947 * This register contains the thirty-eighth 32-bits of PCIe type 0 configuration space. 3948 * 3949 */ 3950 union cvmx_pcieepx_cfg037 { 3951 u32 u32; 3952 struct cvmx_pcieepx_cfg037_s { 3953 u32 reserved_24_31 : 8; 3954 u32 meetp : 2; 3955 u32 eetps : 1; 3956 u32 effs : 1; 3957 u32 obffs : 2; 3958 u32 reserved_12_17 : 6; 3959 u32 ltrs : 1; 3960 u32 noroprpr : 1; 3961 u32 atom128s : 1; 3962 u32 atom64s : 1; 3963 u32 atom32s : 1; 3964 u32 atom_ops : 1; 3965 u32 ari : 1; 3966 u32 ctds : 1; 3967 u32 ctrs : 4; 3968 } s; 3969 struct cvmx_pcieepx_cfg037_cn52xx { 3970 u32 reserved_5_31 : 27; 3971 u32 ctds : 1; 3972 u32 ctrs : 4; 3973 } cn52xx; 3974 struct cvmx_pcieepx_cfg037_cn52xx cn52xxp1; 3975 struct cvmx_pcieepx_cfg037_cn52xx cn56xx; 3976 struct cvmx_pcieepx_cfg037_cn52xx cn56xxp1; 3977 struct cvmx_pcieepx_cfg037_cn61xx { 3978 u32 reserved_14_31 : 18; 3979 u32 tph : 2; 3980 u32 reserved_11_11 : 1; 3981 u32 noroprpr : 1; 3982 u32 atom128s : 1; 3983 u32 atom64s : 1; 3984 u32 atom32s : 1; 3985 u32 atom_ops : 1; 3986 u32 ari : 1; 3987 u32 ctds : 1; 3988 u32 ctrs : 4; 3989 } cn61xx; 3990 struct cvmx_pcieepx_cfg037_cn52xx cn63xx; 3991 struct cvmx_pcieepx_cfg037_cn52xx cn63xxp1; 3992 struct cvmx_pcieepx_cfg037_cn61xx cn66xx; 3993 struct cvmx_pcieepx_cfg037_cn61xx cn68xx; 3994 struct cvmx_pcieepx_cfg037_cn61xx cn68xxp1; 3995 struct cvmx_pcieepx_cfg037_cn61xx cn70xx; 3996 struct cvmx_pcieepx_cfg037_cn61xx cn70xxp1; 3997 struct cvmx_pcieepx_cfg037_cn73xx { 3998 u32 reserved_24_31 : 8; 3999 u32 meetp : 2; 4000 u32 eetps : 1; 4001 u32 effs : 1; 4002 u32 obffs : 2; 4003 u32 reserved_14_17 : 4; 4004 u32 tphs : 2; 4005 u32 ltrs : 1; 4006 u32 noroprpr : 1; 4007 u32 atom128s : 1; 4008 u32 atom64s : 1; 4009 u32 atom32s : 1; 4010 u32 atom_ops : 1; 4011 u32 ari : 1; 4012 u32 ctds : 1; 4013 u32 ctrs : 4; 4014 } cn73xx; 4015 struct cvmx_pcieepx_cfg037_cn73xx cn78xx; 4016 struct cvmx_pcieepx_cfg037_cn73xx cn78xxp1; 4017 struct cvmx_pcieepx_cfg037_cnf71xx { 4018 u32 reserved_20_31 : 12; 4019 u32 obffs : 2; 4020 u32 reserved_14_17 : 4; 4021 u32 tphs : 2; 4022 u32 ltrs : 1; 4023 u32 noroprpr : 1; 4024 u32 atom128s : 1; 4025 u32 atom64s : 1; 4026 u32 atom32s : 1; 4027 u32 atom_ops : 1; 4028 u32 ari : 1; 4029 u32 ctds : 1; 4030 u32 ctrs : 4; 4031 } cnf71xx; 4032 struct cvmx_pcieepx_cfg037_cn73xx cnf75xx; 4033 }; 4034 4035 typedef union cvmx_pcieepx_cfg037 cvmx_pcieepx_cfg037_t; 4036 4037 /** 4038 * cvmx_pcieep#_cfg038 4039 * 4040 * This register contains the thirty-ninth 32-bits of PCIe type 0 configuration space. 4041 * 4042 */ 4043 union cvmx_pcieepx_cfg038 { 4044 u32 u32; 4045 struct cvmx_pcieepx_cfg038_s { 4046 u32 reserved_16_31 : 16; 4047 u32 eetpb : 1; 4048 u32 obffe : 2; 4049 u32 reserved_11_12 : 2; 4050 u32 ltre : 1; 4051 u32 id0_cp : 1; 4052 u32 id0_rq : 1; 4053 u32 atom_op_eb : 1; 4054 u32 atom_op : 1; 4055 u32 ari : 1; 4056 u32 ctd : 1; 4057 u32 ctv : 4; 4058 } s; 4059 struct cvmx_pcieepx_cfg038_cn52xx { 4060 u32 reserved_5_31 : 27; 4061 u32 ctd : 1; 4062 u32 ctv : 4; 4063 } cn52xx; 4064 struct cvmx_pcieepx_cfg038_cn52xx cn52xxp1; 4065 struct cvmx_pcieepx_cfg038_cn52xx cn56xx; 4066 struct cvmx_pcieepx_cfg038_cn52xx cn56xxp1; 4067 struct cvmx_pcieepx_cfg038_cn61xx { 4068 u32 reserved_10_31 : 22; 4069 u32 id0_cp : 1; 4070 u32 id0_rq : 1; 4071 u32 atom_op_eb : 1; 4072 u32 atom_op : 1; 4073 u32 ari : 1; 4074 u32 ctd : 1; 4075 u32 ctv : 4; 4076 } cn61xx; 4077 struct cvmx_pcieepx_cfg038_cn52xx cn63xx; 4078 struct cvmx_pcieepx_cfg038_cn52xx cn63xxp1; 4079 struct cvmx_pcieepx_cfg038_cn61xx cn66xx; 4080 struct cvmx_pcieepx_cfg038_cn61xx cn68xx; 4081 struct cvmx_pcieepx_cfg038_cn61xx cn68xxp1; 4082 struct cvmx_pcieepx_cfg038_cn61xx cn70xx; 4083 struct cvmx_pcieepx_cfg038_cn61xx cn70xxp1; 4084 struct cvmx_pcieepx_cfg038_s cn73xx; 4085 struct cvmx_pcieepx_cfg038_s cn78xx; 4086 struct cvmx_pcieepx_cfg038_s cn78xxp1; 4087 struct cvmx_pcieepx_cfg038_cnf71xx { 4088 u32 reserved_15_31 : 17; 4089 u32 obffe : 2; 4090 u32 reserved_11_12 : 2; 4091 u32 ltre : 1; 4092 u32 id0_cp : 1; 4093 u32 id0_rq : 1; 4094 u32 atom_op_eb : 1; 4095 u32 atom_op : 1; 4096 u32 ari : 1; 4097 u32 ctd : 1; 4098 u32 ctv : 4; 4099 } cnf71xx; 4100 struct cvmx_pcieepx_cfg038_s cnf75xx; 4101 }; 4102 4103 typedef union cvmx_pcieepx_cfg038 cvmx_pcieepx_cfg038_t; 4104 4105 /** 4106 * cvmx_pcieep#_cfg039 4107 * 4108 * This register contains the fortieth 32-bits of PCIe type 0 configuration space. 4109 * 4110 */ 4111 union cvmx_pcieepx_cfg039 { 4112 u32 u32; 4113 struct cvmx_pcieepx_cfg039_s { 4114 u32 reserved_9_31 : 23; 4115 u32 cls : 1; 4116 u32 slsv : 7; 4117 u32 reserved_0_0 : 1; 4118 } s; 4119 struct cvmx_pcieepx_cfg039_cn52xx { 4120 u32 reserved_0_31 : 32; 4121 } cn52xx; 4122 struct cvmx_pcieepx_cfg039_cn52xx cn52xxp1; 4123 struct cvmx_pcieepx_cfg039_cn52xx cn56xx; 4124 struct cvmx_pcieepx_cfg039_cn52xx cn56xxp1; 4125 struct cvmx_pcieepx_cfg039_s cn61xx; 4126 struct cvmx_pcieepx_cfg039_s cn63xx; 4127 struct cvmx_pcieepx_cfg039_cn52xx cn63xxp1; 4128 struct cvmx_pcieepx_cfg039_s cn66xx; 4129 struct cvmx_pcieepx_cfg039_s cn68xx; 4130 struct cvmx_pcieepx_cfg039_s cn68xxp1; 4131 struct cvmx_pcieepx_cfg039_s cn70xx; 4132 struct cvmx_pcieepx_cfg039_s cn70xxp1; 4133 struct cvmx_pcieepx_cfg039_s cn73xx; 4134 struct cvmx_pcieepx_cfg039_s cn78xx; 4135 struct cvmx_pcieepx_cfg039_s cn78xxp1; 4136 struct cvmx_pcieepx_cfg039_s cnf71xx; 4137 struct cvmx_pcieepx_cfg039_s cnf75xx; 4138 }; 4139 4140 typedef union cvmx_pcieepx_cfg039 cvmx_pcieepx_cfg039_t; 4141 4142 /** 4143 * cvmx_pcieep#_cfg040 4144 * 4145 * This register contains the forty-first 32-bits of PCIe type 0 configuration space. 4146 * 4147 */ 4148 union cvmx_pcieepx_cfg040 { 4149 u32 u32; 4150 struct cvmx_pcieepx_cfg040_s { 4151 u32 reserved_22_31 : 10; 4152 u32 ler : 1; 4153 u32 ep3s : 1; 4154 u32 ep2s : 1; 4155 u32 ep1s : 1; 4156 u32 eqc : 1; 4157 u32 cdl : 1; 4158 u32 cde : 4; 4159 u32 csos : 1; 4160 u32 emc : 1; 4161 u32 tm : 3; 4162 u32 sde : 1; 4163 u32 hasd : 1; 4164 u32 ec : 1; 4165 u32 tls : 4; 4166 } s; 4167 struct cvmx_pcieepx_cfg040_cn52xx { 4168 u32 reserved_0_31 : 32; 4169 } cn52xx; 4170 struct cvmx_pcieepx_cfg040_cn52xx cn52xxp1; 4171 struct cvmx_pcieepx_cfg040_cn52xx cn56xx; 4172 struct cvmx_pcieepx_cfg040_cn52xx cn56xxp1; 4173 struct cvmx_pcieepx_cfg040_cn61xx { 4174 u32 reserved_17_31 : 15; 4175 u32 cdl : 1; 4176 u32 reserved_13_15 : 3; 4177 u32 cde : 1; 4178 u32 csos : 1; 4179 u32 emc : 1; 4180 u32 tm : 3; 4181 u32 sde : 1; 4182 u32 hasd : 1; 4183 u32 ec : 1; 4184 u32 tls : 4; 4185 } cn61xx; 4186 struct cvmx_pcieepx_cfg040_cn61xx cn63xx; 4187 struct cvmx_pcieepx_cfg040_cn61xx cn63xxp1; 4188 struct cvmx_pcieepx_cfg040_cn61xx cn66xx; 4189 struct cvmx_pcieepx_cfg040_cn61xx cn68xx; 4190 struct cvmx_pcieepx_cfg040_cn61xx cn68xxp1; 4191 struct cvmx_pcieepx_cfg040_cn61xx cn70xx; 4192 struct cvmx_pcieepx_cfg040_cn61xx cn70xxp1; 4193 struct cvmx_pcieepx_cfg040_s cn73xx; 4194 struct cvmx_pcieepx_cfg040_s cn78xx; 4195 struct cvmx_pcieepx_cfg040_s cn78xxp1; 4196 struct cvmx_pcieepx_cfg040_cn61xx cnf71xx; 4197 struct cvmx_pcieepx_cfg040_s cnf75xx; 4198 }; 4199 4200 typedef union cvmx_pcieepx_cfg040 cvmx_pcieepx_cfg040_t; 4201 4202 /** 4203 * cvmx_pcieep#_cfg041 4204 * 4205 * PCIE_CFG041 = Fourty-second 32-bits of PCIE type 0 config space 4206 * (Slot Capabilities 2 Register) 4207 */ 4208 union cvmx_pcieepx_cfg041 { 4209 u32 u32; 4210 struct cvmx_pcieepx_cfg041_s { 4211 u32 reserved_0_31 : 32; 4212 } s; 4213 struct cvmx_pcieepx_cfg041_s cn52xx; 4214 struct cvmx_pcieepx_cfg041_s cn52xxp1; 4215 struct cvmx_pcieepx_cfg041_s cn56xx; 4216 struct cvmx_pcieepx_cfg041_s cn56xxp1; 4217 struct cvmx_pcieepx_cfg041_s cn63xx; 4218 struct cvmx_pcieepx_cfg041_s cn63xxp1; 4219 }; 4220 4221 typedef union cvmx_pcieepx_cfg041 cvmx_pcieepx_cfg041_t; 4222 4223 /** 4224 * cvmx_pcieep#_cfg042 4225 * 4226 * PCIE_CFG042 = Fourty-third 32-bits of PCIE type 0 config space 4227 * (Slot Control 2 Register/Slot Status 2 Register) 4228 */ 4229 union cvmx_pcieepx_cfg042 { 4230 u32 u32; 4231 struct cvmx_pcieepx_cfg042_s { 4232 u32 reserved_0_31 : 32; 4233 } s; 4234 struct cvmx_pcieepx_cfg042_s cn52xx; 4235 struct cvmx_pcieepx_cfg042_s cn52xxp1; 4236 struct cvmx_pcieepx_cfg042_s cn56xx; 4237 struct cvmx_pcieepx_cfg042_s cn56xxp1; 4238 struct cvmx_pcieepx_cfg042_s cn63xx; 4239 struct cvmx_pcieepx_cfg042_s cn63xxp1; 4240 }; 4241 4242 typedef union cvmx_pcieepx_cfg042 cvmx_pcieepx_cfg042_t; 4243 4244 /** 4245 * cvmx_pcieep#_cfg044 4246 * 4247 * This register contains the forty-fifth 32-bits of PCIe type 0 configuration space. 4248 * 4249 */ 4250 union cvmx_pcieepx_cfg044 { 4251 u32 u32; 4252 struct cvmx_pcieepx_cfg044_s { 4253 u32 msixen : 1; 4254 u32 funm : 1; 4255 u32 reserved_27_29 : 3; 4256 u32 msixts : 11; 4257 u32 ncp : 8; 4258 u32 msixcid : 8; 4259 } s; 4260 struct cvmx_pcieepx_cfg044_s cn73xx; 4261 struct cvmx_pcieepx_cfg044_s cn78xx; 4262 struct cvmx_pcieepx_cfg044_s cn78xxp1; 4263 struct cvmx_pcieepx_cfg044_s cnf75xx; 4264 }; 4265 4266 typedef union cvmx_pcieepx_cfg044 cvmx_pcieepx_cfg044_t; 4267 4268 /** 4269 * cvmx_pcieep#_cfg045 4270 * 4271 * This register contains the forty-sixth 32-bits of PCIe type 0 configuration space. 4272 * 4273 */ 4274 union cvmx_pcieepx_cfg045 { 4275 u32 u32; 4276 struct cvmx_pcieepx_cfg045_s { 4277 u32 msixtoffs : 29; 4278 u32 msixtbir : 3; 4279 } s; 4280 struct cvmx_pcieepx_cfg045_s cn73xx; 4281 struct cvmx_pcieepx_cfg045_s cn78xx; 4282 struct cvmx_pcieepx_cfg045_s cn78xxp1; 4283 struct cvmx_pcieepx_cfg045_s cnf75xx; 4284 }; 4285 4286 typedef union cvmx_pcieepx_cfg045 cvmx_pcieepx_cfg045_t; 4287 4288 /** 4289 * cvmx_pcieep#_cfg046 4290 * 4291 * This register contains the forty-seventh 32-bits of PCIe type 0 configuration space. 4292 * 4293 */ 4294 union cvmx_pcieepx_cfg046 { 4295 u32 u32; 4296 struct cvmx_pcieepx_cfg046_s { 4297 u32 msixpoffs : 29; 4298 u32 msixpbir : 3; 4299 } s; 4300 struct cvmx_pcieepx_cfg046_s cn73xx; 4301 struct cvmx_pcieepx_cfg046_s cn78xx; 4302 struct cvmx_pcieepx_cfg046_s cn78xxp1; 4303 struct cvmx_pcieepx_cfg046_s cnf75xx; 4304 }; 4305 4306 typedef union cvmx_pcieepx_cfg046 cvmx_pcieepx_cfg046_t; 4307 4308 /** 4309 * cvmx_pcieep#_cfg064 4310 * 4311 * This register contains the sixty-fifth 32-bits of PCIe type 0 configuration space. 4312 * 4313 */ 4314 union cvmx_pcieepx_cfg064 { 4315 u32 u32; 4316 struct cvmx_pcieepx_cfg064_s { 4317 u32 nco : 12; 4318 u32 cv : 4; 4319 u32 pcieec : 16; 4320 } s; 4321 struct cvmx_pcieepx_cfg064_s cn52xx; 4322 struct cvmx_pcieepx_cfg064_s cn52xxp1; 4323 struct cvmx_pcieepx_cfg064_s cn56xx; 4324 struct cvmx_pcieepx_cfg064_s cn56xxp1; 4325 struct cvmx_pcieepx_cfg064_s cn61xx; 4326 struct cvmx_pcieepx_cfg064_s cn63xx; 4327 struct cvmx_pcieepx_cfg064_s cn63xxp1; 4328 struct cvmx_pcieepx_cfg064_s cn66xx; 4329 struct cvmx_pcieepx_cfg064_s cn68xx; 4330 struct cvmx_pcieepx_cfg064_s cn68xxp1; 4331 struct cvmx_pcieepx_cfg064_s cn70xx; 4332 struct cvmx_pcieepx_cfg064_s cn70xxp1; 4333 struct cvmx_pcieepx_cfg064_s cn73xx; 4334 struct cvmx_pcieepx_cfg064_s cn78xx; 4335 struct cvmx_pcieepx_cfg064_s cn78xxp1; 4336 struct cvmx_pcieepx_cfg064_s cnf71xx; 4337 struct cvmx_pcieepx_cfg064_s cnf75xx; 4338 }; 4339 4340 typedef union cvmx_pcieepx_cfg064 cvmx_pcieepx_cfg064_t; 4341 4342 /** 4343 * cvmx_pcieep#_cfg065 4344 * 4345 * This register contains the sixty-sixth 32-bits of PCIe type 0 configuration space. 4346 * 4347 */ 4348 union cvmx_pcieepx_cfg065 { 4349 u32 u32; 4350 struct cvmx_pcieepx_cfg065_s { 4351 u32 reserved_26_31 : 6; 4352 u32 tpbes : 1; 4353 u32 uatombs : 1; 4354 u32 reserved_23_23 : 1; 4355 u32 ucies : 1; 4356 u32 reserved_21_21 : 1; 4357 u32 ures : 1; 4358 u32 ecrces : 1; 4359 u32 mtlps : 1; 4360 u32 ros : 1; 4361 u32 ucs : 1; 4362 u32 cas : 1; 4363 u32 cts : 1; 4364 u32 fcpes : 1; 4365 u32 ptlps : 1; 4366 u32 reserved_6_11 : 6; 4367 u32 sdes : 1; 4368 u32 dlpes : 1; 4369 u32 reserved_0_3 : 4; 4370 } s; 4371 struct cvmx_pcieepx_cfg065_cn52xx { 4372 u32 reserved_21_31 : 11; 4373 u32 ures : 1; 4374 u32 ecrces : 1; 4375 u32 mtlps : 1; 4376 u32 ros : 1; 4377 u32 ucs : 1; 4378 u32 cas : 1; 4379 u32 cts : 1; 4380 u32 fcpes : 1; 4381 u32 ptlps : 1; 4382 u32 reserved_6_11 : 6; 4383 u32 sdes : 1; 4384 u32 dlpes : 1; 4385 u32 reserved_0_3 : 4; 4386 } cn52xx; 4387 struct cvmx_pcieepx_cfg065_cn52xx cn52xxp1; 4388 struct cvmx_pcieepx_cfg065_cn52xx cn56xx; 4389 struct cvmx_pcieepx_cfg065_cn52xx cn56xxp1; 4390 struct cvmx_pcieepx_cfg065_cn61xx { 4391 u32 reserved_25_31 : 7; 4392 u32 uatombs : 1; 4393 u32 reserved_21_23 : 3; 4394 u32 ures : 1; 4395 u32 ecrces : 1; 4396 u32 mtlps : 1; 4397 u32 ros : 1; 4398 u32 ucs : 1; 4399 u32 cas : 1; 4400 u32 cts : 1; 4401 u32 fcpes : 1; 4402 u32 ptlps : 1; 4403 u32 reserved_6_11 : 6; 4404 u32 sdes : 1; 4405 u32 dlpes : 1; 4406 u32 reserved_0_3 : 4; 4407 } cn61xx; 4408 struct cvmx_pcieepx_cfg065_cn52xx cn63xx; 4409 struct cvmx_pcieepx_cfg065_cn52xx cn63xxp1; 4410 struct cvmx_pcieepx_cfg065_cn61xx cn66xx; 4411 struct cvmx_pcieepx_cfg065_cn61xx cn68xx; 4412 struct cvmx_pcieepx_cfg065_cn52xx cn68xxp1; 4413 struct cvmx_pcieepx_cfg065_cn70xx { 4414 u32 reserved_25_31 : 7; 4415 u32 uatombs : 1; 4416 u32 reserved_23_23 : 1; 4417 u32 ucies : 1; 4418 u32 reserved_21_21 : 1; 4419 u32 ures : 1; 4420 u32 ecrces : 1; 4421 u32 mtlps : 1; 4422 u32 ros : 1; 4423 u32 ucs : 1; 4424 u32 cas : 1; 4425 u32 cts : 1; 4426 u32 fcpes : 1; 4427 u32 ptlps : 1; 4428 u32 reserved_6_11 : 6; 4429 u32 sdes : 1; 4430 u32 dlpes : 1; 4431 u32 reserved_0_3 : 4; 4432 } cn70xx; 4433 struct cvmx_pcieepx_cfg065_cn70xx cn70xxp1; 4434 struct cvmx_pcieepx_cfg065_cn73xx { 4435 u32 reserved_26_31 : 6; 4436 u32 tpbes : 1; 4437 u32 uatombs : 1; 4438 u32 reserved_23_23 : 1; 4439 u32 ucies : 1; 4440 u32 reserved_21_21 : 1; 4441 u32 ures : 1; 4442 u32 ecrces : 1; 4443 u32 mtlps : 1; 4444 u32 ros : 1; 4445 u32 ucs : 1; 4446 u32 cas : 1; 4447 u32 cts : 1; 4448 u32 fcpes : 1; 4449 u32 ptlps : 1; 4450 u32 reserved_5_11 : 7; 4451 u32 dlpes : 1; 4452 u32 reserved_0_3 : 4; 4453 } cn73xx; 4454 struct cvmx_pcieepx_cfg065_cn73xx cn78xx; 4455 struct cvmx_pcieepx_cfg065_cn73xx cn78xxp1; 4456 struct cvmx_pcieepx_cfg065_cnf71xx { 4457 u32 reserved_25_31 : 7; 4458 u32 uatombs : 1; 4459 u32 reserved_23_23 : 1; 4460 u32 ucies : 1; 4461 u32 reserved_21_21 : 1; 4462 u32 ures : 1; 4463 u32 ecrces : 1; 4464 u32 mtlps : 1; 4465 u32 ros : 1; 4466 u32 ucs : 1; 4467 u32 cas : 1; 4468 u32 cts : 1; 4469 u32 fcpes : 1; 4470 u32 ptlps : 1; 4471 u32 reserved_5_11 : 7; 4472 u32 dlpes : 1; 4473 u32 reserved_0_3 : 4; 4474 } cnf71xx; 4475 struct cvmx_pcieepx_cfg065_cn73xx cnf75xx; 4476 }; 4477 4478 typedef union cvmx_pcieepx_cfg065 cvmx_pcieepx_cfg065_t; 4479 4480 /** 4481 * cvmx_pcieep#_cfg066 4482 * 4483 * This register contains the sixty-seventh 32-bits of PCIe type 0 configuration space. 4484 * 4485 */ 4486 union cvmx_pcieepx_cfg066 { 4487 u32 u32; 4488 struct cvmx_pcieepx_cfg066_s { 4489 u32 reserved_26_31 : 6; 4490 u32 tpbem : 1; 4491 u32 uatombm : 1; 4492 u32 reserved_23_23 : 1; 4493 u32 uciem : 1; 4494 u32 reserved_21_21 : 1; 4495 u32 urem : 1; 4496 u32 ecrcem : 1; 4497 u32 mtlpm : 1; 4498 u32 rom : 1; 4499 u32 ucm : 1; 4500 u32 cam : 1; 4501 u32 ctm : 1; 4502 u32 fcpem : 1; 4503 u32 ptlpm : 1; 4504 u32 reserved_6_11 : 6; 4505 u32 sdem : 1; 4506 u32 dlpem : 1; 4507 u32 reserved_0_3 : 4; 4508 } s; 4509 struct cvmx_pcieepx_cfg066_cn52xx { 4510 u32 reserved_21_31 : 11; 4511 u32 urem : 1; 4512 u32 ecrcem : 1; 4513 u32 mtlpm : 1; 4514 u32 rom : 1; 4515 u32 ucm : 1; 4516 u32 cam : 1; 4517 u32 ctm : 1; 4518 u32 fcpem : 1; 4519 u32 ptlpm : 1; 4520 u32 reserved_6_11 : 6; 4521 u32 sdem : 1; 4522 u32 dlpem : 1; 4523 u32 reserved_0_3 : 4; 4524 } cn52xx; 4525 struct cvmx_pcieepx_cfg066_cn52xx cn52xxp1; 4526 struct cvmx_pcieepx_cfg066_cn52xx cn56xx; 4527 struct cvmx_pcieepx_cfg066_cn52xx cn56xxp1; 4528 struct cvmx_pcieepx_cfg066_cn61xx { 4529 u32 reserved_25_31 : 7; 4530 u32 uatombm : 1; 4531 u32 reserved_21_23 : 3; 4532 u32 urem : 1; 4533 u32 ecrcem : 1; 4534 u32 mtlpm : 1; 4535 u32 rom : 1; 4536 u32 ucm : 1; 4537 u32 cam : 1; 4538 u32 ctm : 1; 4539 u32 fcpem : 1; 4540 u32 ptlpm : 1; 4541 u32 reserved_6_11 : 6; 4542 u32 sdem : 1; 4543 u32 dlpem : 1; 4544 u32 reserved_0_3 : 4; 4545 } cn61xx; 4546 struct cvmx_pcieepx_cfg066_cn52xx cn63xx; 4547 struct cvmx_pcieepx_cfg066_cn52xx cn63xxp1; 4548 struct cvmx_pcieepx_cfg066_cn61xx cn66xx; 4549 struct cvmx_pcieepx_cfg066_cn61xx cn68xx; 4550 struct cvmx_pcieepx_cfg066_cn52xx cn68xxp1; 4551 struct cvmx_pcieepx_cfg066_cn70xx { 4552 u32 reserved_25_31 : 7; 4553 u32 uatombm : 1; 4554 u32 reserved_23_23 : 1; 4555 u32 uciem : 1; 4556 u32 reserved_21_21 : 1; 4557 u32 urem : 1; 4558 u32 ecrcem : 1; 4559 u32 mtlpm : 1; 4560 u32 rom : 1; 4561 u32 ucm : 1; 4562 u32 cam : 1; 4563 u32 ctm : 1; 4564 u32 fcpem : 1; 4565 u32 ptlpm : 1; 4566 u32 reserved_6_11 : 6; 4567 u32 sdem : 1; 4568 u32 dlpem : 1; 4569 u32 reserved_0_3 : 4; 4570 } cn70xx; 4571 struct cvmx_pcieepx_cfg066_cn70xx cn70xxp1; 4572 struct cvmx_pcieepx_cfg066_cn73xx { 4573 u32 reserved_26_31 : 6; 4574 u32 tpbem : 1; 4575 u32 uatombm : 1; 4576 u32 reserved_23_23 : 1; 4577 u32 uciem : 1; 4578 u32 reserved_21_21 : 1; 4579 u32 urem : 1; 4580 u32 ecrcem : 1; 4581 u32 mtlpm : 1; 4582 u32 rom : 1; 4583 u32 ucm : 1; 4584 u32 cam : 1; 4585 u32 ctm : 1; 4586 u32 fcpem : 1; 4587 u32 ptlpm : 1; 4588 u32 reserved_5_11 : 7; 4589 u32 dlpem : 1; 4590 u32 reserved_0_3 : 4; 4591 } cn73xx; 4592 struct cvmx_pcieepx_cfg066_cn73xx cn78xx; 4593 struct cvmx_pcieepx_cfg066_cn73xx cn78xxp1; 4594 struct cvmx_pcieepx_cfg066_cnf71xx { 4595 u32 reserved_25_31 : 7; 4596 u32 uatombm : 1; 4597 u32 reserved_23_23 : 1; 4598 u32 uciem : 1; 4599 u32 reserved_21_21 : 1; 4600 u32 urem : 1; 4601 u32 ecrcem : 1; 4602 u32 mtlpm : 1; 4603 u32 rom : 1; 4604 u32 ucm : 1; 4605 u32 cam : 1; 4606 u32 ctm : 1; 4607 u32 fcpem : 1; 4608 u32 ptlpm : 1; 4609 u32 reserved_5_11 : 7; 4610 u32 dlpem : 1; 4611 u32 reserved_0_3 : 4; 4612 } cnf71xx; 4613 struct cvmx_pcieepx_cfg066_cn73xx cnf75xx; 4614 }; 4615 4616 typedef union cvmx_pcieepx_cfg066 cvmx_pcieepx_cfg066_t; 4617 4618 /** 4619 * cvmx_pcieep#_cfg067 4620 * 4621 * This register contains the sixty-eighth 32-bits of PCIe type 0 configuration space. 4622 * 4623 */ 4624 union cvmx_pcieepx_cfg067 { 4625 u32 u32; 4626 struct cvmx_pcieepx_cfg067_s { 4627 u32 reserved_26_31 : 6; 4628 u32 tpbes : 1; 4629 u32 uatombs : 1; 4630 u32 reserved_23_23 : 1; 4631 u32 ucies : 1; 4632 u32 reserved_21_21 : 1; 4633 u32 ures : 1; 4634 u32 ecrces : 1; 4635 u32 mtlps : 1; 4636 u32 ros : 1; 4637 u32 ucs : 1; 4638 u32 cas : 1; 4639 u32 cts : 1; 4640 u32 fcpes : 1; 4641 u32 ptlps : 1; 4642 u32 reserved_6_11 : 6; 4643 u32 sdes : 1; 4644 u32 dlpes : 1; 4645 u32 reserved_0_3 : 4; 4646 } s; 4647 struct cvmx_pcieepx_cfg067_cn52xx { 4648 u32 reserved_21_31 : 11; 4649 u32 ures : 1; 4650 u32 ecrces : 1; 4651 u32 mtlps : 1; 4652 u32 ros : 1; 4653 u32 ucs : 1; 4654 u32 cas : 1; 4655 u32 cts : 1; 4656 u32 fcpes : 1; 4657 u32 ptlps : 1; 4658 u32 reserved_6_11 : 6; 4659 u32 sdes : 1; 4660 u32 dlpes : 1; 4661 u32 reserved_0_3 : 4; 4662 } cn52xx; 4663 struct cvmx_pcieepx_cfg067_cn52xx cn52xxp1; 4664 struct cvmx_pcieepx_cfg067_cn52xx cn56xx; 4665 struct cvmx_pcieepx_cfg067_cn52xx cn56xxp1; 4666 struct cvmx_pcieepx_cfg067_cn61xx { 4667 u32 reserved_25_31 : 7; 4668 u32 uatombs : 1; 4669 u32 reserved_21_23 : 3; 4670 u32 ures : 1; 4671 u32 ecrces : 1; 4672 u32 mtlps : 1; 4673 u32 ros : 1; 4674 u32 ucs : 1; 4675 u32 cas : 1; 4676 u32 cts : 1; 4677 u32 fcpes : 1; 4678 u32 ptlps : 1; 4679 u32 reserved_6_11 : 6; 4680 u32 sdes : 1; 4681 u32 dlpes : 1; 4682 u32 reserved_0_3 : 4; 4683 } cn61xx; 4684 struct cvmx_pcieepx_cfg067_cn52xx cn63xx; 4685 struct cvmx_pcieepx_cfg067_cn52xx cn63xxp1; 4686 struct cvmx_pcieepx_cfg067_cn61xx cn66xx; 4687 struct cvmx_pcieepx_cfg067_cn61xx cn68xx; 4688 struct cvmx_pcieepx_cfg067_cn52xx cn68xxp1; 4689 struct cvmx_pcieepx_cfg067_cn70xx { 4690 u32 reserved_25_31 : 7; 4691 u32 uatombs : 1; 4692 u32 reserved_23_23 : 1; 4693 u32 ucies : 1; 4694 u32 reserved_21_21 : 1; 4695 u32 ures : 1; 4696 u32 ecrces : 1; 4697 u32 mtlps : 1; 4698 u32 ros : 1; 4699 u32 ucs : 1; 4700 u32 cas : 1; 4701 u32 cts : 1; 4702 u32 fcpes : 1; 4703 u32 ptlps : 1; 4704 u32 reserved_6_11 : 6; 4705 u32 sdes : 1; 4706 u32 dlpes : 1; 4707 u32 reserved_0_3 : 4; 4708 } cn70xx; 4709 struct cvmx_pcieepx_cfg067_cn70xx cn70xxp1; 4710 struct cvmx_pcieepx_cfg067_cn73xx { 4711 u32 reserved_26_31 : 6; 4712 u32 tpbes : 1; 4713 u32 uatombs : 1; 4714 u32 reserved_23_23 : 1; 4715 u32 ucies : 1; 4716 u32 reserved_21_21 : 1; 4717 u32 ures : 1; 4718 u32 ecrces : 1; 4719 u32 mtlps : 1; 4720 u32 ros : 1; 4721 u32 ucs : 1; 4722 u32 cas : 1; 4723 u32 cts : 1; 4724 u32 fcpes : 1; 4725 u32 ptlps : 1; 4726 u32 reserved_11_5 : 7; 4727 u32 dlpes : 1; 4728 u32 reserved_0_3 : 4; 4729 } cn73xx; 4730 struct cvmx_pcieepx_cfg067_cn73xx cn78xx; 4731 struct cvmx_pcieepx_cfg067_cn73xx cn78xxp1; 4732 struct cvmx_pcieepx_cfg067_cnf71xx { 4733 u32 reserved_25_31 : 7; 4734 u32 uatombs : 1; 4735 u32 reserved_23_23 : 1; 4736 u32 ucies : 1; 4737 u32 reserved_21_21 : 1; 4738 u32 ures : 1; 4739 u32 ecrces : 1; 4740 u32 mtlps : 1; 4741 u32 ros : 1; 4742 u32 ucs : 1; 4743 u32 cas : 1; 4744 u32 cts : 1; 4745 u32 fcpes : 1; 4746 u32 ptlps : 1; 4747 u32 reserved_5_11 : 7; 4748 u32 dlpes : 1; 4749 u32 reserved_0_3 : 4; 4750 } cnf71xx; 4751 struct cvmx_pcieepx_cfg067_cn73xx cnf75xx; 4752 }; 4753 4754 typedef union cvmx_pcieepx_cfg067 cvmx_pcieepx_cfg067_t; 4755 4756 /** 4757 * cvmx_pcieep#_cfg068 4758 * 4759 * This register contains the sixty-ninth 32-bits of PCIe type 0 configuration space. 4760 * 4761 */ 4762 union cvmx_pcieepx_cfg068 { 4763 u32 u32; 4764 struct cvmx_pcieepx_cfg068_s { 4765 u32 reserved_15_31 : 17; 4766 u32 cies : 1; 4767 u32 anfes : 1; 4768 u32 rtts : 1; 4769 u32 reserved_9_11 : 3; 4770 u32 rnrs : 1; 4771 u32 bdllps : 1; 4772 u32 btlps : 1; 4773 u32 reserved_1_5 : 5; 4774 u32 res : 1; 4775 } s; 4776 struct cvmx_pcieepx_cfg068_cn52xx { 4777 u32 reserved_14_31 : 18; 4778 u32 anfes : 1; 4779 u32 rtts : 1; 4780 u32 reserved_9_11 : 3; 4781 u32 rnrs : 1; 4782 u32 bdllps : 1; 4783 u32 btlps : 1; 4784 u32 reserved_1_5 : 5; 4785 u32 res : 1; 4786 } cn52xx; 4787 struct cvmx_pcieepx_cfg068_cn52xx cn52xxp1; 4788 struct cvmx_pcieepx_cfg068_cn52xx cn56xx; 4789 struct cvmx_pcieepx_cfg068_cn52xx cn56xxp1; 4790 struct cvmx_pcieepx_cfg068_cn52xx cn61xx; 4791 struct cvmx_pcieepx_cfg068_cn52xx cn63xx; 4792 struct cvmx_pcieepx_cfg068_cn52xx cn63xxp1; 4793 struct cvmx_pcieepx_cfg068_cn52xx cn66xx; 4794 struct cvmx_pcieepx_cfg068_cn52xx cn68xx; 4795 struct cvmx_pcieepx_cfg068_cn52xx cn68xxp1; 4796 struct cvmx_pcieepx_cfg068_s cn70xx; 4797 struct cvmx_pcieepx_cfg068_s cn70xxp1; 4798 struct cvmx_pcieepx_cfg068_s cn73xx; 4799 struct cvmx_pcieepx_cfg068_s cn78xx; 4800 struct cvmx_pcieepx_cfg068_s cn78xxp1; 4801 struct cvmx_pcieepx_cfg068_s cnf71xx; 4802 struct cvmx_pcieepx_cfg068_s cnf75xx; 4803 }; 4804 4805 typedef union cvmx_pcieepx_cfg068 cvmx_pcieepx_cfg068_t; 4806 4807 /** 4808 * cvmx_pcieep#_cfg069 4809 * 4810 * This register contains the seventieth 32-bits of PCIe type 0 configuration space. 4811 * 4812 */ 4813 union cvmx_pcieepx_cfg069 { 4814 u32 u32; 4815 struct cvmx_pcieepx_cfg069_s { 4816 u32 reserved_15_31 : 17; 4817 u32 ciem : 1; 4818 u32 anfem : 1; 4819 u32 rttm : 1; 4820 u32 reserved_9_11 : 3; 4821 u32 rnrm : 1; 4822 u32 bdllpm : 1; 4823 u32 btlpm : 1; 4824 u32 reserved_1_5 : 5; 4825 u32 rem : 1; 4826 } s; 4827 struct cvmx_pcieepx_cfg069_cn52xx { 4828 u32 reserved_14_31 : 18; 4829 u32 anfem : 1; 4830 u32 rttm : 1; 4831 u32 reserved_9_11 : 3; 4832 u32 rnrm : 1; 4833 u32 bdllpm : 1; 4834 u32 btlpm : 1; 4835 u32 reserved_1_5 : 5; 4836 u32 rem : 1; 4837 } cn52xx; 4838 struct cvmx_pcieepx_cfg069_cn52xx cn52xxp1; 4839 struct cvmx_pcieepx_cfg069_cn52xx cn56xx; 4840 struct cvmx_pcieepx_cfg069_cn52xx cn56xxp1; 4841 struct cvmx_pcieepx_cfg069_cn52xx cn61xx; 4842 struct cvmx_pcieepx_cfg069_cn52xx cn63xx; 4843 struct cvmx_pcieepx_cfg069_cn52xx cn63xxp1; 4844 struct cvmx_pcieepx_cfg069_cn52xx cn66xx; 4845 struct cvmx_pcieepx_cfg069_cn52xx cn68xx; 4846 struct cvmx_pcieepx_cfg069_cn52xx cn68xxp1; 4847 struct cvmx_pcieepx_cfg069_s cn70xx; 4848 struct cvmx_pcieepx_cfg069_s cn70xxp1; 4849 struct cvmx_pcieepx_cfg069_s cn73xx; 4850 struct cvmx_pcieepx_cfg069_s cn78xx; 4851 struct cvmx_pcieepx_cfg069_s cn78xxp1; 4852 struct cvmx_pcieepx_cfg069_s cnf71xx; 4853 struct cvmx_pcieepx_cfg069_s cnf75xx; 4854 }; 4855 4856 typedef union cvmx_pcieepx_cfg069 cvmx_pcieepx_cfg069_t; 4857 4858 /** 4859 * cvmx_pcieep#_cfg070 4860 * 4861 * This register contains the seventy-first 32-bits of PCIe type 0 configuration space. 4862 * 4863 */ 4864 union cvmx_pcieepx_cfg070 { 4865 u32 u32; 4866 struct cvmx_pcieepx_cfg070_s { 4867 u32 reserved_12_31 : 20; 4868 u32 tlp_plp : 1; 4869 u32 reserved_9_10 : 2; 4870 u32 ce : 1; 4871 u32 cc : 1; 4872 u32 ge : 1; 4873 u32 gc : 1; 4874 u32 fep : 5; 4875 } s; 4876 struct cvmx_pcieepx_cfg070_cn52xx { 4877 u32 reserved_9_31 : 23; 4878 u32 ce : 1; 4879 u32 cc : 1; 4880 u32 ge : 1; 4881 u32 gc : 1; 4882 u32 fep : 5; 4883 } cn52xx; 4884 struct cvmx_pcieepx_cfg070_cn52xx cn52xxp1; 4885 struct cvmx_pcieepx_cfg070_cn52xx cn56xx; 4886 struct cvmx_pcieepx_cfg070_cn52xx cn56xxp1; 4887 struct cvmx_pcieepx_cfg070_cn52xx cn61xx; 4888 struct cvmx_pcieepx_cfg070_cn52xx cn63xx; 4889 struct cvmx_pcieepx_cfg070_cn52xx cn63xxp1; 4890 struct cvmx_pcieepx_cfg070_cn52xx cn66xx; 4891 struct cvmx_pcieepx_cfg070_cn52xx cn68xx; 4892 struct cvmx_pcieepx_cfg070_cn52xx cn68xxp1; 4893 struct cvmx_pcieepx_cfg070_cn52xx cn70xx; 4894 struct cvmx_pcieepx_cfg070_cn52xx cn70xxp1; 4895 struct cvmx_pcieepx_cfg070_s cn73xx; 4896 struct cvmx_pcieepx_cfg070_s cn78xx; 4897 struct cvmx_pcieepx_cfg070_s cn78xxp1; 4898 struct cvmx_pcieepx_cfg070_cn52xx cnf71xx; 4899 struct cvmx_pcieepx_cfg070_s cnf75xx; 4900 }; 4901 4902 typedef union cvmx_pcieepx_cfg070 cvmx_pcieepx_cfg070_t; 4903 4904 /** 4905 * cvmx_pcieep#_cfg071 4906 * 4907 * This register contains the seventy-second 32-bits of PCIe type 0 configuration space. 4908 * 4909 */ 4910 union cvmx_pcieepx_cfg071 { 4911 u32 u32; 4912 struct cvmx_pcieepx_cfg071_s { 4913 u32 dword1 : 32; 4914 } s; 4915 struct cvmx_pcieepx_cfg071_s cn52xx; 4916 struct cvmx_pcieepx_cfg071_s cn52xxp1; 4917 struct cvmx_pcieepx_cfg071_s cn56xx; 4918 struct cvmx_pcieepx_cfg071_s cn56xxp1; 4919 struct cvmx_pcieepx_cfg071_s cn61xx; 4920 struct cvmx_pcieepx_cfg071_s cn63xx; 4921 struct cvmx_pcieepx_cfg071_s cn63xxp1; 4922 struct cvmx_pcieepx_cfg071_s cn66xx; 4923 struct cvmx_pcieepx_cfg071_s cn68xx; 4924 struct cvmx_pcieepx_cfg071_s cn68xxp1; 4925 struct cvmx_pcieepx_cfg071_s cn70xx; 4926 struct cvmx_pcieepx_cfg071_s cn70xxp1; 4927 struct cvmx_pcieepx_cfg071_s cn73xx; 4928 struct cvmx_pcieepx_cfg071_s cn78xx; 4929 struct cvmx_pcieepx_cfg071_s cn78xxp1; 4930 struct cvmx_pcieepx_cfg071_s cnf71xx; 4931 struct cvmx_pcieepx_cfg071_s cnf75xx; 4932 }; 4933 4934 typedef union cvmx_pcieepx_cfg071 cvmx_pcieepx_cfg071_t; 4935 4936 /** 4937 * cvmx_pcieep#_cfg072 4938 * 4939 * This register contains the seventy-third 32-bits of PCIe type 0 configuration space. 4940 * 4941 */ 4942 union cvmx_pcieepx_cfg072 { 4943 u32 u32; 4944 struct cvmx_pcieepx_cfg072_s { 4945 u32 dword2 : 32; 4946 } s; 4947 struct cvmx_pcieepx_cfg072_s cn52xx; 4948 struct cvmx_pcieepx_cfg072_s cn52xxp1; 4949 struct cvmx_pcieepx_cfg072_s cn56xx; 4950 struct cvmx_pcieepx_cfg072_s cn56xxp1; 4951 struct cvmx_pcieepx_cfg072_s cn61xx; 4952 struct cvmx_pcieepx_cfg072_s cn63xx; 4953 struct cvmx_pcieepx_cfg072_s cn63xxp1; 4954 struct cvmx_pcieepx_cfg072_s cn66xx; 4955 struct cvmx_pcieepx_cfg072_s cn68xx; 4956 struct cvmx_pcieepx_cfg072_s cn68xxp1; 4957 struct cvmx_pcieepx_cfg072_s cn70xx; 4958 struct cvmx_pcieepx_cfg072_s cn70xxp1; 4959 struct cvmx_pcieepx_cfg072_s cn73xx; 4960 struct cvmx_pcieepx_cfg072_s cn78xx; 4961 struct cvmx_pcieepx_cfg072_s cn78xxp1; 4962 struct cvmx_pcieepx_cfg072_s cnf71xx; 4963 struct cvmx_pcieepx_cfg072_s cnf75xx; 4964 }; 4965 4966 typedef union cvmx_pcieepx_cfg072 cvmx_pcieepx_cfg072_t; 4967 4968 /** 4969 * cvmx_pcieep#_cfg073 4970 * 4971 * This register contains the seventy-fourth 32-bits of PCIe type 0 configuration space. 4972 * 4973 */ 4974 union cvmx_pcieepx_cfg073 { 4975 u32 u32; 4976 struct cvmx_pcieepx_cfg073_s { 4977 u32 dword3 : 32; 4978 } s; 4979 struct cvmx_pcieepx_cfg073_s cn52xx; 4980 struct cvmx_pcieepx_cfg073_s cn52xxp1; 4981 struct cvmx_pcieepx_cfg073_s cn56xx; 4982 struct cvmx_pcieepx_cfg073_s cn56xxp1; 4983 struct cvmx_pcieepx_cfg073_s cn61xx; 4984 struct cvmx_pcieepx_cfg073_s cn63xx; 4985 struct cvmx_pcieepx_cfg073_s cn63xxp1; 4986 struct cvmx_pcieepx_cfg073_s cn66xx; 4987 struct cvmx_pcieepx_cfg073_s cn68xx; 4988 struct cvmx_pcieepx_cfg073_s cn68xxp1; 4989 struct cvmx_pcieepx_cfg073_s cn70xx; 4990 struct cvmx_pcieepx_cfg073_s cn70xxp1; 4991 struct cvmx_pcieepx_cfg073_s cn73xx; 4992 struct cvmx_pcieepx_cfg073_s cn78xx; 4993 struct cvmx_pcieepx_cfg073_s cn78xxp1; 4994 struct cvmx_pcieepx_cfg073_s cnf71xx; 4995 struct cvmx_pcieepx_cfg073_s cnf75xx; 4996 }; 4997 4998 typedef union cvmx_pcieepx_cfg073 cvmx_pcieepx_cfg073_t; 4999 5000 /** 5001 * cvmx_pcieep#_cfg074 5002 * 5003 * This register contains the seventy-fifth 32-bits of PCIe type 0 configuration space. 5004 * 5005 */ 5006 union cvmx_pcieepx_cfg074 { 5007 u32 u32; 5008 struct cvmx_pcieepx_cfg074_s { 5009 u32 dword4 : 32; 5010 } s; 5011 struct cvmx_pcieepx_cfg074_s cn52xx; 5012 struct cvmx_pcieepx_cfg074_s cn52xxp1; 5013 struct cvmx_pcieepx_cfg074_s cn56xx; 5014 struct cvmx_pcieepx_cfg074_s cn56xxp1; 5015 struct cvmx_pcieepx_cfg074_s cn61xx; 5016 struct cvmx_pcieepx_cfg074_s cn63xx; 5017 struct cvmx_pcieepx_cfg074_s cn63xxp1; 5018 struct cvmx_pcieepx_cfg074_s cn66xx; 5019 struct cvmx_pcieepx_cfg074_s cn68xx; 5020 struct cvmx_pcieepx_cfg074_s cn68xxp1; 5021 struct cvmx_pcieepx_cfg074_s cn70xx; 5022 struct cvmx_pcieepx_cfg074_s cn70xxp1; 5023 struct cvmx_pcieepx_cfg074_s cn73xx; 5024 struct cvmx_pcieepx_cfg074_s cn78xx; 5025 struct cvmx_pcieepx_cfg074_s cn78xxp1; 5026 struct cvmx_pcieepx_cfg074_s cnf71xx; 5027 struct cvmx_pcieepx_cfg074_s cnf75xx; 5028 }; 5029 5030 typedef union cvmx_pcieepx_cfg074 cvmx_pcieepx_cfg074_t; 5031 5032 /** 5033 * cvmx_pcieep#_cfg078 5034 * 5035 * This register contains the seventy-ninth 32-bits of PCIe type 0 configuration space. 5036 * 5037 */ 5038 union cvmx_pcieepx_cfg078 { 5039 u32 u32; 5040 struct cvmx_pcieepx_cfg078_s { 5041 u32 tlp_pfx_log : 32; 5042 } s; 5043 struct cvmx_pcieepx_cfg078_s cn73xx; 5044 struct cvmx_pcieepx_cfg078_s cn78xx; 5045 struct cvmx_pcieepx_cfg078_s cn78xxp1; 5046 struct cvmx_pcieepx_cfg078_s cnf75xx; 5047 }; 5048 5049 typedef union cvmx_pcieepx_cfg078 cvmx_pcieepx_cfg078_t; 5050 5051 /** 5052 * cvmx_pcieep#_cfg082 5053 * 5054 * This register contains the eighty-third 32-bits of PCIe type 0 configuration space. 5055 * 5056 */ 5057 union cvmx_pcieepx_cfg082 { 5058 u32 u32; 5059 struct cvmx_pcieepx_cfg082_s { 5060 u32 nco : 12; 5061 u32 cv : 4; 5062 u32 reserved_0_15 : 16; 5063 } s; 5064 struct cvmx_pcieepx_cfg082_cn70xx { 5065 u32 nco : 12; 5066 u32 cv : 4; 5067 u32 pcieec : 16; 5068 } cn70xx; 5069 struct cvmx_pcieepx_cfg082_cn70xx cn70xxp1; 5070 struct cvmx_pcieepx_cfg082_cn73xx { 5071 u32 nco : 12; 5072 u32 cv : 4; 5073 u32 ariid : 16; 5074 } cn73xx; 5075 struct cvmx_pcieepx_cfg082_cn73xx cn78xx; 5076 struct cvmx_pcieepx_cfg082_cn73xx cn78xxp1; 5077 struct cvmx_pcieepx_cfg082_cn73xx cnf75xx; 5078 }; 5079 5080 typedef union cvmx_pcieepx_cfg082 cvmx_pcieepx_cfg082_t; 5081 5082 /** 5083 * cvmx_pcieep#_cfg083 5084 * 5085 * This register contains the eighty-fourth 32-bits of PCIe type 0 configuration space. 5086 * 5087 */ 5088 union cvmx_pcieepx_cfg083 { 5089 u32 u32; 5090 struct cvmx_pcieepx_cfg083_s { 5091 u32 reserved_2_31 : 30; 5092 u32 acsfgc : 1; 5093 u32 mfvcfgc : 1; 5094 } s; 5095 struct cvmx_pcieepx_cfg083_cn70xx { 5096 u32 reserved_26_31 : 6; 5097 u32 srs : 22; 5098 u32 reserved_0_3 : 4; 5099 } cn70xx; 5100 struct cvmx_pcieepx_cfg083_cn70xx cn70xxp1; 5101 struct cvmx_pcieepx_cfg083_cn73xx { 5102 u32 reserved_23_31 : 9; 5103 u32 fg : 3; 5104 u32 reserved_18_19 : 2; 5105 u32 acsfge : 1; 5106 u32 mfvcfge : 1; 5107 u32 nfn : 8; 5108 u32 reserved_2_7 : 6; 5109 u32 acsfgc : 1; 5110 u32 mfvcfgc : 1; 5111 } cn73xx; 5112 struct cvmx_pcieepx_cfg083_cn73xx cn78xx; 5113 struct cvmx_pcieepx_cfg083_cn73xx cn78xxp1; 5114 struct cvmx_pcieepx_cfg083_cn73xx cnf75xx; 5115 }; 5116 5117 typedef union cvmx_pcieepx_cfg083 cvmx_pcieepx_cfg083_t; 5118 5119 /** 5120 * cvmx_pcieep#_cfg084 5121 * 5122 * PCIE_CFG084 = Eighty-fifth 32-bits of PCIE type 0 config space 5123 * (PCI Express Resizable BAR (RBAR) Control Register) 5124 */ 5125 union cvmx_pcieepx_cfg084 { 5126 u32 u32; 5127 struct cvmx_pcieepx_cfg084_s { 5128 u32 reserved_13_31 : 19; 5129 u32 rbars : 5; 5130 u32 nrbar : 3; 5131 u32 reserved_3_4 : 2; 5132 u32 rbari : 3; 5133 } s; 5134 struct cvmx_pcieepx_cfg084_s cn70xx; 5135 struct cvmx_pcieepx_cfg084_s cn70xxp1; 5136 }; 5137 5138 typedef union cvmx_pcieepx_cfg084 cvmx_pcieepx_cfg084_t; 5139 5140 /** 5141 * cvmx_pcieep#_cfg086 5142 * 5143 * This register contains the eighty-seventh 32-bits of PCIe type 0 configuration space. 5144 * 5145 */ 5146 union cvmx_pcieepx_cfg086 { 5147 u32 u32; 5148 struct cvmx_pcieepx_cfg086_s { 5149 u32 nco : 12; 5150 u32 cv : 4; 5151 u32 pcieec : 16; 5152 } s; 5153 struct cvmx_pcieepx_cfg086_s cn73xx; 5154 struct cvmx_pcieepx_cfg086_s cn78xx; 5155 struct cvmx_pcieepx_cfg086_s cn78xxp1; 5156 struct cvmx_pcieepx_cfg086_s cnf75xx; 5157 }; 5158 5159 typedef union cvmx_pcieepx_cfg086 cvmx_pcieepx_cfg086_t; 5160 5161 /** 5162 * cvmx_pcieep#_cfg087 5163 * 5164 * This register contains the eighty-eighth 32-bits of PCIe type 0 configuration space. 5165 * 5166 */ 5167 union cvmx_pcieepx_cfg087 { 5168 u32 u32; 5169 struct cvmx_pcieepx_cfg087_s { 5170 u32 reserved_0_31 : 32; 5171 } s; 5172 struct cvmx_pcieepx_cfg087_s cn73xx; 5173 struct cvmx_pcieepx_cfg087_s cn78xx; 5174 struct cvmx_pcieepx_cfg087_s cn78xxp1; 5175 struct cvmx_pcieepx_cfg087_s cnf75xx; 5176 }; 5177 5178 typedef union cvmx_pcieepx_cfg087 cvmx_pcieepx_cfg087_t; 5179 5180 /** 5181 * cvmx_pcieep#_cfg088 5182 * 5183 * This register contains the eighty-ninth 32-bits of PCIe type 0 configuration space. 5184 * 5185 */ 5186 union cvmx_pcieepx_cfg088 { 5187 u32 u32; 5188 struct cvmx_pcieepx_cfg088_s { 5189 u32 reserved_8_31 : 24; 5190 u32 les : 8; 5191 } s; 5192 struct cvmx_pcieepx_cfg088_s cn73xx; 5193 struct cvmx_pcieepx_cfg088_s cn78xx; 5194 struct cvmx_pcieepx_cfg088_s cn78xxp1; 5195 struct cvmx_pcieepx_cfg088_s cnf75xx; 5196 }; 5197 5198 typedef union cvmx_pcieepx_cfg088 cvmx_pcieepx_cfg088_t; 5199 5200 /** 5201 * cvmx_pcieep#_cfg089 5202 * 5203 * This register contains the ninetieth 32-bits of PCIe type 0 configuration space. 5204 * 5205 */ 5206 union cvmx_pcieepx_cfg089 { 5207 u32 u32; 5208 struct cvmx_pcieepx_cfg089_s { 5209 u32 reserved_31_31 : 1; 5210 u32 l1dph : 3; 5211 u32 l1dtp : 4; 5212 u32 reserved_15_23 : 9; 5213 u32 l0dph : 3; 5214 u32 l0dtp : 4; 5215 u32 reserved_0_7 : 8; 5216 } s; 5217 struct cvmx_pcieepx_cfg089_s cn73xx; 5218 struct cvmx_pcieepx_cfg089_s cn78xx; 5219 struct cvmx_pcieepx_cfg089_s cn78xxp1; 5220 struct cvmx_pcieepx_cfg089_s cnf75xx; 5221 }; 5222 5223 typedef union cvmx_pcieepx_cfg089 cvmx_pcieepx_cfg089_t; 5224 5225 /** 5226 * cvmx_pcieep#_cfg090 5227 * 5228 * This register contains the ninety-first 32-bits of PCIe type 0 configuration space. 5229 * 5230 */ 5231 union cvmx_pcieepx_cfg090 { 5232 u32 u32; 5233 struct cvmx_pcieepx_cfg090_s { 5234 u32 reserved_31_31 : 1; 5235 u32 l3dph : 3; 5236 u32 l3dtp : 4; 5237 u32 reserved_15_23 : 9; 5238 u32 l2dph : 3; 5239 u32 l2dtp : 4; 5240 u32 reserved_0_7 : 8; 5241 } s; 5242 struct cvmx_pcieepx_cfg090_s cn73xx; 5243 struct cvmx_pcieepx_cfg090_s cn78xx; 5244 struct cvmx_pcieepx_cfg090_s cn78xxp1; 5245 struct cvmx_pcieepx_cfg090_s cnf75xx; 5246 }; 5247 5248 typedef union cvmx_pcieepx_cfg090 cvmx_pcieepx_cfg090_t; 5249 5250 /** 5251 * cvmx_pcieep#_cfg091 5252 * 5253 * This register contains the ninety-second 32-bits of PCIe type 0 configuration space. 5254 * 5255 */ 5256 union cvmx_pcieepx_cfg091 { 5257 u32 u32; 5258 struct cvmx_pcieepx_cfg091_s { 5259 u32 reserved_31_31 : 1; 5260 u32 l5dph : 3; 5261 u32 l5dtp : 4; 5262 u32 reserved_15_23 : 9; 5263 u32 l4dph : 3; 5264 u32 l4dtp : 4; 5265 u32 reserved_0_7 : 8; 5266 } s; 5267 struct cvmx_pcieepx_cfg091_s cn73xx; 5268 struct cvmx_pcieepx_cfg091_s cn78xx; 5269 struct cvmx_pcieepx_cfg091_s cn78xxp1; 5270 struct cvmx_pcieepx_cfg091_s cnf75xx; 5271 }; 5272 5273 typedef union cvmx_pcieepx_cfg091 cvmx_pcieepx_cfg091_t; 5274 5275 /** 5276 * cvmx_pcieep#_cfg092 5277 * 5278 * This register contains the ninety-fourth 32-bits of PCIe type 0 configuration space. 5279 * 5280 */ 5281 union cvmx_pcieepx_cfg092 { 5282 u32 u32; 5283 struct cvmx_pcieepx_cfg092_s { 5284 u32 reserved_31_31 : 1; 5285 u32 l7dph : 3; 5286 u32 l7dtp : 4; 5287 u32 reserved_15_23 : 9; 5288 u32 l6dph : 3; 5289 u32 l6dtp : 4; 5290 u32 reserved_0_7 : 8; 5291 } s; 5292 struct cvmx_pcieepx_cfg092_s cn73xx; 5293 struct cvmx_pcieepx_cfg092_s cn78xx; 5294 struct cvmx_pcieepx_cfg092_s cn78xxp1; 5295 struct cvmx_pcieepx_cfg092_s cnf75xx; 5296 }; 5297 5298 typedef union cvmx_pcieepx_cfg092 cvmx_pcieepx_cfg092_t; 5299 5300 /** 5301 * cvmx_pcieep#_cfg094 5302 * 5303 * This register contains the ninety-fifth 32-bits of PCIe type 0 configuration space. 5304 * 5305 */ 5306 union cvmx_pcieepx_cfg094 { 5307 u32 u32; 5308 struct cvmx_pcieepx_cfg094_s { 5309 u32 nco : 12; 5310 u32 cv : 4; 5311 u32 pcieec : 16; 5312 } s; 5313 struct cvmx_pcieepx_cfg094_s cn73xx; 5314 struct cvmx_pcieepx_cfg094_s cn78xx; 5315 struct cvmx_pcieepx_cfg094_s cn78xxp1; 5316 struct cvmx_pcieepx_cfg094_s cnf75xx; 5317 }; 5318 5319 typedef union cvmx_pcieepx_cfg094 cvmx_pcieepx_cfg094_t; 5320 5321 /** 5322 * cvmx_pcieep#_cfg095 5323 * 5324 * This register contains the ninety-sixth 32-bits of PCIe type 0 configuration space. 5325 * 5326 */ 5327 union cvmx_pcieepx_cfg095 { 5328 u32 u32; 5329 struct cvmx_pcieepx_cfg095_s { 5330 u32 vfmimn : 11; 5331 u32 reserved_2_20 : 19; 5332 u32 arichp : 1; 5333 u32 vfmc : 1; 5334 } s; 5335 struct cvmx_pcieepx_cfg095_s cn73xx; 5336 struct cvmx_pcieepx_cfg095_s cn78xx; 5337 struct cvmx_pcieepx_cfg095_s cn78xxp1; 5338 struct cvmx_pcieepx_cfg095_s cnf75xx; 5339 }; 5340 5341 typedef union cvmx_pcieepx_cfg095 cvmx_pcieepx_cfg095_t; 5342 5343 /** 5344 * cvmx_pcieep#_cfg096 5345 * 5346 * This register contains the ninety-seventh 32-bits of PCIe type 0 configuration space. 5347 * 5348 */ 5349 union cvmx_pcieepx_cfg096 { 5350 u32 u32; 5351 struct cvmx_pcieepx_cfg096_s { 5352 u32 reserved_17_31 : 15; 5353 u32 ms : 1; 5354 u32 reserved_5_15 : 11; 5355 u32 ach : 1; 5356 u32 mse : 1; 5357 u32 mie : 1; 5358 u32 me : 1; 5359 u32 vfe : 1; 5360 } s; 5361 struct cvmx_pcieepx_cfg096_s cn73xx; 5362 struct cvmx_pcieepx_cfg096_s cn78xx; 5363 struct cvmx_pcieepx_cfg096_s cn78xxp1; 5364 struct cvmx_pcieepx_cfg096_s cnf75xx; 5365 }; 5366 5367 typedef union cvmx_pcieepx_cfg096 cvmx_pcieepx_cfg096_t; 5368 5369 /** 5370 * cvmx_pcieep#_cfg097 5371 * 5372 * This register contains the ninety-eighth 32-bits of PCIe type 0 configuration space. 5373 * 5374 */ 5375 union cvmx_pcieepx_cfg097 { 5376 u32 u32; 5377 struct cvmx_pcieepx_cfg097_s { 5378 u32 tvf : 16; 5379 u32 ivf : 16; 5380 } s; 5381 struct cvmx_pcieepx_cfg097_s cn73xx; 5382 struct cvmx_pcieepx_cfg097_s cn78xx; 5383 struct cvmx_pcieepx_cfg097_s cn78xxp1; 5384 struct cvmx_pcieepx_cfg097_s cnf75xx; 5385 }; 5386 5387 typedef union cvmx_pcieepx_cfg097 cvmx_pcieepx_cfg097_t; 5388 5389 /** 5390 * cvmx_pcieep#_cfg098 5391 * 5392 * This register contains the ninety-ninth 32-bits of PCIe type 0 configuration space. 5393 * 5394 */ 5395 union cvmx_pcieepx_cfg098 { 5396 u32 u32; 5397 struct cvmx_pcieepx_cfg098_s { 5398 u32 reserved_24_31 : 8; 5399 u32 fdl : 8; 5400 u32 nvf : 16; 5401 } s; 5402 struct cvmx_pcieepx_cfg098_s cn73xx; 5403 struct cvmx_pcieepx_cfg098_s cn78xx; 5404 struct cvmx_pcieepx_cfg098_s cn78xxp1; 5405 struct cvmx_pcieepx_cfg098_s cnf75xx; 5406 }; 5407 5408 typedef union cvmx_pcieepx_cfg098 cvmx_pcieepx_cfg098_t; 5409 5410 /** 5411 * cvmx_pcieep#_cfg099 5412 * 5413 * This register contains the one hundredth 32-bits of PCIe type 0 configuration space. 5414 * 5415 */ 5416 union cvmx_pcieepx_cfg099 { 5417 u32 u32; 5418 struct cvmx_pcieepx_cfg099_s { 5419 u32 vfs : 16; 5420 u32 fo : 16; 5421 } s; 5422 struct cvmx_pcieepx_cfg099_s cn73xx; 5423 struct cvmx_pcieepx_cfg099_s cn78xx; 5424 struct cvmx_pcieepx_cfg099_s cn78xxp1; 5425 struct cvmx_pcieepx_cfg099_s cnf75xx; 5426 }; 5427 5428 typedef union cvmx_pcieepx_cfg099 cvmx_pcieepx_cfg099_t; 5429 5430 /** 5431 * cvmx_pcieep#_cfg100 5432 * 5433 * This register contains the one hundred first 32-bits of PCIe type 0 configuration space. 5434 * 5435 */ 5436 union cvmx_pcieepx_cfg100 { 5437 u32 u32; 5438 struct cvmx_pcieepx_cfg100_s { 5439 u32 vfdev : 16; 5440 u32 reserved_0_15 : 16; 5441 } s; 5442 struct cvmx_pcieepx_cfg100_s cn73xx; 5443 struct cvmx_pcieepx_cfg100_s cn78xx; 5444 struct cvmx_pcieepx_cfg100_s cn78xxp1; 5445 struct cvmx_pcieepx_cfg100_s cnf75xx; 5446 }; 5447 5448 typedef union cvmx_pcieepx_cfg100 cvmx_pcieepx_cfg100_t; 5449 5450 /** 5451 * cvmx_pcieep#_cfg101 5452 * 5453 * This register contains the one hundred second 32-bits of PCIe type 0 configuration space. 5454 * 5455 */ 5456 union cvmx_pcieepx_cfg101 { 5457 u32 u32; 5458 struct cvmx_pcieepx_cfg101_s { 5459 u32 supps : 32; 5460 } s; 5461 struct cvmx_pcieepx_cfg101_s cn73xx; 5462 struct cvmx_pcieepx_cfg101_s cn78xx; 5463 struct cvmx_pcieepx_cfg101_s cn78xxp1; 5464 struct cvmx_pcieepx_cfg101_s cnf75xx; 5465 }; 5466 5467 typedef union cvmx_pcieepx_cfg101 cvmx_pcieepx_cfg101_t; 5468 5469 /** 5470 * cvmx_pcieep#_cfg102 5471 * 5472 * This register contains the one hundred third 32-bits of PCIe type 0 configuration space. 5473 * 5474 */ 5475 union cvmx_pcieepx_cfg102 { 5476 u32 u32; 5477 struct cvmx_pcieepx_cfg102_s { 5478 u32 ps : 32; 5479 } s; 5480 struct cvmx_pcieepx_cfg102_s cn73xx; 5481 struct cvmx_pcieepx_cfg102_s cn78xx; 5482 struct cvmx_pcieepx_cfg102_s cn78xxp1; 5483 struct cvmx_pcieepx_cfg102_s cnf75xx; 5484 }; 5485 5486 typedef union cvmx_pcieepx_cfg102 cvmx_pcieepx_cfg102_t; 5487 5488 /** 5489 * cvmx_pcieep#_cfg103 5490 * 5491 * This register contains the one hundred fourth 32-bits of PCIe type 0 configuration space. 5492 * 5493 */ 5494 union cvmx_pcieepx_cfg103 { 5495 u32 u32; 5496 struct cvmx_pcieepx_cfg103_s { 5497 u32 reserved_4_31 : 28; 5498 u32 pf : 1; 5499 u32 typ : 2; 5500 u32 mspc : 1; 5501 } s; 5502 struct cvmx_pcieepx_cfg103_cn73xx { 5503 u32 lbab : 12; 5504 u32 reserved_4_19 : 16; 5505 u32 pf : 1; 5506 u32 typ : 2; 5507 u32 mspc : 1; 5508 } cn73xx; 5509 struct cvmx_pcieepx_cfg103_cn73xx cn78xx; 5510 struct cvmx_pcieepx_cfg103_cn78xxp1 { 5511 u32 lbab : 17; 5512 u32 reserved_4_14 : 11; 5513 u32 pf : 1; 5514 u32 typ : 2; 5515 u32 mspc : 1; 5516 } cn78xxp1; 5517 struct cvmx_pcieepx_cfg103_cn73xx cnf75xx; 5518 }; 5519 5520 typedef union cvmx_pcieepx_cfg103 cvmx_pcieepx_cfg103_t; 5521 5522 /** 5523 * cvmx_pcieep#_cfg104 5524 * 5525 * This register contains the one hundred seventh 32-bits of PCIe type 0 configuration space. 5526 * 5527 */ 5528 union cvmx_pcieepx_cfg104 { 5529 u32 u32; 5530 struct cvmx_pcieepx_cfg104_s { 5531 u32 ubab : 32; 5532 } s; 5533 struct cvmx_pcieepx_cfg104_s cn73xx; 5534 struct cvmx_pcieepx_cfg104_s cn78xx; 5535 struct cvmx_pcieepx_cfg104_s cn78xxp1; 5536 struct cvmx_pcieepx_cfg104_s cnf75xx; 5537 }; 5538 5539 typedef union cvmx_pcieepx_cfg104 cvmx_pcieepx_cfg104_t; 5540 5541 /** 5542 * cvmx_pcieep#_cfg105 5543 * 5544 * This register contains the one hundred sixth 32-bits of PCIe type 0 configuration space. 5545 * 5546 */ 5547 union cvmx_pcieepx_cfg105 { 5548 u32 u32; 5549 struct cvmx_pcieepx_cfg105_s { 5550 u32 reserved_0_31 : 32; 5551 } s; 5552 struct cvmx_pcieepx_cfg105_s cn73xx; 5553 struct cvmx_pcieepx_cfg105_s cn78xx; 5554 struct cvmx_pcieepx_cfg105_s cn78xxp1; 5555 struct cvmx_pcieepx_cfg105_s cnf75xx; 5556 }; 5557 5558 typedef union cvmx_pcieepx_cfg105 cvmx_pcieepx_cfg105_t; 5559 5560 /** 5561 * cvmx_pcieep#_cfg106 5562 * 5563 * This register contains the one hundred seventh 32-bits of PCIe type 0 configuration space. 5564 * 5565 */ 5566 union cvmx_pcieepx_cfg106 { 5567 u32 u32; 5568 struct cvmx_pcieepx_cfg106_s { 5569 u32 reserved_0_31 : 32; 5570 } s; 5571 struct cvmx_pcieepx_cfg106_s cn73xx; 5572 struct cvmx_pcieepx_cfg106_s cn78xx; 5573 struct cvmx_pcieepx_cfg106_s cn78xxp1; 5574 struct cvmx_pcieepx_cfg106_s cnf75xx; 5575 }; 5576 5577 typedef union cvmx_pcieepx_cfg106 cvmx_pcieepx_cfg106_t; 5578 5579 /** 5580 * cvmx_pcieep#_cfg107 5581 * 5582 * This register contains the one hundred eighth 32-bits of PCIe type 0 configuration space. 5583 * 5584 */ 5585 union cvmx_pcieepx_cfg107 { 5586 u32 u32; 5587 struct cvmx_pcieepx_cfg107_s { 5588 u32 reserved_0_31 : 32; 5589 } s; 5590 struct cvmx_pcieepx_cfg107_s cn73xx; 5591 struct cvmx_pcieepx_cfg107_s cn78xx; 5592 struct cvmx_pcieepx_cfg107_s cn78xxp1; 5593 struct cvmx_pcieepx_cfg107_s cnf75xx; 5594 }; 5595 5596 typedef union cvmx_pcieepx_cfg107 cvmx_pcieepx_cfg107_t; 5597 5598 /** 5599 * cvmx_pcieep#_cfg108 5600 * 5601 * This register contains the one hundred ninth 32-bits of PCIe type 0 configuration space. 5602 * 5603 */ 5604 union cvmx_pcieepx_cfg108 { 5605 u32 u32; 5606 struct cvmx_pcieepx_cfg108_s { 5607 u32 reserved_0_31 : 32; 5608 } s; 5609 struct cvmx_pcieepx_cfg108_s cn73xx; 5610 struct cvmx_pcieepx_cfg108_s cn78xx; 5611 struct cvmx_pcieepx_cfg108_s cn78xxp1; 5612 struct cvmx_pcieepx_cfg108_s cnf75xx; 5613 }; 5614 5615 typedef union cvmx_pcieepx_cfg108 cvmx_pcieepx_cfg108_t; 5616 5617 /** 5618 * cvmx_pcieep#_cfg109 5619 * 5620 * This register contains the one hundred tenth 32-bits of PCIe type 0 configuration space. 5621 * 5622 */ 5623 union cvmx_pcieepx_cfg109 { 5624 u32 u32; 5625 struct cvmx_pcieepx_cfg109_s { 5626 u32 mso : 29; 5627 u32 msbir : 3; 5628 } s; 5629 struct cvmx_pcieepx_cfg109_s cn73xx; 5630 struct cvmx_pcieepx_cfg109_s cn78xx; 5631 struct cvmx_pcieepx_cfg109_s cn78xxp1; 5632 struct cvmx_pcieepx_cfg109_s cnf75xx; 5633 }; 5634 5635 typedef union cvmx_pcieepx_cfg109 cvmx_pcieepx_cfg109_t; 5636 5637 /** 5638 * cvmx_pcieep#_cfg110 5639 * 5640 * This register contains the one hundred eleventh 32-bits of PCIe type 0 configuration space. 5641 * 5642 */ 5643 union cvmx_pcieepx_cfg110 { 5644 u32 u32; 5645 struct cvmx_pcieepx_cfg110_s { 5646 u32 nco : 12; 5647 u32 cv : 4; 5648 u32 pcieec : 16; 5649 } s; 5650 struct cvmx_pcieepx_cfg110_s cn73xx; 5651 struct cvmx_pcieepx_cfg110_s cn78xx; 5652 struct cvmx_pcieepx_cfg110_s cn78xxp1; 5653 struct cvmx_pcieepx_cfg110_s cnf75xx; 5654 }; 5655 5656 typedef union cvmx_pcieepx_cfg110 cvmx_pcieepx_cfg110_t; 5657 5658 /** 5659 * cvmx_pcieep#_cfg111 5660 * 5661 * This register contains the one hundred twelfth 32-bits of PCIe type 0 configuration space. 5662 * 5663 */ 5664 union cvmx_pcieepx_cfg111 { 5665 u32 u32; 5666 struct cvmx_pcieepx_cfg111_s { 5667 u32 reserved_30_31 : 2; 5668 u32 srs : 26; 5669 u32 reserved_0_3 : 4; 5670 } s; 5671 struct cvmx_pcieepx_cfg111_s cn73xx; 5672 struct cvmx_pcieepx_cfg111_s cn78xx; 5673 struct cvmx_pcieepx_cfg111_s cn78xxp1; 5674 struct cvmx_pcieepx_cfg111_s cnf75xx; 5675 }; 5676 5677 typedef union cvmx_pcieepx_cfg111 cvmx_pcieepx_cfg111_t; 5678 5679 /** 5680 * cvmx_pcieep#_cfg112 5681 * 5682 * This register contains the one hundred thirteenth 32-bits of PCIe type 0 configuration space. 5683 * 5684 */ 5685 union cvmx_pcieepx_cfg112 { 5686 u32 u32; 5687 struct cvmx_pcieepx_cfg112_s { 5688 u32 reserved_13_31 : 19; 5689 u32 rbars : 5; 5690 u32 nrbar : 3; 5691 u32 reserved_3_4 : 2; 5692 u32 rbari : 3; 5693 } s; 5694 struct cvmx_pcieepx_cfg112_s cn73xx; 5695 struct cvmx_pcieepx_cfg112_s cn78xx; 5696 struct cvmx_pcieepx_cfg112_s cn78xxp1; 5697 struct cvmx_pcieepx_cfg112_s cnf75xx; 5698 }; 5699 5700 typedef union cvmx_pcieepx_cfg112 cvmx_pcieepx_cfg112_t; 5701 5702 /** 5703 * cvmx_pcieep#_cfg448 5704 * 5705 * This register contains the four hundred forty-ninth 32-bits of PCIe type 0 configuration space. 5706 * 5707 */ 5708 union cvmx_pcieepx_cfg448 { 5709 u32 u32; 5710 struct cvmx_pcieepx_cfg448_s { 5711 u32 rtl : 16; 5712 u32 rtltl : 16; 5713 } s; 5714 struct cvmx_pcieepx_cfg448_s cn52xx; 5715 struct cvmx_pcieepx_cfg448_s cn52xxp1; 5716 struct cvmx_pcieepx_cfg448_s cn56xx; 5717 struct cvmx_pcieepx_cfg448_s cn56xxp1; 5718 struct cvmx_pcieepx_cfg448_s cn61xx; 5719 struct cvmx_pcieepx_cfg448_s cn63xx; 5720 struct cvmx_pcieepx_cfg448_s cn63xxp1; 5721 struct cvmx_pcieepx_cfg448_s cn66xx; 5722 struct cvmx_pcieepx_cfg448_s cn68xx; 5723 struct cvmx_pcieepx_cfg448_s cn68xxp1; 5724 struct cvmx_pcieepx_cfg448_s cn70xx; 5725 struct cvmx_pcieepx_cfg448_s cn70xxp1; 5726 struct cvmx_pcieepx_cfg448_s cn73xx; 5727 struct cvmx_pcieepx_cfg448_s cn78xx; 5728 struct cvmx_pcieepx_cfg448_s cn78xxp1; 5729 struct cvmx_pcieepx_cfg448_s cnf71xx; 5730 struct cvmx_pcieepx_cfg448_s cnf75xx; 5731 }; 5732 5733 typedef union cvmx_pcieepx_cfg448 cvmx_pcieepx_cfg448_t; 5734 5735 /** 5736 * cvmx_pcieep#_cfg449 5737 * 5738 * This register contains the four hundred fiftieth 32-bits of PCIe type 0 configuration space. 5739 * 5740 */ 5741 union cvmx_pcieepx_cfg449 { 5742 u32 u32; 5743 struct cvmx_pcieepx_cfg449_s { 5744 u32 omr : 32; 5745 } s; 5746 struct cvmx_pcieepx_cfg449_s cn52xx; 5747 struct cvmx_pcieepx_cfg449_s cn52xxp1; 5748 struct cvmx_pcieepx_cfg449_s cn56xx; 5749 struct cvmx_pcieepx_cfg449_s cn56xxp1; 5750 struct cvmx_pcieepx_cfg449_s cn61xx; 5751 struct cvmx_pcieepx_cfg449_s cn63xx; 5752 struct cvmx_pcieepx_cfg449_s cn63xxp1; 5753 struct cvmx_pcieepx_cfg449_s cn66xx; 5754 struct cvmx_pcieepx_cfg449_s cn68xx; 5755 struct cvmx_pcieepx_cfg449_s cn68xxp1; 5756 struct cvmx_pcieepx_cfg449_s cn70xx; 5757 struct cvmx_pcieepx_cfg449_s cn70xxp1; 5758 struct cvmx_pcieepx_cfg449_s cn73xx; 5759 struct cvmx_pcieepx_cfg449_s cn78xx; 5760 struct cvmx_pcieepx_cfg449_s cn78xxp1; 5761 struct cvmx_pcieepx_cfg449_s cnf71xx; 5762 struct cvmx_pcieepx_cfg449_s cnf75xx; 5763 }; 5764 5765 typedef union cvmx_pcieepx_cfg449 cvmx_pcieepx_cfg449_t; 5766 5767 /** 5768 * cvmx_pcieep#_cfg450 5769 * 5770 * This register contains the four hundred fifty-first 32-bits of PCIe type 0 configuration space. 5771 * 5772 */ 5773 union cvmx_pcieepx_cfg450 { 5774 u32 u32; 5775 struct cvmx_pcieepx_cfg450_s { 5776 u32 lpec : 8; 5777 u32 reserved_22_23 : 2; 5778 u32 link_state : 6; 5779 u32 force_link : 1; 5780 u32 reserved_8_14 : 7; 5781 u32 link_num : 8; 5782 } s; 5783 struct cvmx_pcieepx_cfg450_s cn52xx; 5784 struct cvmx_pcieepx_cfg450_s cn52xxp1; 5785 struct cvmx_pcieepx_cfg450_s cn56xx; 5786 struct cvmx_pcieepx_cfg450_s cn56xxp1; 5787 struct cvmx_pcieepx_cfg450_s cn61xx; 5788 struct cvmx_pcieepx_cfg450_s cn63xx; 5789 struct cvmx_pcieepx_cfg450_s cn63xxp1; 5790 struct cvmx_pcieepx_cfg450_s cn66xx; 5791 struct cvmx_pcieepx_cfg450_s cn68xx; 5792 struct cvmx_pcieepx_cfg450_s cn68xxp1; 5793 struct cvmx_pcieepx_cfg450_cn70xx { 5794 u32 lpec : 8; 5795 u32 reserved_22_23 : 2; 5796 u32 link_state : 6; 5797 u32 force_link : 1; 5798 u32 reserved_12_14 : 3; 5799 u32 link_cmd : 4; 5800 u32 link_num : 8; 5801 } cn70xx; 5802 struct cvmx_pcieepx_cfg450_cn70xx cn70xxp1; 5803 struct cvmx_pcieepx_cfg450_cn73xx { 5804 u32 lpec : 8; 5805 u32 reserved_22_23 : 2; 5806 u32 link_state : 6; 5807 u32 force_link : 1; 5808 u32 reserved_12_14 : 3; 5809 u32 forced_ltssm : 4; 5810 u32 link_num : 8; 5811 } cn73xx; 5812 struct cvmx_pcieepx_cfg450_cn73xx cn78xx; 5813 struct cvmx_pcieepx_cfg450_cn73xx cn78xxp1; 5814 struct cvmx_pcieepx_cfg450_s cnf71xx; 5815 struct cvmx_pcieepx_cfg450_cn73xx cnf75xx; 5816 }; 5817 5818 typedef union cvmx_pcieepx_cfg450 cvmx_pcieepx_cfg450_t; 5819 5820 /** 5821 * cvmx_pcieep#_cfg451 5822 * 5823 * This register contains the four hundred fifty-second 32-bits of PCIe type 0 configuration space. 5824 * 5825 */ 5826 union cvmx_pcieepx_cfg451 { 5827 u32 u32; 5828 struct cvmx_pcieepx_cfg451_s { 5829 u32 reserved_31_31 : 1; 5830 u32 easpml1 : 1; 5831 u32 l1el : 3; 5832 u32 l0el : 3; 5833 u32 n_fts_cc : 8; 5834 u32 n_fts : 8; 5835 u32 ack_freq : 8; 5836 } s; 5837 struct cvmx_pcieepx_cfg451_cn52xx { 5838 u32 reserved_30_31 : 2; 5839 u32 l1el : 3; 5840 u32 l0el : 3; 5841 u32 n_fts_cc : 8; 5842 u32 n_fts : 8; 5843 u32 ack_freq : 8; 5844 } cn52xx; 5845 struct cvmx_pcieepx_cfg451_cn52xx cn52xxp1; 5846 struct cvmx_pcieepx_cfg451_cn52xx cn56xx; 5847 struct cvmx_pcieepx_cfg451_cn52xx cn56xxp1; 5848 struct cvmx_pcieepx_cfg451_s cn61xx; 5849 struct cvmx_pcieepx_cfg451_cn52xx cn63xx; 5850 struct cvmx_pcieepx_cfg451_cn52xx cn63xxp1; 5851 struct cvmx_pcieepx_cfg451_s cn66xx; 5852 struct cvmx_pcieepx_cfg451_s cn68xx; 5853 struct cvmx_pcieepx_cfg451_s cn68xxp1; 5854 struct cvmx_pcieepx_cfg451_s cn70xx; 5855 struct cvmx_pcieepx_cfg451_s cn70xxp1; 5856 struct cvmx_pcieepx_cfg451_s cn73xx; 5857 struct cvmx_pcieepx_cfg451_s cn78xx; 5858 struct cvmx_pcieepx_cfg451_s cn78xxp1; 5859 struct cvmx_pcieepx_cfg451_s cnf71xx; 5860 struct cvmx_pcieepx_cfg451_s cnf75xx; 5861 }; 5862 5863 typedef union cvmx_pcieepx_cfg451 cvmx_pcieepx_cfg451_t; 5864 5865 /** 5866 * cvmx_pcieep#_cfg452 5867 * 5868 * This register contains the four hundred fifty-third 32-bits of PCIe type 0 configuration space. 5869 * 5870 */ 5871 union cvmx_pcieepx_cfg452 { 5872 u32 u32; 5873 struct cvmx_pcieepx_cfg452_s { 5874 u32 reserved_26_31 : 6; 5875 u32 eccrc : 1; 5876 u32 reserved_22_24 : 3; 5877 u32 lme : 6; 5878 u32 reserved_12_15 : 4; 5879 u32 link_rate : 4; 5880 u32 flm : 1; 5881 u32 reserved_6_6 : 1; 5882 u32 dllle : 1; 5883 u32 reserved_4_4 : 1; 5884 u32 ra : 1; 5885 u32 le : 1; 5886 u32 sd : 1; 5887 u32 omr : 1; 5888 } s; 5889 struct cvmx_pcieepx_cfg452_cn52xx { 5890 u32 reserved_26_31 : 6; 5891 u32 eccrc : 1; 5892 u32 reserved_22_24 : 3; 5893 u32 lme : 6; 5894 u32 reserved_8_15 : 8; 5895 u32 flm : 1; 5896 u32 reserved_6_6 : 1; 5897 u32 dllle : 1; 5898 u32 reserved_4_4 : 1; 5899 u32 ra : 1; 5900 u32 le : 1; 5901 u32 sd : 1; 5902 u32 omr : 1; 5903 } cn52xx; 5904 struct cvmx_pcieepx_cfg452_cn52xx cn52xxp1; 5905 struct cvmx_pcieepx_cfg452_cn52xx cn56xx; 5906 struct cvmx_pcieepx_cfg452_cn52xx cn56xxp1; 5907 struct cvmx_pcieepx_cfg452_cn61xx { 5908 u32 reserved_22_31 : 10; 5909 u32 lme : 6; 5910 u32 reserved_8_15 : 8; 5911 u32 flm : 1; 5912 u32 reserved_6_6 : 1; 5913 u32 dllle : 1; 5914 u32 reserved_4_4 : 1; 5915 u32 ra : 1; 5916 u32 le : 1; 5917 u32 sd : 1; 5918 u32 omr : 1; 5919 } cn61xx; 5920 struct cvmx_pcieepx_cfg452_cn52xx cn63xx; 5921 struct cvmx_pcieepx_cfg452_cn52xx cn63xxp1; 5922 struct cvmx_pcieepx_cfg452_cn61xx cn66xx; 5923 struct cvmx_pcieepx_cfg452_cn61xx cn68xx; 5924 struct cvmx_pcieepx_cfg452_cn61xx cn68xxp1; 5925 struct cvmx_pcieepx_cfg452_cn70xx { 5926 u32 reserved_22_31 : 10; 5927 u32 lme : 6; 5928 u32 reserved_12_15 : 4; 5929 u32 link_rate : 4; 5930 u32 flm : 1; 5931 u32 reserved_6_6 : 1; 5932 u32 dllle : 1; 5933 u32 reserved_4_4 : 1; 5934 u32 ra : 1; 5935 u32 le : 1; 5936 u32 sd : 1; 5937 u32 omr : 1; 5938 } cn70xx; 5939 struct cvmx_pcieepx_cfg452_cn70xx cn70xxp1; 5940 struct cvmx_pcieepx_cfg452_cn70xx cn73xx; 5941 struct cvmx_pcieepx_cfg452_cn70xx cn78xx; 5942 struct cvmx_pcieepx_cfg452_cn70xx cn78xxp1; 5943 struct cvmx_pcieepx_cfg452_cn61xx cnf71xx; 5944 struct cvmx_pcieepx_cfg452_cn70xx cnf75xx; 5945 }; 5946 5947 typedef union cvmx_pcieepx_cfg452 cvmx_pcieepx_cfg452_t; 5948 5949 /** 5950 * cvmx_pcieep#_cfg453 5951 * 5952 * This register contains the four hundred fifty-fourth 32-bits of PCIe type 0 configuration space. 5953 * 5954 */ 5955 union cvmx_pcieepx_cfg453 { 5956 u32 u32; 5957 struct cvmx_pcieepx_cfg453_s { 5958 u32 dlld : 1; 5959 u32 reserved_26_30 : 5; 5960 u32 ack_nak : 1; 5961 u32 fcd : 1; 5962 u32 ilst : 24; 5963 } s; 5964 struct cvmx_pcieepx_cfg453_s cn52xx; 5965 struct cvmx_pcieepx_cfg453_s cn52xxp1; 5966 struct cvmx_pcieepx_cfg453_s cn56xx; 5967 struct cvmx_pcieepx_cfg453_s cn56xxp1; 5968 struct cvmx_pcieepx_cfg453_s cn61xx; 5969 struct cvmx_pcieepx_cfg453_s cn63xx; 5970 struct cvmx_pcieepx_cfg453_s cn63xxp1; 5971 struct cvmx_pcieepx_cfg453_s cn66xx; 5972 struct cvmx_pcieepx_cfg453_s cn68xx; 5973 struct cvmx_pcieepx_cfg453_s cn68xxp1; 5974 struct cvmx_pcieepx_cfg453_s cn70xx; 5975 struct cvmx_pcieepx_cfg453_s cn70xxp1; 5976 struct cvmx_pcieepx_cfg453_s cn73xx; 5977 struct cvmx_pcieepx_cfg453_s cn78xx; 5978 struct cvmx_pcieepx_cfg453_s cn78xxp1; 5979 struct cvmx_pcieepx_cfg453_s cnf71xx; 5980 struct cvmx_pcieepx_cfg453_s cnf75xx; 5981 }; 5982 5983 typedef union cvmx_pcieepx_cfg453 cvmx_pcieepx_cfg453_t; 5984 5985 /** 5986 * cvmx_pcieep#_cfg454 5987 * 5988 * This register contains the four hundred fifty-fifth 32-bits of PCIe type 0 configuration space. 5989 * 5990 */ 5991 union cvmx_pcieepx_cfg454 { 5992 u32 u32; 5993 struct cvmx_pcieepx_cfg454_s { 5994 u32 cx_nfunc : 3; 5995 u32 tmfcwt : 5; 5996 u32 tmanlt : 5; 5997 u32 tmrt : 5; 5998 u32 reserved_11_13 : 3; 5999 u32 nskps : 3; 6000 u32 reserved_0_7 : 8; 6001 } s; 6002 struct cvmx_pcieepx_cfg454_cn52xx { 6003 u32 reserved_29_31 : 3; 6004 u32 tmfcwt : 5; 6005 u32 tmanlt : 5; 6006 u32 tmrt : 5; 6007 u32 reserved_11_13 : 3; 6008 u32 nskps : 3; 6009 u32 reserved_4_7 : 4; 6010 u32 ntss : 4; 6011 } cn52xx; 6012 struct cvmx_pcieepx_cfg454_cn52xx cn52xxp1; 6013 struct cvmx_pcieepx_cfg454_cn52xx cn56xx; 6014 struct cvmx_pcieepx_cfg454_cn52xx cn56xxp1; 6015 struct cvmx_pcieepx_cfg454_cn61xx { 6016 u32 cx_nfunc : 3; 6017 u32 tmfcwt : 5; 6018 u32 tmanlt : 5; 6019 u32 tmrt : 5; 6020 u32 reserved_8_13 : 6; 6021 u32 mfuncn : 8; 6022 } cn61xx; 6023 struct cvmx_pcieepx_cfg454_cn52xx cn63xx; 6024 struct cvmx_pcieepx_cfg454_cn52xx cn63xxp1; 6025 struct cvmx_pcieepx_cfg454_cn61xx cn66xx; 6026 struct cvmx_pcieepx_cfg454_cn61xx cn68xx; 6027 struct cvmx_pcieepx_cfg454_cn52xx cn68xxp1; 6028 struct cvmx_pcieepx_cfg454_cn70xx { 6029 u32 reserved_24_31 : 8; 6030 u32 tmanlt : 5; 6031 u32 tmrt : 5; 6032 u32 reserved_8_13 : 6; 6033 u32 mfuncn : 8; 6034 } cn70xx; 6035 struct cvmx_pcieepx_cfg454_cn70xx cn70xxp1; 6036 struct cvmx_pcieepx_cfg454_cn73xx { 6037 u32 reserved_29_31 : 3; 6038 u32 tmfcwt : 5; 6039 u32 tmanlt : 5; 6040 u32 tmrt : 5; 6041 u32 reserved_8_13 : 6; 6042 u32 mfuncn : 8; 6043 } cn73xx; 6044 struct cvmx_pcieepx_cfg454_cn73xx cn78xx; 6045 struct cvmx_pcieepx_cfg454_cn73xx cn78xxp1; 6046 struct cvmx_pcieepx_cfg454_cn61xx cnf71xx; 6047 struct cvmx_pcieepx_cfg454_cn73xx cnf75xx; 6048 }; 6049 6050 typedef union cvmx_pcieepx_cfg454 cvmx_pcieepx_cfg454_t; 6051 6052 /** 6053 * cvmx_pcieep#_cfg455 6054 * 6055 * This register contains the four hundred fifty-sixth 32-bits of PCIe type 0 configuration space. 6056 * 6057 */ 6058 union cvmx_pcieepx_cfg455 { 6059 u32 u32; 6060 struct cvmx_pcieepx_cfg455_s { 6061 u32 m_cfg0_filt : 1; 6062 u32 m_io_filt : 1; 6063 u32 msg_ctrl : 1; 6064 u32 m_cpl_ecrc_filt : 1; 6065 u32 m_ecrc_filt : 1; 6066 u32 m_cpl_len_err : 1; 6067 u32 m_cpl_attr_err : 1; 6068 u32 m_cpl_tc_err : 1; 6069 u32 m_cpl_fun_err : 1; 6070 u32 m_cpl_rid_err : 1; 6071 u32 m_cpl_tag_err : 1; 6072 u32 m_lk_filt : 1; 6073 u32 m_cfg1_filt : 1; 6074 u32 m_bar_match : 1; 6075 u32 m_pois_filt : 1; 6076 u32 m_fun : 1; 6077 u32 dfcwt : 1; 6078 u32 reserved_11_14 : 4; 6079 u32 skpiv : 11; 6080 } s; 6081 struct cvmx_pcieepx_cfg455_s cn52xx; 6082 struct cvmx_pcieepx_cfg455_s cn52xxp1; 6083 struct cvmx_pcieepx_cfg455_s cn56xx; 6084 struct cvmx_pcieepx_cfg455_s cn56xxp1; 6085 struct cvmx_pcieepx_cfg455_s cn61xx; 6086 struct cvmx_pcieepx_cfg455_s cn63xx; 6087 struct cvmx_pcieepx_cfg455_s cn63xxp1; 6088 struct cvmx_pcieepx_cfg455_s cn66xx; 6089 struct cvmx_pcieepx_cfg455_s cn68xx; 6090 struct cvmx_pcieepx_cfg455_s cn68xxp1; 6091 struct cvmx_pcieepx_cfg455_s cn70xx; 6092 struct cvmx_pcieepx_cfg455_s cn70xxp1; 6093 struct cvmx_pcieepx_cfg455_s cn73xx; 6094 struct cvmx_pcieepx_cfg455_s cn78xx; 6095 struct cvmx_pcieepx_cfg455_s cn78xxp1; 6096 struct cvmx_pcieepx_cfg455_s cnf71xx; 6097 struct cvmx_pcieepx_cfg455_s cnf75xx; 6098 }; 6099 6100 typedef union cvmx_pcieepx_cfg455 cvmx_pcieepx_cfg455_t; 6101 6102 /** 6103 * cvmx_pcieep#_cfg456 6104 * 6105 * This register contains the four hundred fifty-seventh 32-bits of PCIe type 0 configuration space. 6106 * 6107 */ 6108 union cvmx_pcieepx_cfg456 { 6109 u32 u32; 6110 struct cvmx_pcieepx_cfg456_s { 6111 u32 reserved_4_31 : 28; 6112 u32 m_handle_flush : 1; 6113 u32 m_dabort_4ucpl : 1; 6114 u32 m_vend1_drp : 1; 6115 u32 m_vend0_drp : 1; 6116 } s; 6117 struct cvmx_pcieepx_cfg456_cn52xx { 6118 u32 reserved_2_31 : 30; 6119 u32 m_vend1_drp : 1; 6120 u32 m_vend0_drp : 1; 6121 } cn52xx; 6122 struct cvmx_pcieepx_cfg456_cn52xx cn52xxp1; 6123 struct cvmx_pcieepx_cfg456_cn52xx cn56xx; 6124 struct cvmx_pcieepx_cfg456_cn52xx cn56xxp1; 6125 struct cvmx_pcieepx_cfg456_s cn61xx; 6126 struct cvmx_pcieepx_cfg456_cn52xx cn63xx; 6127 struct cvmx_pcieepx_cfg456_cn52xx cn63xxp1; 6128 struct cvmx_pcieepx_cfg456_s cn66xx; 6129 struct cvmx_pcieepx_cfg456_s cn68xx; 6130 struct cvmx_pcieepx_cfg456_cn52xx cn68xxp1; 6131 struct cvmx_pcieepx_cfg456_s cn70xx; 6132 struct cvmx_pcieepx_cfg456_s cn70xxp1; 6133 struct cvmx_pcieepx_cfg456_s cn73xx; 6134 struct cvmx_pcieepx_cfg456_s cn78xx; 6135 struct cvmx_pcieepx_cfg456_s cn78xxp1; 6136 struct cvmx_pcieepx_cfg456_s cnf71xx; 6137 struct cvmx_pcieepx_cfg456_s cnf75xx; 6138 }; 6139 6140 typedef union cvmx_pcieepx_cfg456 cvmx_pcieepx_cfg456_t; 6141 6142 /** 6143 * cvmx_pcieep#_cfg458 6144 * 6145 * This register contains the four hundred fifty-ninth 32-bits of PCIe type 0 configuration space. 6146 * 6147 */ 6148 union cvmx_pcieepx_cfg458 { 6149 u32 u32; 6150 struct cvmx_pcieepx_cfg458_s { 6151 u32 dbg_info_l32 : 32; 6152 } s; 6153 struct cvmx_pcieepx_cfg458_s cn52xx; 6154 struct cvmx_pcieepx_cfg458_s cn52xxp1; 6155 struct cvmx_pcieepx_cfg458_s cn56xx; 6156 struct cvmx_pcieepx_cfg458_s cn56xxp1; 6157 struct cvmx_pcieepx_cfg458_s cn61xx; 6158 struct cvmx_pcieepx_cfg458_s cn63xx; 6159 struct cvmx_pcieepx_cfg458_s cn63xxp1; 6160 struct cvmx_pcieepx_cfg458_s cn66xx; 6161 struct cvmx_pcieepx_cfg458_s cn68xx; 6162 struct cvmx_pcieepx_cfg458_s cn68xxp1; 6163 struct cvmx_pcieepx_cfg458_s cn70xx; 6164 struct cvmx_pcieepx_cfg458_s cn70xxp1; 6165 struct cvmx_pcieepx_cfg458_s cn73xx; 6166 struct cvmx_pcieepx_cfg458_s cn78xx; 6167 struct cvmx_pcieepx_cfg458_s cn78xxp1; 6168 struct cvmx_pcieepx_cfg458_s cnf71xx; 6169 struct cvmx_pcieepx_cfg458_s cnf75xx; 6170 }; 6171 6172 typedef union cvmx_pcieepx_cfg458 cvmx_pcieepx_cfg458_t; 6173 6174 /** 6175 * cvmx_pcieep#_cfg459 6176 * 6177 * This register contains the four hundred sixtieth 32-bits of PCIe type 0 configuration space. 6178 * 6179 */ 6180 union cvmx_pcieepx_cfg459 { 6181 u32 u32; 6182 struct cvmx_pcieepx_cfg459_s { 6183 u32 dbg_info_u32 : 32; 6184 } s; 6185 struct cvmx_pcieepx_cfg459_s cn52xx; 6186 struct cvmx_pcieepx_cfg459_s cn52xxp1; 6187 struct cvmx_pcieepx_cfg459_s cn56xx; 6188 struct cvmx_pcieepx_cfg459_s cn56xxp1; 6189 struct cvmx_pcieepx_cfg459_s cn61xx; 6190 struct cvmx_pcieepx_cfg459_s cn63xx; 6191 struct cvmx_pcieepx_cfg459_s cn63xxp1; 6192 struct cvmx_pcieepx_cfg459_s cn66xx; 6193 struct cvmx_pcieepx_cfg459_s cn68xx; 6194 struct cvmx_pcieepx_cfg459_s cn68xxp1; 6195 struct cvmx_pcieepx_cfg459_s cn70xx; 6196 struct cvmx_pcieepx_cfg459_s cn70xxp1; 6197 struct cvmx_pcieepx_cfg459_s cn73xx; 6198 struct cvmx_pcieepx_cfg459_s cn78xx; 6199 struct cvmx_pcieepx_cfg459_s cn78xxp1; 6200 struct cvmx_pcieepx_cfg459_s cnf71xx; 6201 struct cvmx_pcieepx_cfg459_s cnf75xx; 6202 }; 6203 6204 typedef union cvmx_pcieepx_cfg459 cvmx_pcieepx_cfg459_t; 6205 6206 /** 6207 * cvmx_pcieep#_cfg460 6208 * 6209 * This register contains the four hundred sixty-first 32-bits of PCIe type 0 configuration space. 6210 * 6211 */ 6212 union cvmx_pcieepx_cfg460 { 6213 u32 u32; 6214 struct cvmx_pcieepx_cfg460_s { 6215 u32 reserved_20_31 : 12; 6216 u32 tphfcc : 8; 6217 u32 tpdfcc : 12; 6218 } s; 6219 struct cvmx_pcieepx_cfg460_s cn52xx; 6220 struct cvmx_pcieepx_cfg460_s cn52xxp1; 6221 struct cvmx_pcieepx_cfg460_s cn56xx; 6222 struct cvmx_pcieepx_cfg460_s cn56xxp1; 6223 struct cvmx_pcieepx_cfg460_s cn61xx; 6224 struct cvmx_pcieepx_cfg460_s cn63xx; 6225 struct cvmx_pcieepx_cfg460_s cn63xxp1; 6226 struct cvmx_pcieepx_cfg460_s cn66xx; 6227 struct cvmx_pcieepx_cfg460_s cn68xx; 6228 struct cvmx_pcieepx_cfg460_s cn68xxp1; 6229 struct cvmx_pcieepx_cfg460_s cn70xx; 6230 struct cvmx_pcieepx_cfg460_s cn70xxp1; 6231 struct cvmx_pcieepx_cfg460_s cn73xx; 6232 struct cvmx_pcieepx_cfg460_s cn78xx; 6233 struct cvmx_pcieepx_cfg460_s cn78xxp1; 6234 struct cvmx_pcieepx_cfg460_s cnf71xx; 6235 struct cvmx_pcieepx_cfg460_s cnf75xx; 6236 }; 6237 6238 typedef union cvmx_pcieepx_cfg460 cvmx_pcieepx_cfg460_t; 6239 6240 /** 6241 * cvmx_pcieep#_cfg461 6242 * 6243 * This register contains the four hundred sixty-second 32-bits of PCIe type 0 configuration space. 6244 * 6245 */ 6246 union cvmx_pcieepx_cfg461 { 6247 u32 u32; 6248 struct cvmx_pcieepx_cfg461_s { 6249 u32 reserved_20_31 : 12; 6250 u32 tchfcc : 8; 6251 u32 tcdfcc : 12; 6252 } s; 6253 struct cvmx_pcieepx_cfg461_s cn52xx; 6254 struct cvmx_pcieepx_cfg461_s cn52xxp1; 6255 struct cvmx_pcieepx_cfg461_s cn56xx; 6256 struct cvmx_pcieepx_cfg461_s cn56xxp1; 6257 struct cvmx_pcieepx_cfg461_s cn61xx; 6258 struct cvmx_pcieepx_cfg461_s cn63xx; 6259 struct cvmx_pcieepx_cfg461_s cn63xxp1; 6260 struct cvmx_pcieepx_cfg461_s cn66xx; 6261 struct cvmx_pcieepx_cfg461_s cn68xx; 6262 struct cvmx_pcieepx_cfg461_s cn68xxp1; 6263 struct cvmx_pcieepx_cfg461_s cn70xx; 6264 struct cvmx_pcieepx_cfg461_s cn70xxp1; 6265 struct cvmx_pcieepx_cfg461_s cn73xx; 6266 struct cvmx_pcieepx_cfg461_s cn78xx; 6267 struct cvmx_pcieepx_cfg461_s cn78xxp1; 6268 struct cvmx_pcieepx_cfg461_s cnf71xx; 6269 struct cvmx_pcieepx_cfg461_s cnf75xx; 6270 }; 6271 6272 typedef union cvmx_pcieepx_cfg461 cvmx_pcieepx_cfg461_t; 6273 6274 /** 6275 * cvmx_pcieep#_cfg462 6276 * 6277 * This register contains the four hundred sixty-third 32-bits of PCIe type 0 configuration space. 6278 * 6279 */ 6280 union cvmx_pcieepx_cfg462 { 6281 u32 u32; 6282 struct cvmx_pcieepx_cfg462_s { 6283 u32 reserved_20_31 : 12; 6284 u32 tchfcc : 8; 6285 u32 tcdfcc : 12; 6286 } s; 6287 struct cvmx_pcieepx_cfg462_s cn52xx; 6288 struct cvmx_pcieepx_cfg462_s cn52xxp1; 6289 struct cvmx_pcieepx_cfg462_s cn56xx; 6290 struct cvmx_pcieepx_cfg462_s cn56xxp1; 6291 struct cvmx_pcieepx_cfg462_s cn61xx; 6292 struct cvmx_pcieepx_cfg462_s cn63xx; 6293 struct cvmx_pcieepx_cfg462_s cn63xxp1; 6294 struct cvmx_pcieepx_cfg462_s cn66xx; 6295 struct cvmx_pcieepx_cfg462_s cn68xx; 6296 struct cvmx_pcieepx_cfg462_s cn68xxp1; 6297 struct cvmx_pcieepx_cfg462_s cn70xx; 6298 struct cvmx_pcieepx_cfg462_s cn70xxp1; 6299 struct cvmx_pcieepx_cfg462_s cn73xx; 6300 struct cvmx_pcieepx_cfg462_s cn78xx; 6301 struct cvmx_pcieepx_cfg462_s cn78xxp1; 6302 struct cvmx_pcieepx_cfg462_s cnf71xx; 6303 struct cvmx_pcieepx_cfg462_s cnf75xx; 6304 }; 6305 6306 typedef union cvmx_pcieepx_cfg462 cvmx_pcieepx_cfg462_t; 6307 6308 /** 6309 * cvmx_pcieep#_cfg463 6310 * 6311 * This register contains the four hundred sixty-fourth 32-bits of PCIe type 0 configuration space. 6312 * 6313 */ 6314 union cvmx_pcieepx_cfg463 { 6315 u32 u32; 6316 struct cvmx_pcieepx_cfg463_s { 6317 u32 fcltoe : 1; 6318 u32 reserved_29_30 : 2; 6319 u32 fcltov : 13; 6320 u32 reserved_3_15 : 13; 6321 u32 rqne : 1; 6322 u32 trbne : 1; 6323 u32 rtlpfccnr : 1; 6324 } s; 6325 struct cvmx_pcieepx_cfg463_cn52xx { 6326 u32 reserved_3_31 : 29; 6327 u32 rqne : 1; 6328 u32 trbne : 1; 6329 u32 rtlpfccnr : 1; 6330 } cn52xx; 6331 struct cvmx_pcieepx_cfg463_cn52xx cn52xxp1; 6332 struct cvmx_pcieepx_cfg463_cn52xx cn56xx; 6333 struct cvmx_pcieepx_cfg463_cn52xx cn56xxp1; 6334 struct cvmx_pcieepx_cfg463_cn52xx cn61xx; 6335 struct cvmx_pcieepx_cfg463_cn52xx cn63xx; 6336 struct cvmx_pcieepx_cfg463_cn52xx cn63xxp1; 6337 struct cvmx_pcieepx_cfg463_cn52xx cn66xx; 6338 struct cvmx_pcieepx_cfg463_cn52xx cn68xx; 6339 struct cvmx_pcieepx_cfg463_cn52xx cn68xxp1; 6340 struct cvmx_pcieepx_cfg463_cn52xx cn70xx; 6341 struct cvmx_pcieepx_cfg463_cn52xx cn70xxp1; 6342 struct cvmx_pcieepx_cfg463_s cn73xx; 6343 struct cvmx_pcieepx_cfg463_s cn78xx; 6344 struct cvmx_pcieepx_cfg463_s cn78xxp1; 6345 struct cvmx_pcieepx_cfg463_cn52xx cnf71xx; 6346 struct cvmx_pcieepx_cfg463_s cnf75xx; 6347 }; 6348 6349 typedef union cvmx_pcieepx_cfg463 cvmx_pcieepx_cfg463_t; 6350 6351 /** 6352 * cvmx_pcieep#_cfg464 6353 * 6354 * This register contains the four hundred sixty-fifth 32-bits of PCIe type 0 configuration space. 6355 * 6356 */ 6357 union cvmx_pcieepx_cfg464 { 6358 u32 u32; 6359 struct cvmx_pcieepx_cfg464_s { 6360 u32 wrr_vc3 : 8; 6361 u32 wrr_vc2 : 8; 6362 u32 wrr_vc1 : 8; 6363 u32 wrr_vc0 : 8; 6364 } s; 6365 struct cvmx_pcieepx_cfg464_s cn52xx; 6366 struct cvmx_pcieepx_cfg464_s cn52xxp1; 6367 struct cvmx_pcieepx_cfg464_s cn56xx; 6368 struct cvmx_pcieepx_cfg464_s cn56xxp1; 6369 struct cvmx_pcieepx_cfg464_s cn61xx; 6370 struct cvmx_pcieepx_cfg464_s cn63xx; 6371 struct cvmx_pcieepx_cfg464_s cn63xxp1; 6372 struct cvmx_pcieepx_cfg464_s cn66xx; 6373 struct cvmx_pcieepx_cfg464_s cn68xx; 6374 struct cvmx_pcieepx_cfg464_s cn68xxp1; 6375 struct cvmx_pcieepx_cfg464_s cn70xx; 6376 struct cvmx_pcieepx_cfg464_s cn70xxp1; 6377 struct cvmx_pcieepx_cfg464_s cn73xx; 6378 struct cvmx_pcieepx_cfg464_s cn78xx; 6379 struct cvmx_pcieepx_cfg464_s cn78xxp1; 6380 struct cvmx_pcieepx_cfg464_s cnf71xx; 6381 struct cvmx_pcieepx_cfg464_s cnf75xx; 6382 }; 6383 6384 typedef union cvmx_pcieepx_cfg464 cvmx_pcieepx_cfg464_t; 6385 6386 /** 6387 * cvmx_pcieep#_cfg465 6388 * 6389 * This register contains the four hundred sixty-sixth 32-bits of PCIe type 0 configuration space. 6390 * 6391 */ 6392 union cvmx_pcieepx_cfg465 { 6393 u32 u32; 6394 struct cvmx_pcieepx_cfg465_s { 6395 u32 wrr_vc7 : 8; 6396 u32 wrr_vc6 : 8; 6397 u32 wrr_vc5 : 8; 6398 u32 wrr_vc4 : 8; 6399 } s; 6400 struct cvmx_pcieepx_cfg465_s cn52xx; 6401 struct cvmx_pcieepx_cfg465_s cn52xxp1; 6402 struct cvmx_pcieepx_cfg465_s cn56xx; 6403 struct cvmx_pcieepx_cfg465_s cn56xxp1; 6404 struct cvmx_pcieepx_cfg465_s cn61xx; 6405 struct cvmx_pcieepx_cfg465_s cn63xx; 6406 struct cvmx_pcieepx_cfg465_s cn63xxp1; 6407 struct cvmx_pcieepx_cfg465_s cn66xx; 6408 struct cvmx_pcieepx_cfg465_s cn68xx; 6409 struct cvmx_pcieepx_cfg465_s cn68xxp1; 6410 struct cvmx_pcieepx_cfg465_s cn70xx; 6411 struct cvmx_pcieepx_cfg465_s cn70xxp1; 6412 struct cvmx_pcieepx_cfg465_s cn73xx; 6413 struct cvmx_pcieepx_cfg465_s cn78xx; 6414 struct cvmx_pcieepx_cfg465_s cn78xxp1; 6415 struct cvmx_pcieepx_cfg465_s cnf71xx; 6416 struct cvmx_pcieepx_cfg465_s cnf75xx; 6417 }; 6418 6419 typedef union cvmx_pcieepx_cfg465 cvmx_pcieepx_cfg465_t; 6420 6421 /** 6422 * cvmx_pcieep#_cfg466 6423 * 6424 * This register contains the four hundred sixty-seventh 32-bits of PCIe type 0 configuration space. 6425 * 6426 */ 6427 union cvmx_pcieepx_cfg466 { 6428 u32 u32; 6429 struct cvmx_pcieepx_cfg466_s { 6430 u32 rx_queue_order : 1; 6431 u32 type_ordering : 1; 6432 u32 reserved_24_29 : 6; 6433 u32 queue_mode : 3; 6434 u32 reserved_20_20 : 1; 6435 u32 header_credits : 8; 6436 u32 data_credits : 12; 6437 } s; 6438 struct cvmx_pcieepx_cfg466_s cn52xx; 6439 struct cvmx_pcieepx_cfg466_s cn52xxp1; 6440 struct cvmx_pcieepx_cfg466_s cn56xx; 6441 struct cvmx_pcieepx_cfg466_s cn56xxp1; 6442 struct cvmx_pcieepx_cfg466_s cn61xx; 6443 struct cvmx_pcieepx_cfg466_s cn63xx; 6444 struct cvmx_pcieepx_cfg466_s cn63xxp1; 6445 struct cvmx_pcieepx_cfg466_s cn66xx; 6446 struct cvmx_pcieepx_cfg466_s cn68xx; 6447 struct cvmx_pcieepx_cfg466_s cn68xxp1; 6448 struct cvmx_pcieepx_cfg466_s cn70xx; 6449 struct cvmx_pcieepx_cfg466_s cn70xxp1; 6450 struct cvmx_pcieepx_cfg466_s cn73xx; 6451 struct cvmx_pcieepx_cfg466_s cn78xx; 6452 struct cvmx_pcieepx_cfg466_s cn78xxp1; 6453 struct cvmx_pcieepx_cfg466_s cnf71xx; 6454 struct cvmx_pcieepx_cfg466_s cnf75xx; 6455 }; 6456 6457 typedef union cvmx_pcieepx_cfg466 cvmx_pcieepx_cfg466_t; 6458 6459 /** 6460 * cvmx_pcieep#_cfg467 6461 * 6462 * This register contains the four hundred sixty-eighth 32-bits of PCIe type 0 configuration space. 6463 * 6464 */ 6465 union cvmx_pcieepx_cfg467 { 6466 u32 u32; 6467 struct cvmx_pcieepx_cfg467_s { 6468 u32 reserved_24_31 : 8; 6469 u32 queue_mode : 3; 6470 u32 reserved_20_20 : 1; 6471 u32 header_credits : 8; 6472 u32 data_credits : 12; 6473 } s; 6474 struct cvmx_pcieepx_cfg467_s cn52xx; 6475 struct cvmx_pcieepx_cfg467_s cn52xxp1; 6476 struct cvmx_pcieepx_cfg467_s cn56xx; 6477 struct cvmx_pcieepx_cfg467_s cn56xxp1; 6478 struct cvmx_pcieepx_cfg467_s cn61xx; 6479 struct cvmx_pcieepx_cfg467_s cn63xx; 6480 struct cvmx_pcieepx_cfg467_s cn63xxp1; 6481 struct cvmx_pcieepx_cfg467_s cn66xx; 6482 struct cvmx_pcieepx_cfg467_s cn68xx; 6483 struct cvmx_pcieepx_cfg467_s cn68xxp1; 6484 struct cvmx_pcieepx_cfg467_s cn70xx; 6485 struct cvmx_pcieepx_cfg467_s cn70xxp1; 6486 struct cvmx_pcieepx_cfg467_s cn73xx; 6487 struct cvmx_pcieepx_cfg467_s cn78xx; 6488 struct cvmx_pcieepx_cfg467_s cn78xxp1; 6489 struct cvmx_pcieepx_cfg467_s cnf71xx; 6490 struct cvmx_pcieepx_cfg467_s cnf75xx; 6491 }; 6492 6493 typedef union cvmx_pcieepx_cfg467 cvmx_pcieepx_cfg467_t; 6494 6495 /** 6496 * cvmx_pcieep#_cfg468 6497 * 6498 * This register contains the four hundred sixty-ninth 32-bits of PCIe type 0 configuration space. 6499 * 6500 */ 6501 union cvmx_pcieepx_cfg468 { 6502 u32 u32; 6503 struct cvmx_pcieepx_cfg468_s { 6504 u32 reserved_24_31 : 8; 6505 u32 queue_mode : 3; 6506 u32 reserved_20_20 : 1; 6507 u32 header_credits : 8; 6508 u32 data_credits : 12; 6509 } s; 6510 struct cvmx_pcieepx_cfg468_s cn52xx; 6511 struct cvmx_pcieepx_cfg468_s cn52xxp1; 6512 struct cvmx_pcieepx_cfg468_s cn56xx; 6513 struct cvmx_pcieepx_cfg468_s cn56xxp1; 6514 struct cvmx_pcieepx_cfg468_s cn61xx; 6515 struct cvmx_pcieepx_cfg468_s cn63xx; 6516 struct cvmx_pcieepx_cfg468_s cn63xxp1; 6517 struct cvmx_pcieepx_cfg468_s cn66xx; 6518 struct cvmx_pcieepx_cfg468_s cn68xx; 6519 struct cvmx_pcieepx_cfg468_s cn68xxp1; 6520 struct cvmx_pcieepx_cfg468_s cn70xx; 6521 struct cvmx_pcieepx_cfg468_s cn70xxp1; 6522 struct cvmx_pcieepx_cfg468_s cn73xx; 6523 struct cvmx_pcieepx_cfg468_s cn78xx; 6524 struct cvmx_pcieepx_cfg468_s cn78xxp1; 6525 struct cvmx_pcieepx_cfg468_s cnf71xx; 6526 struct cvmx_pcieepx_cfg468_s cnf75xx; 6527 }; 6528 6529 typedef union cvmx_pcieepx_cfg468 cvmx_pcieepx_cfg468_t; 6530 6531 /** 6532 * cvmx_pcieep#_cfg490 6533 * 6534 * PCIE_CFG490 = Four hundred ninety-first 32-bits of PCIE type 0 config space 6535 * (VC0 Posted Buffer Depth) 6536 */ 6537 union cvmx_pcieepx_cfg490 { 6538 u32 u32; 6539 struct cvmx_pcieepx_cfg490_s { 6540 u32 reserved_26_31 : 6; 6541 u32 header_depth : 10; 6542 u32 reserved_14_15 : 2; 6543 u32 data_depth : 14; 6544 } s; 6545 struct cvmx_pcieepx_cfg490_s cn52xx; 6546 struct cvmx_pcieepx_cfg490_s cn52xxp1; 6547 struct cvmx_pcieepx_cfg490_s cn56xx; 6548 struct cvmx_pcieepx_cfg490_s cn56xxp1; 6549 struct cvmx_pcieepx_cfg490_s cn61xx; 6550 struct cvmx_pcieepx_cfg490_s cn63xx; 6551 struct cvmx_pcieepx_cfg490_s cn63xxp1; 6552 struct cvmx_pcieepx_cfg490_s cn66xx; 6553 struct cvmx_pcieepx_cfg490_s cn68xx; 6554 struct cvmx_pcieepx_cfg490_s cn68xxp1; 6555 struct cvmx_pcieepx_cfg490_s cn70xx; 6556 struct cvmx_pcieepx_cfg490_s cn70xxp1; 6557 struct cvmx_pcieepx_cfg490_s cnf71xx; 6558 }; 6559 6560 typedef union cvmx_pcieepx_cfg490 cvmx_pcieepx_cfg490_t; 6561 6562 /** 6563 * cvmx_pcieep#_cfg491 6564 * 6565 * PCIE_CFG491 = Four hundred ninety-second 32-bits of PCIE type 0 config space 6566 * (VC0 Non-Posted Buffer Depth) 6567 */ 6568 union cvmx_pcieepx_cfg491 { 6569 u32 u32; 6570 struct cvmx_pcieepx_cfg491_s { 6571 u32 reserved_26_31 : 6; 6572 u32 header_depth : 10; 6573 u32 reserved_14_15 : 2; 6574 u32 data_depth : 14; 6575 } s; 6576 struct cvmx_pcieepx_cfg491_s cn52xx; 6577 struct cvmx_pcieepx_cfg491_s cn52xxp1; 6578 struct cvmx_pcieepx_cfg491_s cn56xx; 6579 struct cvmx_pcieepx_cfg491_s cn56xxp1; 6580 struct cvmx_pcieepx_cfg491_s cn61xx; 6581 struct cvmx_pcieepx_cfg491_s cn63xx; 6582 struct cvmx_pcieepx_cfg491_s cn63xxp1; 6583 struct cvmx_pcieepx_cfg491_s cn66xx; 6584 struct cvmx_pcieepx_cfg491_s cn68xx; 6585 struct cvmx_pcieepx_cfg491_s cn68xxp1; 6586 struct cvmx_pcieepx_cfg491_s cn70xx; 6587 struct cvmx_pcieepx_cfg491_s cn70xxp1; 6588 struct cvmx_pcieepx_cfg491_s cnf71xx; 6589 }; 6590 6591 typedef union cvmx_pcieepx_cfg491 cvmx_pcieepx_cfg491_t; 6592 6593 /** 6594 * cvmx_pcieep#_cfg492 6595 * 6596 * PCIE_CFG492 = Four hundred ninety-third 32-bits of PCIE type 0 config space 6597 * (VC0 Completion Buffer Depth) 6598 */ 6599 union cvmx_pcieepx_cfg492 { 6600 u32 u32; 6601 struct cvmx_pcieepx_cfg492_s { 6602 u32 reserved_26_31 : 6; 6603 u32 header_depth : 10; 6604 u32 reserved_14_15 : 2; 6605 u32 data_depth : 14; 6606 } s; 6607 struct cvmx_pcieepx_cfg492_s cn52xx; 6608 struct cvmx_pcieepx_cfg492_s cn52xxp1; 6609 struct cvmx_pcieepx_cfg492_s cn56xx; 6610 struct cvmx_pcieepx_cfg492_s cn56xxp1; 6611 struct cvmx_pcieepx_cfg492_s cn61xx; 6612 struct cvmx_pcieepx_cfg492_s cn63xx; 6613 struct cvmx_pcieepx_cfg492_s cn63xxp1; 6614 struct cvmx_pcieepx_cfg492_s cn66xx; 6615 struct cvmx_pcieepx_cfg492_s cn68xx; 6616 struct cvmx_pcieepx_cfg492_s cn68xxp1; 6617 struct cvmx_pcieepx_cfg492_s cn70xx; 6618 struct cvmx_pcieepx_cfg492_s cn70xxp1; 6619 struct cvmx_pcieepx_cfg492_s cnf71xx; 6620 }; 6621 6622 typedef union cvmx_pcieepx_cfg492 cvmx_pcieepx_cfg492_t; 6623 6624 /** 6625 * cvmx_pcieep#_cfg515 6626 * 6627 * This register contains the five hundred sixteenth 32-bits of PCIe type 0 configuration space. 6628 * 6629 */ 6630 union cvmx_pcieepx_cfg515 { 6631 u32 u32; 6632 struct cvmx_pcieepx_cfg515_s { 6633 u32 reserved_21_31 : 11; 6634 u32 s_d_e : 1; 6635 u32 ctcrb : 1; 6636 u32 cpyts : 1; 6637 u32 dsc : 1; 6638 u32 reserved_8_16 : 9; 6639 u32 n_fts : 8; 6640 } s; 6641 struct cvmx_pcieepx_cfg515_cn61xx { 6642 u32 reserved_21_31 : 11; 6643 u32 s_d_e : 1; 6644 u32 ctcrb : 1; 6645 u32 cpyts : 1; 6646 u32 dsc : 1; 6647 u32 le : 9; 6648 u32 n_fts : 8; 6649 } cn61xx; 6650 struct cvmx_pcieepx_cfg515_cn61xx cn63xx; 6651 struct cvmx_pcieepx_cfg515_cn61xx cn63xxp1; 6652 struct cvmx_pcieepx_cfg515_cn61xx cn66xx; 6653 struct cvmx_pcieepx_cfg515_cn61xx cn68xx; 6654 struct cvmx_pcieepx_cfg515_cn61xx cn68xxp1; 6655 struct cvmx_pcieepx_cfg515_cn61xx cn70xx; 6656 struct cvmx_pcieepx_cfg515_cn61xx cn70xxp1; 6657 struct cvmx_pcieepx_cfg515_cn61xx cn73xx; 6658 struct cvmx_pcieepx_cfg515_cn78xx { 6659 u32 reserved_21_31 : 11; 6660 u32 s_d_e : 1; 6661 u32 ctcrb : 1; 6662 u32 cpyts : 1; 6663 u32 dsc : 1; 6664 u32 alaneflip : 1; 6665 u32 pdetlane : 3; 6666 u32 nlanes : 5; 6667 u32 n_fts : 8; 6668 } cn78xx; 6669 struct cvmx_pcieepx_cfg515_cn61xx cn78xxp1; 6670 struct cvmx_pcieepx_cfg515_cn61xx cnf71xx; 6671 struct cvmx_pcieepx_cfg515_cn78xx cnf75xx; 6672 }; 6673 6674 typedef union cvmx_pcieepx_cfg515 cvmx_pcieepx_cfg515_t; 6675 6676 /** 6677 * cvmx_pcieep#_cfg516 6678 * 6679 * This register contains the five hundred seventeenth 32-bits of PCIe type 0 configuration space. 6680 * 6681 */ 6682 union cvmx_pcieepx_cfg516 { 6683 u32 u32; 6684 struct cvmx_pcieepx_cfg516_s { 6685 u32 phy_stat : 32; 6686 } s; 6687 struct cvmx_pcieepx_cfg516_s cn52xx; 6688 struct cvmx_pcieepx_cfg516_s cn52xxp1; 6689 struct cvmx_pcieepx_cfg516_s cn56xx; 6690 struct cvmx_pcieepx_cfg516_s cn56xxp1; 6691 struct cvmx_pcieepx_cfg516_s cn61xx; 6692 struct cvmx_pcieepx_cfg516_s cn63xx; 6693 struct cvmx_pcieepx_cfg516_s cn63xxp1; 6694 struct cvmx_pcieepx_cfg516_s cn66xx; 6695 struct cvmx_pcieepx_cfg516_s cn68xx; 6696 struct cvmx_pcieepx_cfg516_s cn68xxp1; 6697 struct cvmx_pcieepx_cfg516_s cn70xx; 6698 struct cvmx_pcieepx_cfg516_s cn70xxp1; 6699 struct cvmx_pcieepx_cfg516_s cn73xx; 6700 struct cvmx_pcieepx_cfg516_s cn78xx; 6701 struct cvmx_pcieepx_cfg516_s cn78xxp1; 6702 struct cvmx_pcieepx_cfg516_s cnf71xx; 6703 struct cvmx_pcieepx_cfg516_s cnf75xx; 6704 }; 6705 6706 typedef union cvmx_pcieepx_cfg516 cvmx_pcieepx_cfg516_t; 6707 6708 /** 6709 * cvmx_pcieep#_cfg517 6710 * 6711 * This register contains the five hundred eighteenth 32-bits of PCIe type 0 configuration space. 6712 * 6713 */ 6714 union cvmx_pcieepx_cfg517 { 6715 u32 u32; 6716 struct cvmx_pcieepx_cfg517_s { 6717 u32 phy_ctrl : 32; 6718 } s; 6719 struct cvmx_pcieepx_cfg517_s cn52xx; 6720 struct cvmx_pcieepx_cfg517_s cn52xxp1; 6721 struct cvmx_pcieepx_cfg517_s cn56xx; 6722 struct cvmx_pcieepx_cfg517_s cn56xxp1; 6723 struct cvmx_pcieepx_cfg517_s cn61xx; 6724 struct cvmx_pcieepx_cfg517_s cn63xx; 6725 struct cvmx_pcieepx_cfg517_s cn63xxp1; 6726 struct cvmx_pcieepx_cfg517_s cn66xx; 6727 struct cvmx_pcieepx_cfg517_s cn68xx; 6728 struct cvmx_pcieepx_cfg517_s cn68xxp1; 6729 struct cvmx_pcieepx_cfg517_s cn70xx; 6730 struct cvmx_pcieepx_cfg517_s cn70xxp1; 6731 struct cvmx_pcieepx_cfg517_s cn73xx; 6732 struct cvmx_pcieepx_cfg517_s cn78xx; 6733 struct cvmx_pcieepx_cfg517_s cn78xxp1; 6734 struct cvmx_pcieepx_cfg517_s cnf71xx; 6735 struct cvmx_pcieepx_cfg517_s cnf75xx; 6736 }; 6737 6738 typedef union cvmx_pcieepx_cfg517 cvmx_pcieepx_cfg517_t; 6739 6740 /** 6741 * cvmx_pcieep#_cfg548 6742 * 6743 * This register contains the five hundred forty-ninth 32-bits of PCIe type 0 configuration space. 6744 * 6745 */ 6746 union cvmx_pcieepx_cfg548 { 6747 u32 u32; 6748 struct cvmx_pcieepx_cfg548_s { 6749 u32 reserved_26_31 : 6; 6750 u32 rss : 2; 6751 u32 eiedd : 1; 6752 u32 reserved_19_22 : 4; 6753 u32 dcbd : 1; 6754 u32 dtdd : 1; 6755 u32 ed : 1; 6756 u32 reserved_13_15 : 3; 6757 u32 rxeq_ph01_en : 1; 6758 u32 erd : 1; 6759 u32 ecrd : 1; 6760 u32 ep2p3d : 1; 6761 u32 dsg3 : 1; 6762 u32 reserved_1_7 : 7; 6763 u32 grizdnc : 1; 6764 } s; 6765 struct cvmx_pcieepx_cfg548_s cn73xx; 6766 struct cvmx_pcieepx_cfg548_s cn78xx; 6767 struct cvmx_pcieepx_cfg548_s cn78xxp1; 6768 struct cvmx_pcieepx_cfg548_s cnf75xx; 6769 }; 6770 6771 typedef union cvmx_pcieepx_cfg548 cvmx_pcieepx_cfg548_t; 6772 6773 /** 6774 * cvmx_pcieep#_cfg554 6775 * 6776 * This register contains the five hundred fifty-fifth 32-bits of PCIe type 0 configuration space. 6777 * 6778 */ 6779 union cvmx_pcieepx_cfg554 { 6780 u32 u32; 6781 struct cvmx_pcieepx_cfg554_s { 6782 u32 reserved_27_31 : 5; 6783 u32 scefpm : 1; 6784 u32 reserved_25_25 : 1; 6785 u32 iif : 1; 6786 u32 prv : 16; 6787 u32 reserved_6_7 : 2; 6788 u32 p23td : 1; 6789 u32 bt : 1; 6790 u32 fm : 4; 6791 } s; 6792 struct cvmx_pcieepx_cfg554_cn73xx { 6793 u32 reserved_25_31 : 7; 6794 u32 iif : 1; 6795 u32 prv : 16; 6796 u32 reserved_6_7 : 2; 6797 u32 p23td : 1; 6798 u32 bt : 1; 6799 u32 fm : 4; 6800 } cn73xx; 6801 struct cvmx_pcieepx_cfg554_s cn78xx; 6802 struct cvmx_pcieepx_cfg554_s cn78xxp1; 6803 struct cvmx_pcieepx_cfg554_s cnf75xx; 6804 }; 6805 6806 typedef union cvmx_pcieepx_cfg554 cvmx_pcieepx_cfg554_t; 6807 6808 /** 6809 * cvmx_pcieep#_cfg558 6810 * 6811 * This register contains the five hundred fifty-ninth 32-bits of PCIe type 0 configuration space. 6812 * 6813 */ 6814 union cvmx_pcieepx_cfg558 { 6815 u32 u32; 6816 struct cvmx_pcieepx_cfg558_s { 6817 u32 ple : 1; 6818 u32 rxstatus : 31; 6819 } s; 6820 struct cvmx_pcieepx_cfg558_s cn73xx; 6821 struct cvmx_pcieepx_cfg558_s cn78xx; 6822 struct cvmx_pcieepx_cfg558_s cn78xxp1; 6823 struct cvmx_pcieepx_cfg558_s cnf75xx; 6824 }; 6825 6826 typedef union cvmx_pcieepx_cfg558 cvmx_pcieepx_cfg558_t; 6827 6828 /** 6829 * cvmx_pcieep#_cfg559 6830 * 6831 * This register contains the five hundred sixtieth 32-bits of PCIe type 0 configuration space. 6832 * 6833 */ 6834 union cvmx_pcieepx_cfg559 { 6835 u32 u32; 6836 struct cvmx_pcieepx_cfg559_s { 6837 u32 reserved_1_31 : 31; 6838 u32 dbi_ro_wr_en : 1; 6839 } s; 6840 struct cvmx_pcieepx_cfg559_s cn73xx; 6841 struct cvmx_pcieepx_cfg559_s cn78xx; 6842 struct cvmx_pcieepx_cfg559_s cn78xxp1; 6843 struct cvmx_pcieepx_cfg559_s cnf75xx; 6844 }; 6845 6846 typedef union cvmx_pcieepx_cfg559 cvmx_pcieepx_cfg559_t; 6847 6848 #endif 6849