1Tiny Code Generator - Fabrice Bellard. 2 31) Introduction 4 5TCG (Tiny Code Generator) began as a generic backend for a C 6compiler. It was simplified to be used in QEMU. It also has its roots 7in the QOP code generator written by Paul Brook. 8 92) Definitions 10 11TCG receives RISC-like "TCG ops" and performs some optimizations on them, 12including liveness analysis and trivial constant expression 13evaluation. TCG ops are then implemented in the host CPU back end, 14also known as the TCG "target". 15 16The TCG "target" is the architecture for which we generate the 17code. It is of course not the same as the "target" of QEMU which is 18the emulated architecture. As TCG started as a generic C backend used 19for cross compiling, it is assumed that the TCG target is different 20from the host, although it is never the case for QEMU. 21 22In this document, we use "guest" to specify what architecture we are 23emulating; "target" always means the TCG target, the machine on which 24we are running QEMU. 25 26A TCG "function" corresponds to a QEMU Translated Block (TB). 27 28A TCG "temporary" is a variable only live in a basic 29block. Temporaries are allocated explicitly in each function. 30 31A TCG "local temporary" is a variable only live in a function. Local 32temporaries are allocated explicitly in each function. 33 34A TCG "global" is a variable which is live in all the functions 35(equivalent of a C global variable). They are defined before the 36functions defined. A TCG global can be a memory location (e.g. a QEMU 37CPU register), a fixed host register (e.g. the QEMU CPU state pointer) 38or a memory location which is stored in a register outside QEMU TBs 39(not implemented yet). 40 41A TCG "basic block" corresponds to a list of instructions terminated 42by a branch instruction. 43 44An operation with "undefined behavior" may result in a crash. 45 46An operation with "unspecified behavior" shall not crash. However, 47the result may be one of several possibilities so may be considered 48an "undefined result". 49 503) Intermediate representation 51 523.1) Introduction 53 54TCG instructions operate on variables which are temporaries, local 55temporaries or globals. TCG instructions and variables are strongly 56typed. Two types are supported: 32 bit integers and 64 bit 57integers. Pointers are defined as an alias to 32 bit or 64 bit 58integers depending on the TCG target word size. 59 60Each instruction has a fixed number of output variable operands, input 61variable operands and always constant operands. 62 63The notable exception is the call instruction which has a variable 64number of outputs and inputs. 65 66In the textual form, output operands usually come first, followed by 67input operands, followed by constant operands. The output type is 68included in the instruction name. Constants are prefixed with a '$'. 69 70add_i32 t0, t1, t2 (t0 <- t1 + t2) 71 723.2) Assumptions 73 74* Basic blocks 75 76- Basic blocks end after branches (e.g. brcond_i32 instruction), 77 goto_tb and exit_tb instructions. 78- Basic blocks start after the end of a previous basic block, or at a 79 set_label instruction. 80 81After the end of a basic block, the content of temporaries is 82destroyed, but local temporaries and globals are preserved. 83 84* Floating point types are not supported yet 85 86* Pointers: depending on the TCG target, pointer size is 32 bit or 64 87 bit. The type TCG_TYPE_PTR is an alias to TCG_TYPE_I32 or 88 TCG_TYPE_I64. 89 90* Helpers: 91 92Using the tcg_gen_helper_x_y it is possible to call any function 93taking i32, i64 or pointer types. By default, before calling a helper, 94all globals are stored at their canonical location and it is assumed 95that the function can modify them. By default, the helper is allowed to 96modify the CPU state or raise an exception. 97 98This can be overridden using the following function modifiers: 99- TCG_CALL_NO_READ_GLOBALS means that the helper does not read globals, 100 either directly or via an exception. They will not be saved to their 101 canonical locations before calling the helper. 102- TCG_CALL_NO_WRITE_GLOBALS means that the helper does not modify any globals. 103 They will only be saved to their canonical location before calling helpers, 104 but they won't be reloaded afterwards. 105- TCG_CALL_NO_SIDE_EFFECTS means that the call to the function is removed if 106 the return value is not used. 107 108Note that TCG_CALL_NO_READ_GLOBALS implies TCG_CALL_NO_WRITE_GLOBALS. 109 110On some TCG targets (e.g. x86), several calling conventions are 111supported. 112 113* Branches: 114 115Use the instruction 'br' to jump to a label. 116 1173.3) Code Optimizations 118 119When generating instructions, you can count on at least the following 120optimizations: 121 122- Single instructions are simplified, e.g. 123 124 and_i32 t0, t0, $0xffffffff 125 126 is suppressed. 127 128- A liveness analysis is done at the basic block level. The 129 information is used to suppress moves from a dead variable to 130 another one. It is also used to remove instructions which compute 131 dead results. The later is especially useful for condition code 132 optimization in QEMU. 133 134 In the following example: 135 136 add_i32 t0, t1, t2 137 add_i32 t0, t0, $1 138 mov_i32 t0, $1 139 140 only the last instruction is kept. 141 1423.4) Instruction Reference 143 144********* Function call 145 146* call <ret> <params> ptr 147 148call function 'ptr' (pointer type) 149 150<ret> optional 32 bit or 64 bit return value 151<params> optional 32 bit or 64 bit parameters 152 153********* Jumps/Labels 154 155* set_label $label 156 157Define label 'label' at the current program point. 158 159* br $label 160 161Jump to label. 162 163* brcond_i32/i64 t0, t1, cond, label 164 165Conditional jump if t0 cond t1 is true. cond can be: 166 TCG_COND_EQ 167 TCG_COND_NE 168 TCG_COND_LT /* signed */ 169 TCG_COND_GE /* signed */ 170 TCG_COND_LE /* signed */ 171 TCG_COND_GT /* signed */ 172 TCG_COND_LTU /* unsigned */ 173 TCG_COND_GEU /* unsigned */ 174 TCG_COND_LEU /* unsigned */ 175 TCG_COND_GTU /* unsigned */ 176 177********* Arithmetic 178 179* add_i32/i64 t0, t1, t2 180 181t0=t1+t2 182 183* sub_i32/i64 t0, t1, t2 184 185t0=t1-t2 186 187* neg_i32/i64 t0, t1 188 189t0=-t1 (two's complement) 190 191* mul_i32/i64 t0, t1, t2 192 193t0=t1*t2 194 195* div_i32/i64 t0, t1, t2 196 197t0=t1/t2 (signed). Undefined behavior if division by zero or overflow. 198 199* divu_i32/i64 t0, t1, t2 200 201t0=t1/t2 (unsigned). Undefined behavior if division by zero. 202 203* rem_i32/i64 t0, t1, t2 204 205t0=t1%t2 (signed). Undefined behavior if division by zero or overflow. 206 207* remu_i32/i64 t0, t1, t2 208 209t0=t1%t2 (unsigned). Undefined behavior if division by zero. 210 211********* Logical 212 213* and_i32/i64 t0, t1, t2 214 215t0=t1&t2 216 217* or_i32/i64 t0, t1, t2 218 219t0=t1|t2 220 221* xor_i32/i64 t0, t1, t2 222 223t0=t1^t2 224 225* not_i32/i64 t0, t1 226 227t0=~t1 228 229* andc_i32/i64 t0, t1, t2 230 231t0=t1&~t2 232 233* eqv_i32/i64 t0, t1, t2 234 235t0=~(t1^t2), or equivalently, t0=t1^~t2 236 237* nand_i32/i64 t0, t1, t2 238 239t0=~(t1&t2) 240 241* nor_i32/i64 t0, t1, t2 242 243t0=~(t1|t2) 244 245* orc_i32/i64 t0, t1, t2 246 247t0=t1|~t2 248 249* clz_i32/i64 t0, t1, t2 250 251t0 = t1 ? clz(t1) : t2 252 253* ctz_i32/i64 t0, t1, t2 254 255t0 = t1 ? ctz(t1) : t2 256 257* ctpop_i32/i64 t0, t1 258 259t0 = number of bits set in t1 260With "ctpop" short for "count population", matching 261the function name used in include/qemu/host-utils.h. 262 263********* Shifts/Rotates 264 265* shl_i32/i64 t0, t1, t2 266 267t0=t1 << t2. Unspecified behavior if t2 < 0 or t2 >= 32 (resp 64) 268 269* shr_i32/i64 t0, t1, t2 270 271t0=t1 >> t2 (unsigned). Unspecified behavior if t2 < 0 or t2 >= 32 (resp 64) 272 273* sar_i32/i64 t0, t1, t2 274 275t0=t1 >> t2 (signed). Unspecified behavior if t2 < 0 or t2 >= 32 (resp 64) 276 277* rotl_i32/i64 t0, t1, t2 278 279Rotation of t2 bits to the left. 280Unspecified behavior if t2 < 0 or t2 >= 32 (resp 64) 281 282* rotr_i32/i64 t0, t1, t2 283 284Rotation of t2 bits to the right. 285Unspecified behavior if t2 < 0 or t2 >= 32 (resp 64) 286 287********* Misc 288 289* mov_i32/i64 t0, t1 290 291t0 = t1 292 293Move t1 to t0 (both operands must have the same type). 294 295* ext8s_i32/i64 t0, t1 296ext8u_i32/i64 t0, t1 297ext16s_i32/i64 t0, t1 298ext16u_i32/i64 t0, t1 299ext32s_i64 t0, t1 300ext32u_i64 t0, t1 301 3028, 16 or 32 bit sign/zero extension (both operands must have the same type) 303 304* bswap16_i32/i64 t0, t1, flags 305 30616 bit byte swap on the low bits of a 32/64 bit input. 307If flags & TCG_BSWAP_IZ, then t1 is known to be zero-extended from bit 15. 308If flags & TCG_BSWAP_OZ, then t0 will be zero-extended from bit 15. 309If flags & TCG_BSWAP_OS, then t0 will be sign-extended from bit 15. 310If neither TCG_BSWAP_OZ nor TCG_BSWAP_OS are set, then the bits of 311t0 above bit 15 may contain any value. 312 313* bswap32_i64 t0, t1, flags 314 31532 bit byte swap on a 64-bit value. The flags are the same as for bswap16, 316except they apply from bit 31 instead of bit 15. 317 318* bswap32_i32 t0, t1, flags 319* bswap64_i64 t0, t1, flags 320 32132/64 bit byte swap. The flags are ignored, but still present 322for consistency with the other bswap opcodes. 323 324* discard_i32/i64 t0 325 326Indicate that the value of t0 won't be used later. It is useful to 327force dead code elimination. 328 329* deposit_i32/i64 dest, t1, t2, pos, len 330 331Deposit T2 as a bitfield into T1, placing the result in DEST. 332The bitfield is described by POS/LEN, which are immediate values: 333 334 LEN - the length of the bitfield 335 POS - the position of the first bit, counting from the LSB 336 337For example, "deposit_i32 dest, t1, t2, 8, 4" indicates a 4-bit field 338at bit 8. This operation would be equivalent to 339 340 dest = (t1 & ~0x0f00) | ((t2 << 8) & 0x0f00) 341 342* extract_i32/i64 dest, t1, pos, len 343* sextract_i32/i64 dest, t1, pos, len 344 345Extract a bitfield from T1, placing the result in DEST. 346The bitfield is described by POS/LEN, which are immediate values, 347as above for deposit. For extract_*, the result will be extended 348to the left with zeros; for sextract_*, the result will be extended 349to the left with copies of the bitfield sign bit at pos + len - 1. 350 351For example, "sextract_i32 dest, t1, 8, 4" indicates a 4-bit field 352at bit 8. This operation would be equivalent to 353 354 dest = (t1 << 20) >> 28 355 356(using an arithmetic right shift). 357 358* extract2_i32/i64 dest, t1, t2, pos 359 360For N = {32,64}, extract an N-bit quantity from the concatenation 361of t2:t1, beginning at pos. The tcg_gen_extract2_{i32,i64} expander 362accepts 0 <= pos <= N as inputs. The backend code generator will 363not see either 0 or N as inputs for these opcodes. 364 365* extrl_i64_i32 t0, t1 366 367For 64-bit hosts only, extract the low 32-bits of input T1 and place it 368into 32-bit output T0. Depending on the host, this may be a simple move, 369or may require additional canonicalization. 370 371* extrh_i64_i32 t0, t1 372 373For 64-bit hosts only, extract the high 32-bits of input T1 and place it 374into 32-bit output T0. Depending on the host, this may be a simple shift, 375or may require additional canonicalization. 376 377********* Conditional moves 378 379* setcond_i32/i64 dest, t1, t2, cond 380 381dest = (t1 cond t2) 382 383Set DEST to 1 if (T1 cond T2) is true, otherwise set to 0. 384 385* movcond_i32/i64 dest, c1, c2, v1, v2, cond 386 387dest = (c1 cond c2 ? v1 : v2) 388 389Set DEST to V1 if (C1 cond C2) is true, otherwise set to V2. 390 391********* Type conversions 392 393* ext_i32_i64 t0, t1 394Convert t1 (32 bit) to t0 (64 bit) and does sign extension 395 396* extu_i32_i64 t0, t1 397Convert t1 (32 bit) to t0 (64 bit) and does zero extension 398 399* trunc_i64_i32 t0, t1 400Truncate t1 (64 bit) to t0 (32 bit) 401 402* concat_i32_i64 t0, t1, t2 403Construct t0 (64-bit) taking the low half from t1 (32 bit) and the high half 404from t2 (32 bit). 405 406* concat32_i64 t0, t1, t2 407Construct t0 (64-bit) taking the low half from t1 (64 bit) and the high half 408from t2 (64 bit). 409 410********* Load/Store 411 412* ld_i32/i64 t0, t1, offset 413ld8s_i32/i64 t0, t1, offset 414ld8u_i32/i64 t0, t1, offset 415ld16s_i32/i64 t0, t1, offset 416ld16u_i32/i64 t0, t1, offset 417ld32s_i64 t0, t1, offset 418ld32u_i64 t0, t1, offset 419 420t0 = read(t1 + offset) 421Load 8, 16, 32 or 64 bits with or without sign extension from host memory. 422offset must be a constant. 423 424* st_i32/i64 t0, t1, offset 425st8_i32/i64 t0, t1, offset 426st16_i32/i64 t0, t1, offset 427st32_i64 t0, t1, offset 428 429write(t0, t1 + offset) 430Write 8, 16, 32 or 64 bits to host memory. 431 432All this opcodes assume that the pointed host memory doesn't correspond 433to a global. In the latter case the behaviour is unpredictable. 434 435********* Multiword arithmetic support 436 437* add2_i32/i64 t0_low, t0_high, t1_low, t1_high, t2_low, t2_high 438* sub2_i32/i64 t0_low, t0_high, t1_low, t1_high, t2_low, t2_high 439 440Similar to add/sub, except that the double-word inputs T1 and T2 are 441formed from two single-word arguments, and the double-word output T0 442is returned in two single-word outputs. 443 444* mulu2_i32/i64 t0_low, t0_high, t1, t2 445 446Similar to mul, except two unsigned inputs T1 and T2 yielding the full 447double-word product T0. The later is returned in two single-word outputs. 448 449* muls2_i32/i64 t0_low, t0_high, t1, t2 450 451Similar to mulu2, except the two inputs T1 and T2 are signed. 452 453* mulsh_i32/i64 t0, t1, t2 454* muluh_i32/i64 t0, t1, t2 455 456Provide the high part of a signed or unsigned multiply, respectively. 457If mulu2/muls2 are not provided by the backend, the tcg-op generator 458can obtain the same results can be obtained by emitting a pair of 459opcodes, mul+muluh/mulsh. 460 461********* Memory Barrier support 462 463* mb <$arg> 464 465Generate a target memory barrier instruction to ensure memory ordering as being 466enforced by a corresponding guest memory barrier instruction. The ordering 467enforced by the backend may be stricter than the ordering required by the guest. 468It cannot be weaker. This opcode takes a constant argument which is required to 469generate the appropriate barrier instruction. The backend should take care to 470emit the target barrier instruction only when necessary i.e., for SMP guests and 471when MTTCG is enabled. 472 473The guest translators should generate this opcode for all guest instructions 474which have ordering side effects. 475 476Please see docs/devel/atomics.rst for more information on memory barriers. 477 478********* 64-bit guest on 32-bit host support 479 480The following opcodes are internal to TCG. Thus they are to be implemented by 48132-bit host code generators, but are not to be emitted by guest translators. 482They are emitted as needed by inline functions within "tcg-op.h". 483 484* brcond2_i32 t0_low, t0_high, t1_low, t1_high, cond, label 485 486Similar to brcond, except that the 64-bit values T0 and T1 487are formed from two 32-bit arguments. 488 489* setcond2_i32 dest, t1_low, t1_high, t2_low, t2_high, cond 490 491Similar to setcond, except that the 64-bit values T1 and T2 are 492formed from two 32-bit arguments. The result is a 32-bit value. 493 494********* QEMU specific operations 495 496* exit_tb t0 497 498Exit the current TB and return the value t0 (word type). 499 500* goto_tb index 501 502Exit the current TB and jump to the TB index 'index' (constant) if the 503current TB was linked to this TB. Otherwise execute the next 504instructions. Only indices 0 and 1 are valid and tcg_gen_goto_tb may be issued 505at most once with each slot index per TB. 506 507* lookup_and_goto_ptr tb_addr 508 509Look up a TB address ('tb_addr') and jump to it if valid. If not valid, 510jump to the TCG epilogue to go back to the exec loop. 511 512This operation is optional. If the TCG backend does not implement the 513goto_ptr opcode, emitting this op is equivalent to emitting exit_tb(0). 514 515* qemu_ld_i32/i64 t0, t1, flags, memidx 516* qemu_st_i32/i64 t0, t1, flags, memidx 517* qemu_st8_i32 t0, t1, flags, memidx 518 519Load data at the guest address t1 into t0, or store data in t0 at guest 520address t1. The _i32/_i64 size applies to the size of the input/output 521register t0 only. The address t1 is always sized according to the guest, 522and the width of the memory operation is controlled by flags. 523 524Both t0 and t1 may be split into little-endian ordered pairs of registers 525if dealing with 64-bit quantities on a 32-bit host. 526 527The memidx selects the qemu tlb index to use (e.g. user or kernel access). 528The flags are the MemOp bits, selecting the sign, width, and endianness 529of the memory access. 530 531For a 32-bit host, qemu_ld/st_i64 is guaranteed to only be used with a 53264-bit memory access specified in flags. 533 534For i386, qemu_st8_i32 is exactly like qemu_st_i32, except the size of 535the memory operation is known to be 8-bit. This allows the backend to 536provide a different set of register constraints. 537 538********* Host vector operations 539 540All of the vector ops have two parameters, TCGOP_VECL & TCGOP_VECE. 541The former specifies the length of the vector in log2 64-bit units; the 542later specifies the length of the element (if applicable) in log2 8-bit units. 543E.g. VECL=1 -> 64 << 1 -> v128, and VECE=2 -> 1 << 2 -> i32. 544 545* mov_vec v0, v1 546* ld_vec v0, t1 547* st_vec v0, t1 548 549 Move, load and store. 550 551* dup_vec v0, r1 552 553 Duplicate the low N bits of R1 into VECL/VECE copies across V0. 554 555* dupi_vec v0, c 556 557 Similarly, for a constant. 558 Smaller values will be replicated to host register size by the expanders. 559 560* dup2_vec v0, r1, r2 561 562 Duplicate r2:r1 into VECL/64 copies across V0. This opcode is 563 only present for 32-bit hosts. 564 565* add_vec v0, v1, v2 566 567 v0 = v1 + v2, in elements across the vector. 568 569* sub_vec v0, v1, v2 570 571 Similarly, v0 = v1 - v2. 572 573* mul_vec v0, v1, v2 574 575 Similarly, v0 = v1 * v2. 576 577* neg_vec v0, v1 578 579 Similarly, v0 = -v1. 580 581* abs_vec v0, v1 582 583 Similarly, v0 = v1 < 0 ? -v1 : v1, in elements across the vector. 584 585* smin_vec: 586* umin_vec: 587 588 Similarly, v0 = MIN(v1, v2), for signed and unsigned element types. 589 590* smax_vec: 591* umax_vec: 592 593 Similarly, v0 = MAX(v1, v2), for signed and unsigned element types. 594 595* ssadd_vec: 596* sssub_vec: 597* usadd_vec: 598* ussub_vec: 599 600 Signed and unsigned saturating addition and subtraction. If the true 601 result is not representable within the element type, the element is 602 set to the minimum or maximum value for the type. 603 604* and_vec v0, v1, v2 605* or_vec v0, v1, v2 606* xor_vec v0, v1, v2 607* andc_vec v0, v1, v2 608* orc_vec v0, v1, v2 609* not_vec v0, v1 610 611 Similarly, logical operations with and without complement. 612 Note that VECE is unused. 613 614* shli_vec v0, v1, i2 615* shls_vec v0, v1, s2 616 617 Shift all elements from v1 by a scalar i2/s2. I.e. 618 619 for (i = 0; i < VECL/VECE; ++i) { 620 v0[i] = v1[i] << s2; 621 } 622 623* shri_vec v0, v1, i2 624* sari_vec v0, v1, i2 625* rotli_vec v0, v1, i2 626* shrs_vec v0, v1, s2 627* sars_vec v0, v1, s2 628 629 Similarly for logical and arithmetic right shift, and left rotate. 630 631* shlv_vec v0, v1, v2 632 633 Shift elements from v1 by elements from v2. I.e. 634 635 for (i = 0; i < VECL/VECE; ++i) { 636 v0[i] = v1[i] << v2[i]; 637 } 638 639* shrv_vec v0, v1, v2 640* sarv_vec v0, v1, v2 641* rotlv_vec v0, v1, v2 642* rotrv_vec v0, v1, v2 643 644 Similarly for logical and arithmetic right shift, and rotates. 645 646* cmp_vec v0, v1, v2, cond 647 648 Compare vectors by element, storing -1 for true and 0 for false. 649 650* bitsel_vec v0, v1, v2, v3 651 652 Bitwise select, v0 = (v2 & v1) | (v3 & ~v1), across the entire vector. 653 654* cmpsel_vec v0, c1, c2, v3, v4, cond 655 656 Select elements based on comparison results: 657 for (i = 0; i < n; ++i) { 658 v0[i] = (c1[i] cond c2[i]) ? v3[i] : v4[i]. 659 } 660 661********* 662 663Note 1: Some shortcuts are defined when the last operand is known to be 664a constant (e.g. addi for add, movi for mov). 665 666Note 2: When using TCG, the opcodes must never be generated directly 667as some of them may not be available as "real" opcodes. Always use the 668function tcg_gen_xxx(args). 669 6704) Backend 671 672tcg-target.h contains the target specific definitions. tcg-target.c.inc 673contains the target specific code; it is #included by tcg/tcg.c, rather 674than being a standalone C file. 675 6764.1) Assumptions 677 678The target word size (TCG_TARGET_REG_BITS) is expected to be 32 bit or 67964 bit. It is expected that the pointer has the same size as the word. 680 681On a 32 bit target, all 64 bit operations are converted to 32 bits. A 682few specific operations must be implemented to allow it (see add2_i32, 683sub2_i32, brcond2_i32). 684 685On a 64 bit target, the values are transferred between 32 and 64-bit 686registers using the following ops: 687- trunc_shr_i64_i32 688- ext_i32_i64 689- extu_i32_i64 690 691They ensure that the values are correctly truncated or extended when 692moved from a 32-bit to a 64-bit register or vice-versa. Note that the 693trunc_shr_i64_i32 is an optional op. It is not necessary to implement 694it if all the following conditions are met: 695- 64-bit registers can hold 32-bit values 696- 32-bit values in a 64-bit register do not need to stay zero or 697 sign extended 698- all 32-bit TCG ops ignore the high part of 64-bit registers 699 700Floating point operations are not supported in this version. A 701previous incarnation of the code generator had full support of them, 702but it is better to concentrate on integer operations first. 703 7044.2) Constraints 705 706GCC like constraints are used to define the constraints of every 707instruction. Memory constraints are not supported in this 708version. Aliases are specified in the input operands as for GCC. 709 710The same register may be used for both an input and an output, even when 711they are not explicitly aliased. If an op expands to multiple target 712instructions then care must be taken to avoid clobbering input values. 713GCC style "early clobber" outputs are supported, with '&'. 714 715A target can define specific register or constant constraints. If an 716operation uses a constant input constraint which does not allow all 717constants, it must also accept registers in order to have a fallback. 718The constraint 'i' is defined generically to accept any constant. 719The constraint 'r' is not defined generically, but is consistently 720used by each backend to indicate all registers. 721 722The movi_i32 and movi_i64 operations must accept any constants. 723 724The mov_i32 and mov_i64 operations must accept any registers of the 725same type. 726 727The ld/st/sti instructions must accept signed 32 bit constant offsets. 728This can be implemented by reserving a specific register in which to 729compute the address if the offset is too big. 730 731The ld/st instructions must accept any destination (ld) or source (st) 732register. 733 734The sti instruction may fail if it cannot store the given constant. 735 7364.3) Function call assumptions 737 738- The only supported types for parameters and return value are: 32 and 739 64 bit integers and pointer. 740- The stack grows downwards. 741- The first N parameters are passed in registers. 742- The next parameters are passed on the stack by storing them as words. 743- Some registers are clobbered during the call. 744- The function can return 0 or 1 value in registers. On a 32 bit 745 target, functions must be able to return 2 values in registers for 746 64 bit return type. 747 7485) Recommended coding rules for best performance 749 750- Use globals to represent the parts of the QEMU CPU state which are 751 often modified, e.g. the integer registers and the condition 752 codes. TCG will be able to use host registers to store them. 753 754- Avoid globals stored in fixed registers. They must be used only to 755 store the pointer to the CPU state and possibly to store a pointer 756 to a register window. 757 758- Use temporaries. Use local temporaries only when really needed, 759 e.g. when you need to use a value after a jump. Local temporaries 760 introduce a performance hit in the current TCG implementation: their 761 content is saved to memory at end of each basic block. 762 763- Free temporaries and local temporaries when they are no longer used 764 (tcg_temp_free). Since tcg_const_x() also creates a temporary, you 765 should free it after it is used. Freeing temporaries does not yield 766 a better generated code, but it reduces the memory usage of TCG and 767 the speed of the translation. 768 769- Don't hesitate to use helpers for complicated or seldom used guest 770 instructions. There is little performance advantage in using TCG to 771 implement guest instructions taking more than about twenty TCG 772 instructions. Note that this rule of thumb is more applicable to 773 helpers doing complex logic or arithmetic, where the C compiler has 774 scope to do a good job of optimisation; it is less relevant where 775 the instruction is mostly doing loads and stores, and in those cases 776 inline TCG may still be faster for longer sequences. 777 778- The hard limit on the number of TCG instructions you can generate 779 per guest instruction is set by MAX_OP_PER_INSTR in exec-all.h -- 780 you cannot exceed this without risking a buffer overrun. 781 782- Use the 'discard' instruction if you know that TCG won't be able to 783 prove that a given global is "dead" at a given program point. The 784 x86 guest uses it to improve the condition codes optimisation. 785