1 /****************************************************************************** 2 * Copyright (c) 2013 IBM Corporation 3 * All rights reserved. 4 * This program and the accompanying materials 5 * are made available under the terms of the BSD License 6 * which accompanies this distribution, and is available at 7 * http://www.opensource.org/licenses/bsd-license.php 8 * 9 * Contributors: 10 * IBM Corporation - initial implementation 11 *****************************************************************************/ 12 /* 13 * Definitions for XHCI Controller - Revision 1.0 (5/21/10) 14 * 15 */ 16 17 #ifndef USB_XHCI_H 18 #define USB_XHCI_H 19 20 #include <stdint.h> 21 #include "usb-core.h" 22 23 #define BIT(x) (1 << x) 24 25 /* 5.3 Host Controller Capability Registers 26 * Table 19 27 */ 28 struct xhci_cap_regs { 29 uint8_t caplength; 30 uint8_t reserved; 31 uint16_t hciversion; 32 uint32_t hcsparams1; 33 uint32_t hcsparams2; 34 uint32_t hcsparams3; 35 uint32_t hccparams; 36 #define XHCI_HCCPARAMS_CSZ BIT(2) 37 #define XHCI_HCCPARAMS_XECP(x) ((x & 0xFFFF0000) >> 16) 38 uint32_t dboff; 39 uint32_t rtsoff; 40 } __attribute__ ((packed, aligned(4))); 41 42 /* USB 3.0: Section 7 and 7.2 */ 43 #define XHCI_XECP_CAP_ID(x) ((x & 0xF)) 44 #define XHCI_XECP_CAP_SP 2 45 #define XHCI_XECP_CAP_SP_MN(x) ((x & 0xFF0000) >> 16) 46 #define XHCI_XECP_CAP_SP_MJ(x) ((x & 0xFF000000) >> 24) 47 #define XHCI_XECP_CAP_SP_PC(x) ((x & 0xFF00) >> 8) 48 #define XHCI_XECP_CAP_SP_PO(x) (x & 0xFF) 49 #define XHCI_XECP_NEXT_PTR(x) ((x & 0xFF00) >> 8) 50 51 /* Table 27: Host Controller USB Port Register Set */ 52 struct xhci_port_regs { 53 uint32_t portsc; 54 #define PORTSC_CCS BIT(0) 55 #define PORTSC_PED BIT(1) 56 #define PORTSC_OCA BIT(3) 57 #define PORTSC_PR BIT(4) 58 #define PORTSC_PLS_MASK (0xF << 5) 59 #define PORTSC_PLS_U0 0 60 #define PORTSC_PLS_U1 1 61 #define PORTSC_PLS_U2 2 62 #define PORTSC_PLS_U3 3 63 #define PORTSC_PLS_DISABLED 4 64 #define PORTSC_PLS_RXDETECT 5 65 #define PORTSC_PLS_INACTIVE 6 66 #define PORTSC_PLS_POLLING 7 67 #define PORTSC_PLS_RECOVERY 8 68 #define PORTSC_PLS_HOTRESET 9 69 #define PORTSC_PLS_COMP_MODE 10 70 #define PORTSC_PLS_TEST_MODE 11 71 #define PORTSC_PLS_RESUME 15 72 #define PORTSC_PP BIT(9) 73 #define PORTSC_PS_MASK (0xF << 10) 74 #define PORTSC_PIC_MASK (0x3 << 14) 75 #define PORTSC_LWS BIT(16) 76 #define PORTSC_CSC BIT(17) 77 #define PORTSC_PEC BIT(18) 78 #define PORTSC_WRC BIT(19) 79 #define PORTSC_OCC BIT(20) 80 #define PORTSC_PRC BIT(21) 81 #define PORTSC_PLC BIT(22) 82 #define PORTSC_CEC BIT(23) 83 #define PORTSC_CAS BIT(24) 84 #define PORTSC_WCE BIT(25) 85 #define PORTSC_WDE BIT(26) 86 #define PORTSC_WOE BIT(27) 87 #define PORTSC_DR BIT(30) 88 #define PORTSC_WPR BIT(31) 89 90 uint32_t portpmsc; 91 uint32_t portli; 92 uint32_t reserved; 93 } __attribute__ ((packed, aligned(4))); 94 95 struct port_state { 96 bool PP; 97 bool CCS; 98 bool PED; 99 bool PR; 100 uint8_t PLS; 101 char *state; 102 }; 103 104 /* 5.4 Host Controller Operational Registers 105 * Table 26 106 */ 107 struct xhci_op_regs { 108 uint32_t usbcmd; 109 #define XHCI_USBCMD_RS BIT(0) 110 #define XHCI_USBCMD_HCRST BIT(1) 111 112 uint32_t usbsts; 113 #define XHCI_USBSTS_HCH BIT(0) 114 #define XHCI_USBSTS_CNR BIT(11) 115 116 uint32_t pagesize; 117 uint8_t reserved[8]; /* 0C - 13 */ 118 uint32_t dnctrl; /* Device notification control */ 119 uint64_t crcr; /* Command ring control */ 120 #define XHCI_CRCR_CRP_MASK 0xFFFFFFFFFFFFFFC0 121 #define XHCI_CRCR_CRR BIT(3) 122 #define XHCI_CRCR_CRP_SIZE 4096 123 124 uint8_t reserved1[16]; /* 20 - 2F */ 125 uint64_t dcbaap; /* Device Context Base Address Array Pointer */ 126 #define XHCI_DCBAAP_MAX_SIZE 2048 127 128 uint32_t config; /* Configure */ 129 #define XHCI_CONFIG_MAX_SLOT 44 130 131 uint8_t reserved2[964]; /* 3C - 3FF */ 132 /* USB Port register set */ 133 #define XHCI_PORT_MAX 256 134 struct xhci_port_regs prs[XHCI_PORT_MAX]; 135 } __attribute__ ((packed, aligned(8))); 136 137 /* 138 * 5.5.2 Interrupter Register Set 139 * Table 42: Interrupter Registers 140 */ 141 struct xhci_int_regs { 142 uint32_t iman; 143 uint32_t imod; 144 uint32_t erstsz; 145 #define XHCI_ERST_SIZE_MASK 0xFFFF 146 uint32_t reserved; 147 uint64_t erstba; 148 #define XHCI_ERST_ADDR_MASK (~(0x3FUL)) 149 uint64_t erdp; 150 #define XHCI_ERDP_MASK (~(0xFUL)) 151 } __attribute__ ((packed, aligned(8))); 152 153 /* 5.5 Host Controller Runtime Registers */ 154 struct xhci_run_regs { 155 uint32_t mfindex; /* microframe index */ 156 uint8_t reserved[28]; 157 #define XHCI_IRS_MAX 1024 158 struct xhci_int_regs irs[XHCI_IRS_MAX]; 159 } __attribute__ ((packed, aligned(8))); 160 161 /* 5.6 Doorbell Registers*/ 162 struct xhci_db_regs { 163 uint32_t db[256]; 164 } __attribute__ ((packed, aligned(4))); 165 166 #define COMP_SUCCESS 1 167 168 #define TRB_SLOT_ID(x) (((x) & (0xFF << 24)) >> 24) 169 #define TRB_CMD_SLOT_ID(x) ((x & 0xFF) << 24) 170 #define TRB_TYPE(x) (((x) & (0x3F << 10)) >> 10) 171 #define TRB_CMD_TYPE(x) ((x & 0x3F) << 10) 172 #define TRB_STATUS(x) (((x) & (0xFF << 24)) >> 24) 173 #define TRB_ADDR_LOW(x) ((uint32_t)((uint64_t)(x))) 174 #define TRB_ADDR_HIGH(x) ((uint32_t)((uint64_t)(x) >> 32)) 175 #define TRB_TRT(x) (((x) & 0x3) << 16 ) 176 #define TRB_DIR_IN BIT(16) 177 #define TRB_IOC BIT(5) 178 #define TRB_IDT BIT(6) 179 180 #define TRB_CYCLE_STATE BIT(0) 181 182 struct xhci_transfer_trb { 183 uint64_t addr; 184 uint32_t len; 185 uint32_t flags; 186 } __attribute__ ((packed)); 187 188 struct xhci_link_trb { 189 uint64_t addr; 190 uint32_t field2; 191 uint32_t field3; 192 } __attribute__ ((packed)); 193 194 /* Event TRB */ 195 struct xhci_event_trb { 196 uint64_t addr; 197 uint32_t status; 198 uint32_t flags; 199 } __attribute__ ((packed)); 200 201 #define TRB_NORMAL 1 202 #define TRB_SETUP_STAGE 2 203 #define TRB_DATA_STAGE 3 204 #define TRB_STATUS_STAGE 4 205 #define TRB_ISOCH 5 206 #define TRB_LINK 6 207 #define TRB_EVENT_DATA 7 208 #define TRB_NOOP 8 209 #define TRB_ENABLE_SLOT 9 210 #define TRB_DISABLE_SLOT 10 211 #define TRB_ADDRESS_DEV 11 212 #define TRB_CONFIG_EP 12 213 #define TRB_EVAL_CNTX 13 214 #define TRB_TRANSFER_EVENT 32 215 #define TRB_CMD_COMPLETION 33 216 #define TRB_PORT_STATUS 34 217 218 struct xhci_command_trb { 219 uint32_t field[4]; 220 }__attribute__ ((packed)); 221 222 union xhci_trb { 223 struct xhci_event_trb event; 224 struct xhci_transfer_trb xfer; 225 struct xhci_command_trb cmd; 226 struct xhci_link_trb link; 227 }; 228 229 enum xhci_seg_type { 230 TYPE_CTRL = 0, 231 TYPE_BULK, 232 TYPE_COMMAND, 233 TYPE_EVENT, 234 }; 235 236 struct xhci_seg { 237 union xhci_trb *trbs; 238 struct xhci_seg *next; 239 uint64_t enq; 240 uint64_t deq; 241 uint64_t trbs_dma; 242 uint32_t size; 243 uint32_t cycle_state; 244 enum xhci_seg_type type; 245 }; 246 247 #define XHCI_TRB_SIZE 16 248 #define XHCI_EVENT_TRBS_SIZE 4096 249 #define XHCI_CONTROL_TRBS_SIZE 4096 250 #define XHCI_DATA_TRBS_SIZE 4096 251 #define XHCI_INTR_TRBS_SIZE 4096 252 #define XHCI_ERST_NUM_SEGS 1 253 254 #define XHCI_POLL_NO_WAIT 1 255 256 #define XHCI_MAX_BULK_SIZE 0xF000 257 258 struct xhci_erst_entry { 259 uint64_t addr; 260 uint32_t size; 261 uint32_t reserved; 262 } __attribute__ ((packed, aligned(8))); 263 264 struct xhci_erst { 265 struct xhci_erst_entry *entries; 266 uint64_t dma; 267 uint32_t num_segs; /* number of segments */ 268 }; 269 270 struct xhci_control_ctx { 271 uint32_t d_flags; 272 uint32_t a_flags; 273 uint32_t reserved[6]; 274 } __attribute__ ((packed)); 275 276 struct xhci_slot_ctx { 277 uint32_t field1; 278 #define SLOT_SPEED_FS BIT(20) 279 #define SLOT_SPEED_LS BIT(21) 280 #define SLOT_SPEED_HS BIT(22) 281 #define SLOT_SPEED_SS BIT(23) 282 #define LAST_CONTEXT(x) (x << 27) 283 284 uint32_t field2; 285 #define ROOT_HUB_PORT(x) ((x & 0xff) << 16) 286 287 uint32_t field3; 288 uint32_t field4; 289 #define USB_DEV_ADDRESS(x) (x & 0xFFU) 290 #define SLOT_STATE(x) ((x >> 27) & 0x1FU) 291 #define SLOT_STATE_DIS_ENA 0 292 #define SLOT_STATE_DEFAULT 1 293 #define SLOT_STATE_ADDRESSED 2 294 #define SLOT_STATE_CONFIGURED 3 295 296 297 uint32_t reserved[4]; 298 } __attribute__ ((packed)); 299 300 struct xhci_ep_ctx { 301 uint32_t field1; 302 uint32_t field2; 303 #define MAX_PACKET_SIZE(x) (((x) & 0xFFFF) << 16) 304 #define MAX_BURST(x) (((x) & 0xFF) << 8) 305 #define EP_TYPE(x) (((x) & 0x07) << 3) 306 #define EP_ISOC_OUT 1 307 #define EP_BULK_OUT 2 308 #define EP_INT_OUT 3 309 #define EP_CTRL 4 310 #define EP_ISOC_IN 5 311 #define EP_BULK_IN 6 312 #define EP_INT_IN 7 313 314 #define ERROR_COUNT(x) (((x) & 0x03) << 1) 315 316 uint64_t deq_addr; 317 uint32_t field4; 318 uint32_t reserved[3]; 319 } __attribute__ ((packed)); 320 321 struct xhci_ctx { 322 uint8_t type; 323 #define XHCI_CTX_TYPE_DEVICE 0x1 324 #define XHCI_CTX_TYPE_INPUT 0x2 325 uint32_t size; 326 uint8_t *addr; 327 #define XHCI_CTX_BUF_SIZE 4096 328 uint64_t dma_addr; 329 }; 330 331 struct xhci_dev { 332 struct usb_dev *dev; 333 uint32_t slot_id; 334 struct xhci_ctx in_ctx; 335 struct xhci_ctx out_ctx; 336 struct xhci_seg control; 337 struct xhci_seg intr; 338 struct xhci_seg bulk_in; 339 struct xhci_seg bulk_out; 340 uint32_t ctx_size; 341 }; 342 343 struct xhci_hcd { 344 struct xhci_cap_regs *cap_regs; 345 struct xhci_op_regs *op_regs; 346 struct xhci_run_regs *run_regs; 347 struct xhci_db_regs *db_regs; 348 struct usb_hcd_dev *hcidev; 349 struct xhci_dev xdevs[XHCI_CONFIG_MAX_SLOT + 1]; 350 struct usb_pipe *freelist; 351 struct usb_pipe *end; 352 uint64_t *dcbaap; 353 uint64_t dcbaap_dma; 354 struct xhci_seg ering; 355 struct xhci_seg crseg; 356 struct xhci_erst erst; 357 uint64_t erds_dma; 358 uint32_t erds_size; 359 uint32_t slot_id; 360 uint32_t hcc_csz_64; 361 void *pool; 362 #define XHCI_PIPE_POOL_SIZE 4096 363 364 long pool_phys; 365 }; 366 367 struct xhci_pipe { 368 struct usb_pipe pipe; 369 struct xhci_seg *seg; 370 void *buf; 371 long buf_phys; 372 uint32_t buflen; 373 }; 374 375 extern bool usb3_dev_init(struct xhci_hcd *xhcd, struct usb_dev *hub, 376 uint32_t port, uint32_t slotspeed); 377 378 #endif /* USB_XHCI_H */ 379