1 // Code for handling OHCI USB controllers.
2 //
3 // Copyright (C) 2009 Kevin O'Connor <kevin@koconnor.net>
4 //
5 // This file may be distributed under the terms of the GNU LGPLv3 license.
6
7 #include "biosvar.h" // GET_LOWFLAT
8 #include "config.h" // CONFIG_*
9 #include "malloc.h" // free
10 #include "memmap.h" // PAGE_SIZE
11 #include "output.h" // dprintf
12 #include "pcidevice.h" // foreachpci
13 #include "pci_ids.h" // PCI_CLASS_SERIAL_USB_OHCI
14 #include "pci_regs.h" // PCI_BASE_ADDRESS_0
15 #include "string.h" // memset
16 #include "usb.h" // struct usb_s
17 #include "usb-ehci.h" // ehci_wait_controllers
18 #include "usb-ohci.h" // struct ohci_hcca
19 #include "util.h" // msleep
20 #include "x86.h" // readl
21
22 #define FIT (1 << 31)
23
24 struct usb_ohci_s {
25 struct usb_s usb;
26 struct ohci_regs *regs;
27 };
28
29 struct ohci_pipe {
30 struct ohci_ed ed;
31 struct usb_pipe pipe;
32 struct ohci_regs *regs;
33 void *data;
34 int count;
35 struct ohci_td *tds;
36 };
37
38
39 /****************************************************************
40 * Root hub
41 ****************************************************************/
42
43 // Check if device attached to port
44 static int
ohci_hub_detect(struct usbhub_s * hub,u32 port)45 ohci_hub_detect(struct usbhub_s *hub, u32 port)
46 {
47 struct usb_ohci_s *cntl = container_of(hub->cntl, struct usb_ohci_s, usb);
48 u32 sts = readl(&cntl->regs->roothub_portstatus[port]);
49 return (sts & RH_PS_CCS) ? 1 : 0;
50 }
51
52 // Disable port
53 static void
ohci_hub_disconnect(struct usbhub_s * hub,u32 port)54 ohci_hub_disconnect(struct usbhub_s *hub, u32 port)
55 {
56 struct usb_ohci_s *cntl = container_of(hub->cntl, struct usb_ohci_s, usb);
57 writel(&cntl->regs->roothub_portstatus[port], RH_PS_CCS|RH_PS_LSDA);
58 }
59
60 // Reset device on port
61 static int
ohci_hub_reset(struct usbhub_s * hub,u32 port)62 ohci_hub_reset(struct usbhub_s *hub, u32 port)
63 {
64 struct usb_ohci_s *cntl = container_of(hub->cntl, struct usb_ohci_s, usb);
65 writel(&cntl->regs->roothub_portstatus[port], RH_PS_PRS);
66 u32 sts;
67 u32 end = timer_calc(USB_TIME_DRSTR * 2);
68 for (;;) {
69 sts = readl(&cntl->regs->roothub_portstatus[port]);
70 if (!(sts & RH_PS_PRS))
71 // XXX - need to ensure USB_TIME_DRSTR time in reset?
72 break;
73 if (timer_check(end)) {
74 // Timeout.
75 warn_timeout();
76 ohci_hub_disconnect(hub, port);
77 return -1;
78 }
79 yield();
80 }
81
82 if ((sts & (RH_PS_CCS|RH_PS_PES)) != (RH_PS_CCS|RH_PS_PES))
83 // Device no longer present
84 return -1;
85
86 return !!(sts & RH_PS_LSDA);
87 }
88
89 static struct usbhub_op_s ohci_HubOp = {
90 .detect = ohci_hub_detect,
91 .reset = ohci_hub_reset,
92 .disconnect = ohci_hub_disconnect,
93 };
94
95 // Find any devices connected to the root hub.
96 static int
check_ohci_ports(struct usb_ohci_s * cntl)97 check_ohci_ports(struct usb_ohci_s *cntl)
98 {
99 ASSERT32FLAT();
100 // Wait for ehci init - in case this is a "companion controller"
101 ehci_wait_controllers();
102 // Turn on power for all devices on roothub.
103 u32 rha = readl(&cntl->regs->roothub_a);
104 rha &= ~(RH_A_PSM | RH_A_OCPM);
105 writel(&cntl->regs->roothub_status, RH_HS_LPSC);
106 writel(&cntl->regs->roothub_b, RH_B_PPCM);
107 msleep((rha >> 24) * 2);
108 // XXX - need to sleep for USB_TIME_SIGATT if just powered up?
109
110 struct usbhub_s hub;
111 memset(&hub, 0, sizeof(hub));
112 hub.cntl = &cntl->usb;
113 hub.portcount = rha & RH_A_NDP;
114 hub.op = &ohci_HubOp;
115 usb_enumerate(&hub);
116 return hub.devcount;
117 }
118
119
120 /****************************************************************
121 * Setup
122 ****************************************************************/
123
124 // Wait for next USB frame to start - for ensuring safe memory release.
125 static void
ohci_waittick(struct ohci_regs * regs)126 ohci_waittick(struct ohci_regs *regs)
127 {
128 barrier();
129 struct ohci_hcca *hcca = (void*)regs->hcca;
130 u32 startframe = hcca->frame_no;
131 u32 end = timer_calc(1000 * 5);
132 for (;;) {
133 if (hcca->frame_no != startframe)
134 break;
135 if (timer_check(end)) {
136 warn_timeout();
137 return;
138 }
139 yield();
140 }
141 }
142
143 static void
ohci_free_pipes(struct usb_ohci_s * cntl)144 ohci_free_pipes(struct usb_ohci_s *cntl)
145 {
146 dprintf(7, "ohci_free_pipes %p\n", cntl);
147
148 u32 creg = readl(&cntl->regs->control);
149 if (creg & (OHCI_CTRL_CLE|OHCI_CTRL_BLE)) {
150 writel(&cntl->regs->control, creg & ~(OHCI_CTRL_CLE|OHCI_CTRL_BLE));
151 ohci_waittick(cntl->regs);
152 }
153
154 u32 *pos = &cntl->regs->ed_controlhead;
155 for (;;) {
156 struct ohci_ed *next = (void*)*pos;
157 if (!next)
158 break;
159 struct ohci_pipe *pipe = container_of(next, struct ohci_pipe, ed);
160 if (usb_is_freelist(&cntl->usb, &pipe->pipe)) {
161 *pos = next->hwNextED;
162 free(pipe);
163 } else {
164 pos = &next->hwNextED;
165 }
166 }
167
168 writel(&cntl->regs->ed_controlcurrent, 0);
169 writel(&cntl->regs->ed_bulkcurrent, 0);
170 writel(&cntl->regs->control, creg);
171 cntl->usb.freelist = NULL;
172 }
173
174 static int
start_ohci(struct usb_ohci_s * cntl,struct ohci_hcca * hcca)175 start_ohci(struct usb_ohci_s *cntl, struct ohci_hcca *hcca)
176 {
177 u32 oldfminterval = readl(&cntl->regs->fminterval);
178 u32 oldrwc = readl(&cntl->regs->control) & OHCI_CTRL_RWC;
179
180 // XXX - check if already running?
181
182 // Do reset
183 writel(&cntl->regs->control, OHCI_USB_RESET | oldrwc);
184 readl(&cntl->regs->control); // flush writes
185 msleep(USB_TIME_DRSTR);
186
187 // Do software init (min 10us, max 2ms)
188 u32 end = timer_calc_usec(10);
189 writel(&cntl->regs->cmdstatus, OHCI_HCR);
190 for (;;) {
191 u32 status = readl(&cntl->regs->cmdstatus);
192 if (! status & OHCI_HCR)
193 break;
194 if (timer_check(end)) {
195 warn_timeout();
196 return -1;
197 }
198 }
199
200 // Init memory
201 writel(&cntl->regs->ed_controlhead, 0);
202 writel(&cntl->regs->ed_bulkhead, 0);
203 writel(&cntl->regs->hcca, (u32)hcca);
204
205 // Init fminterval
206 u32 fi = oldfminterval & 0x3fff;
207 writel(&cntl->regs->fminterval
208 , (((oldfminterval & FIT) ^ FIT)
209 | fi | (((6 * (fi - 210)) / 7) << 16)));
210 writel(&cntl->regs->periodicstart, ((9 * fi) / 10) & 0x3fff);
211 readl(&cntl->regs->control); // flush writes
212
213 // XXX - verify that fminterval was setup correctly.
214
215 // Go into operational state
216 writel(&cntl->regs->control
217 , (OHCI_CTRL_CBSR | OHCI_CTRL_CLE | OHCI_CTRL_BLE | OHCI_CTRL_PLE
218 | OHCI_USB_OPER | oldrwc));
219 readl(&cntl->regs->control); // flush writes
220
221 return 0;
222 }
223
224 static void
stop_ohci(struct usb_ohci_s * cntl)225 stop_ohci(struct usb_ohci_s *cntl)
226 {
227 u32 oldrwc = readl(&cntl->regs->control) & OHCI_CTRL_RWC;
228 writel(&cntl->regs->control, oldrwc);
229 readl(&cntl->regs->control); // flush writes
230 }
231
232 static void
configure_ohci(void * data)233 configure_ohci(void *data)
234 {
235 struct usb_ohci_s *cntl = data;
236
237 // Allocate memory
238 struct ohci_hcca *hcca = memalign_high(256, sizeof(*hcca));
239 struct ohci_ed *intr_ed = malloc_high(sizeof(*intr_ed));
240 if (!hcca || !intr_ed) {
241 warn_noalloc();
242 goto free;
243 }
244 memset(hcca, 0, sizeof(*hcca));
245 memset(intr_ed, 0, sizeof(*intr_ed));
246 intr_ed->hwINFO = ED_SKIP;
247 int i;
248 for (i=0; i<ARRAY_SIZE(hcca->int_table); i++)
249 hcca->int_table[i] = (u32)intr_ed;
250
251 int ret = start_ohci(cntl, hcca);
252 if (ret)
253 goto err;
254
255 int count = check_ohci_ports(cntl);
256 ohci_free_pipes(cntl);
257 if (! count)
258 goto err;
259 return;
260
261 err:
262 stop_ohci(cntl);
263 free:
264 free(hcca);
265 free(intr_ed);
266 }
267
268 static void
ohci_controller_setup(struct pci_device * pci)269 ohci_controller_setup(struct pci_device *pci)
270 {
271 struct ohci_regs *regs = pci_enable_membar(pci, PCI_BASE_ADDRESS_0);
272 if (!regs)
273 return;
274
275 struct usb_ohci_s *cntl = malloc_tmphigh(sizeof(*cntl));
276 if (!cntl) {
277 warn_noalloc();
278 return;
279 }
280 memset(cntl, 0, sizeof(*cntl));
281 cntl->usb.pci = pci;
282 cntl->usb.type = USB_TYPE_OHCI;
283 cntl->regs = regs;
284
285 dprintf(1, "OHCI init on dev %pP (regs=%p)\n", pci, cntl->regs);
286
287 pci_enable_busmaster(pci);
288
289 // XXX - check for and disable SMM control?
290
291 // Disable interrupts
292 writel(&cntl->regs->intrdisable, ~0);
293 writel(&cntl->regs->intrstatus, ~0);
294
295 run_thread(configure_ohci, cntl);
296 }
297
298 void
ohci_setup(void)299 ohci_setup(void)
300 {
301 if (! CONFIG_USB_OHCI)
302 return;
303 struct pci_device *pci;
304 foreachpci(pci) {
305 if (pci_classprog(pci) == PCI_CLASS_SERIAL_USB_OHCI)
306 ohci_controller_setup(pci);
307 }
308 }
309
310
311 /****************************************************************
312 * End point communication
313 ****************************************************************/
314
315 // Setup fields in ed
316 static void
ohci_desc2pipe(struct ohci_pipe * pipe,struct usbdevice_s * usbdev,struct usb_endpoint_descriptor * epdesc)317 ohci_desc2pipe(struct ohci_pipe *pipe, struct usbdevice_s *usbdev
318 , struct usb_endpoint_descriptor *epdesc)
319 {
320 usb_desc2pipe(&pipe->pipe, usbdev, epdesc);
321 pipe->ed.hwINFO = (ED_SKIP | usbdev->devaddr | (pipe->pipe.ep << 7)
322 | (epdesc->wMaxPacketSize << 16)
323 | (usbdev->speed ? ED_LOWSPEED : 0));
324 struct usb_ohci_s *cntl = container_of(
325 usbdev->hub->cntl, struct usb_ohci_s, usb);
326 pipe->regs = cntl->regs;
327 }
328
329 static struct usb_pipe *
ohci_alloc_intr_pipe(struct usbdevice_s * usbdev,struct usb_endpoint_descriptor * epdesc)330 ohci_alloc_intr_pipe(struct usbdevice_s *usbdev
331 , struct usb_endpoint_descriptor *epdesc)
332 {
333 struct usb_ohci_s *cntl = container_of(
334 usbdev->hub->cntl, struct usb_ohci_s, usb);
335 int frameexp = usb_get_period(usbdev, epdesc);
336 dprintf(7, "ohci_alloc_intr_pipe %p %d\n", &cntl->usb, frameexp);
337
338 if (frameexp > 5)
339 frameexp = 5;
340 int maxpacket = epdesc->wMaxPacketSize;
341 // Determine number of entries needed for 2 timer ticks.
342 int ms = 1<<frameexp;
343 int count = DIV_ROUND_UP(ticks_to_ms(2), ms) + 1;
344 struct ohci_pipe *pipe = malloc_low(sizeof(*pipe));
345 struct ohci_td *tds = malloc_low(sizeof(*tds) * count);
346 void *data = malloc_low(maxpacket * count);
347 if (!pipe || !tds || !data)
348 goto err;
349 memset(pipe, 0, sizeof(*pipe));
350 ohci_desc2pipe(pipe, usbdev, epdesc);
351 pipe->ed.hwINFO &= ~ED_SKIP;
352 pipe->data = data;
353 pipe->count = count;
354 pipe->tds = tds;
355
356 struct ohci_ed *ed = &pipe->ed;
357 ed->hwHeadP = (u32)&tds[0];
358 ed->hwTailP = (u32)&tds[count-1];
359
360 int i;
361 for (i=0; i<count-1; i++) {
362 tds[i].hwINFO = TD_DP_IN | TD_T_TOGGLE | TD_CC;
363 tds[i].hwCBP = (u32)data + maxpacket * i;
364 tds[i].hwNextTD = (u32)&tds[i+1];
365 tds[i].hwBE = tds[i].hwCBP + maxpacket - 1;
366 }
367
368 // Add to interrupt schedule.
369 struct ohci_hcca *hcca = (void*)cntl->regs->hcca;
370 if (frameexp == 0) {
371 // Add to existing interrupt entry.
372 struct ohci_ed *intr_ed = (void*)hcca->int_table[0];
373 ed->hwNextED = intr_ed->hwNextED;
374 barrier();
375 intr_ed->hwNextED = (u32)ed;
376 } else {
377 int startpos = 1<<(frameexp-1);
378 ed->hwNextED = hcca->int_table[startpos];
379 barrier();
380 for (i=startpos; i<ARRAY_SIZE(hcca->int_table); i+=ms)
381 hcca->int_table[i] = (u32)ed;
382 }
383
384 return &pipe->pipe;
385
386 err:
387 free(pipe);
388 free(tds);
389 free(data);
390 return NULL;
391 }
392
393 struct usb_pipe *
ohci_realloc_pipe(struct usbdevice_s * usbdev,struct usb_pipe * upipe,struct usb_endpoint_descriptor * epdesc)394 ohci_realloc_pipe(struct usbdevice_s *usbdev, struct usb_pipe *upipe
395 , struct usb_endpoint_descriptor *epdesc)
396 {
397 if (! CONFIG_USB_OHCI)
398 return NULL;
399 usb_add_freelist(upipe);
400 if (!epdesc)
401 return NULL;
402 u8 eptype = epdesc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
403 if (eptype == USB_ENDPOINT_XFER_INT)
404 return ohci_alloc_intr_pipe(usbdev, epdesc);
405 struct usb_ohci_s *cntl = container_of(
406 usbdev->hub->cntl, struct usb_ohci_s, usb);
407 dprintf(7, "ohci_alloc_async_pipe %p\n", &cntl->usb);
408
409 struct usb_pipe *usbpipe = usb_get_freelist(&cntl->usb, eptype);
410 if (usbpipe) {
411 // Use previously allocated pipe.
412 struct ohci_pipe *pipe = container_of(usbpipe, struct ohci_pipe, pipe);
413 ohci_desc2pipe(pipe, usbdev, epdesc);
414 return usbpipe;
415 }
416
417 // Allocate a new queue head.
418 struct ohci_pipe *pipe;
419 if (eptype == USB_ENDPOINT_XFER_CONTROL)
420 pipe = malloc_tmphigh(sizeof(*pipe));
421 else
422 pipe = malloc_low(sizeof(*pipe));
423 if (!pipe) {
424 warn_noalloc();
425 return NULL;
426 }
427 memset(pipe, 0, sizeof(*pipe));
428 ohci_desc2pipe(pipe, usbdev, epdesc);
429
430 // Add queue head to controller list.
431 u32 *head = &cntl->regs->ed_controlhead;
432 if (eptype != USB_ENDPOINT_XFER_CONTROL)
433 head = &cntl->regs->ed_bulkhead;
434 pipe->ed.hwNextED = *head;
435 barrier();
436 *head = (u32)&pipe->ed;
437 return &pipe->pipe;
438 }
439
440 static int
wait_ed(struct ohci_ed * ed,int timeout)441 wait_ed(struct ohci_ed *ed, int timeout)
442 {
443 u32 end = timer_calc(timeout);
444 for (;;) {
445 if ((ed->hwHeadP & ~(ED_C|ED_H)) == ed->hwTailP)
446 return 0;
447 if (timer_check(end)) {
448 warn_timeout();
449 dprintf(1, "ohci ed info=%x tail=%x head=%x next=%x\n"
450 , ed->hwINFO, ed->hwTailP, ed->hwHeadP, ed->hwNextED);
451 return -1;
452 }
453 yield();
454 }
455 }
456
457 #define STACKOTDS 18
458 #define OHCI_TD_ALIGN 16
459
460 int
ohci_send_pipe(struct usb_pipe * p,int dir,const void * cmd,void * data,int datasize)461 ohci_send_pipe(struct usb_pipe *p, int dir, const void *cmd
462 , void *data, int datasize)
463 {
464 ASSERT32FLAT();
465 if (! CONFIG_USB_OHCI)
466 return -1;
467 dprintf(7, "ohci_send_pipe %p\n", p);
468 struct ohci_pipe *pipe = container_of(p, struct ohci_pipe, pipe);
469
470 // Allocate tds on stack (with required alignment)
471 u8 tdsbuf[sizeof(struct ohci_td) * STACKOTDS + OHCI_TD_ALIGN - 1];
472 struct ohci_td *tds = (void*)ALIGN((u32)tdsbuf, OHCI_TD_ALIGN), *td = tds;
473 memset(tds, 0, sizeof(*tds) * STACKOTDS);
474
475 // Setup transfer descriptors
476 u16 maxpacket = pipe->pipe.maxpacket;
477 u32 toggle = 0, statuscmd = OHCI_BLF;
478 if (cmd) {
479 // Send setup pid on control transfers
480 td->hwINFO = TD_DP_SETUP | TD_T_DATA0 | TD_CC;
481 td->hwCBP = (u32)cmd;
482 td->hwNextTD = (u32)&td[1];
483 td->hwBE = (u32)cmd + USB_CONTROL_SETUP_SIZE - 1;
484 td++;
485 toggle = TD_T_DATA1;
486 statuscmd = OHCI_CLF;
487 }
488 u32 dest = (u32)data, dataend = dest + datasize;
489 while (dest < dataend) {
490 // Send data pids
491 if (td >= &tds[STACKOTDS]) {
492 warn_noalloc();
493 return -1;
494 }
495 int maxtransfer = 2*PAGE_SIZE - (dest & (PAGE_SIZE-1));
496 int transfer = dataend - dest;
497 if (transfer > maxtransfer)
498 transfer = ALIGN_DOWN(maxtransfer, maxpacket);
499 td->hwINFO = (dir ? TD_DP_IN : TD_DP_OUT) | toggle | TD_CC;
500 td->hwCBP = dest;
501 td->hwNextTD = (u32)&td[1];
502 td->hwBE = dest + transfer - 1;
503 td++;
504 dest += transfer;
505 }
506 if (cmd) {
507 // Send status pid on control transfers
508 if (td >= &tds[STACKOTDS]) {
509 warn_noalloc();
510 return -1;
511 }
512 td->hwINFO = (dir ? TD_DP_OUT : TD_DP_IN) | TD_T_DATA1 | TD_CC;
513 td->hwCBP = 0;
514 td->hwNextTD = (u32)&td[1];
515 td->hwBE = 0;
516 td++;
517 }
518
519 // Transfer data
520 pipe->ed.hwHeadP = (u32)tds | (pipe->ed.hwHeadP & ED_C);
521 pipe->ed.hwTailP = (u32)td;
522 barrier();
523 pipe->ed.hwINFO &= ~ED_SKIP;
524 writel(&pipe->regs->cmdstatus, statuscmd);
525
526 int ret = wait_ed(&pipe->ed, usb_xfer_time(p, datasize));
527 pipe->ed.hwINFO |= ED_SKIP;
528 if (ret)
529 ohci_waittick(pipe->regs);
530 return ret;
531 }
532
533 int
ohci_poll_intr(struct usb_pipe * p,void * data)534 ohci_poll_intr(struct usb_pipe *p, void *data)
535 {
536 ASSERT16();
537 if (! CONFIG_USB_OHCI)
538 return -1;
539
540 struct ohci_pipe *pipe = container_of(p, struct ohci_pipe, pipe);
541 struct ohci_td *tds = GET_LOWFLAT(pipe->tds);
542 struct ohci_td *head = (void*)(GET_LOWFLAT(pipe->ed.hwHeadP) & ~(ED_C|ED_H));
543 struct ohci_td *tail = (void*)GET_LOWFLAT(pipe->ed.hwTailP);
544 int count = GET_LOWFLAT(pipe->count);
545 int pos = (tail - tds + 1) % count;
546 struct ohci_td *next = &tds[pos];
547 if (head == next)
548 // No intrs found.
549 return -1;
550 // XXX - check for errors.
551
552 // Copy data.
553 int maxpacket = GET_LOWFLAT(pipe->pipe.maxpacket);
554 void *pipedata = GET_LOWFLAT((pipe->data));
555 void *intrdata = pipedata + maxpacket * pos;
556 memcpy_far(GET_SEG(SS), data, SEG_LOW, LOWFLAT2LOW(intrdata), maxpacket);
557
558 // Reenable this td.
559 SET_LOWFLAT(tail->hwINFO, TD_DP_IN | TD_T_TOGGLE | TD_CC);
560 intrdata = pipedata + maxpacket * (tail-tds);
561 SET_LOWFLAT(tail->hwCBP, (u32)intrdata);
562 SET_LOWFLAT(tail->hwNextTD, (u32)next);
563 SET_LOWFLAT(tail->hwBE, (u32)intrdata + maxpacket - 1);
564 barrier();
565 SET_LOWFLAT(pipe->ed.hwTailP, (u32)next);
566
567 return 0;
568 }
569