1 /* DO NOT EDIT THIS FILE 2 * Automatically generated by generate-def-headers.xsl 3 * DO NOT EDIT THIS FILE 4 */ 5 6 #ifndef __BFIN_DEF_ADSP_EDN_DUAL_CORE_extended__ 7 #define __BFIN_DEF_ADSP_EDN_DUAL_CORE_extended__ 8 9 #define PLL_CTL 0xFFC00000 10 #define PLL_DIV 0xFFC00004 11 #define VR_CTL 0xFFC00008 12 #define PLL_STAT 0xFFC0000C 13 #define PLL_LOCKCNT 0xFFC00010 14 #define CHIPID 0xFFC00014 15 #define SPI_CTL 0xFFC00500 16 #define SPI_FLG 0xFFC00504 17 #define SPI_STAT 0xFFC00508 18 #define SPI_TDBR 0xFFC0050C 19 #define SPI_RDBR 0xFFC00510 20 #define SPI_BAUD 0xFFC00514 21 #define SPI_SHADOW 0xFFC00518 22 #define WDOGA_CTL 0xFFC00200 23 #define WDOGA_CNT 0xFFC00204 24 #define WDOGA_STAT 0xFFC00208 25 #define WDOGB_CTL 0xFFC01200 26 #define WDOGB_CNT 0xFFC01204 27 #define WDOGB_STAT 0xFFC01208 28 #define DMA1_TC_PER 0xFFC01B0C /* Traffic Control Periods */ 29 #define DMA1_TC_CNT 0xFFC01B10 /* Traffic Control Current Counts */ 30 #define DMA1_0_CONFIG 0xFFC01C08 31 #define DMA1_0_NEXT_DESC_PTR 0xFFC01C00 32 #define DMA1_0_START_ADDR 0xFFC01C04 33 #define DMA1_0_X_COUNT 0xFFC01C10 34 #define DMA1_0_Y_COUNT 0xFFC01C18 35 #define DMA1_0_X_MODIFY 0xFFC01C14 36 #define DMA1_0_Y_MODIFY 0xFFC01C1C 37 #define DMA1_0_CURR_DESC_PTR 0xFFC01C20 38 #define DMA1_0_CURR_ADDR 0xFFC01C24 39 #define DMA1_0_CURR_X_COUNT 0xFFC01C30 40 #define DMA1_0_CURR_Y_COUNT 0xFFC01C38 41 #define DMA1_0_IRQ_STATUS 0xFFC01C28 42 #define DMA1_0_PERIPHERAL_MAP 0xFFC01C2C 43 #define DMA1_1_CONFIG 0xFFC01C48 44 #define DMA1_1_NEXT_DESC_PTR 0xFFC01C40 45 #define DMA1_1_START_ADDR 0xFFC01C44 46 #define DMA1_1_X_COUNT 0xFFC01C50 47 #define DMA1_1_Y_COUNT 0xFFC01C58 48 #define DMA1_1_X_MODIFY 0xFFC01C54 49 #define DMA1_1_Y_MODIFY 0xFFC01C5C 50 #define DMA1_1_CURR_DESC_PTR 0xFFC01C60 51 #define DMA1_1_CURR_ADDR 0xFFC01C64 52 #define DMA1_1_CURR_X_COUNT 0xFFC01C70 53 #define DMA1_1_CURR_Y_COUNT 0xFFC01C78 54 #define DMA1_1_IRQ_STATUS 0xFFC01C68 55 #define DMA1_1_PERIPHERAL_MAP 0xFFC01C6C 56 #define DMA1_2_CONFIG 0xFFC01C88 57 #define DMA1_2_NEXT_DESC_PTR 0xFFC01C80 58 #define DMA1_2_START_ADDR 0xFFC01C84 59 #define DMA1_2_X_COUNT 0xFFC01C90 60 #define DMA1_2_Y_COUNT 0xFFC01C98 61 #define DMA1_2_X_MODIFY 0xFFC01C94 62 #define DMA1_2_Y_MODIFY 0xFFC01C9C 63 #define DMA1_2_CURR_DESC_PTR 0xFFC01CA0 64 #define DMA1_2_CURR_ADDR 0xFFC01CA4 65 #define DMA1_2_CURR_X_COUNT 0xFFC01CB0 66 #define DMA1_2_CURR_Y_COUNT 0xFFC01CB8 67 #define DMA1_2_IRQ_STATUS 0xFFC01CA8 68 #define DMA1_2_PERIPHERAL_MAP 0xFFC01CAC 69 #define DMA1_3_CONFIG 0xFFC01CC8 70 #define DMA1_3_NEXT_DESC_PTR 0xFFC01CC0 71 #define DMA1_3_START_ADDR 0xFFC01CC4 72 #define DMA1_3_X_COUNT 0xFFC01CD0 73 #define DMA1_3_Y_COUNT 0xFFC01CD8 74 #define DMA1_3_X_MODIFY 0xFFC01CD4 75 #define DMA1_3_Y_MODIFY 0xFFC01CDC 76 #define DMA1_3_CURR_DESC_PTR 0xFFC01CE0 77 #define DMA1_3_CURR_ADDR 0xFFC01CE4 78 #define DMA1_3_CURR_X_COUNT 0xFFC01CF0 79 #define DMA1_3_CURR_Y_COUNT 0xFFC01CF8 80 #define DMA1_3_IRQ_STATUS 0xFFC01CE8 81 #define DMA1_3_PERIPHERAL_MAP 0xFFC01CEC 82 #define DMA1_4_CONFIG 0xFFC01D08 83 #define DMA1_4_NEXT_DESC_PTR 0xFFC01D00 84 #define DMA1_4_START_ADDR 0xFFC01D04 85 #define DMA1_4_X_COUNT 0xFFC01D10 86 #define DMA1_4_Y_COUNT 0xFFC01D18 87 #define DMA1_4_X_MODIFY 0xFFC01D14 88 #define DMA1_4_Y_MODIFY 0xFFC01D1C 89 #define DMA1_4_CURR_DESC_PTR 0xFFC01D20 90 #define DMA1_4_CURR_ADDR 0xFFC01D24 91 #define DMA1_4_CURR_X_COUNT 0xFFC01D30 92 #define DMA1_4_CURR_Y_COUNT 0xFFC01D38 93 #define DMA1_4_IRQ_STATUS 0xFFC01D28 94 #define DMA1_4_PERIPHERAL_MAP 0xFFC01D2C 95 #define DMA1_5_CONFIG 0xFFC01D48 96 #define DMA1_5_NEXT_DESC_PTR 0xFFC01D40 97 #define DMA1_5_START_ADDR 0xFFC01D44 98 #define DMA1_5_X_COUNT 0xFFC01D50 99 #define DMA1_5_Y_COUNT 0xFFC01D58 100 #define DMA1_5_X_MODIFY 0xFFC01D54 101 #define DMA1_5_Y_MODIFY 0xFFC01D5C 102 #define DMA1_5_CURR_DESC_PTR 0xFFC01D60 103 #define DMA1_5_CURR_ADDR 0xFFC01D64 104 #define DMA1_5_CURR_X_COUNT 0xFFC01D70 105 #define DMA1_5_CURR_Y_COUNT 0xFFC01D78 106 #define DMA1_5_IRQ_STATUS 0xFFC01D68 107 #define DMA1_5_PERIPHERAL_MAP 0xFFC01D6C 108 #define DMA1_6_CONFIG 0xFFC01D88 109 #define DMA1_6_NEXT_DESC_PTR 0xFFC01D80 110 #define DMA1_6_START_ADDR 0xFFC01D84 111 #define DMA1_6_X_COUNT 0xFFC01D90 112 #define DMA1_6_Y_COUNT 0xFFC01D98 113 #define DMA1_6_X_MODIFY 0xFFC01D94 114 #define DMA1_6_Y_MODIFY 0xFFC01D9C 115 #define DMA1_6_CURR_DESC_PTR 0xFFC01DA0 116 #define DMA1_6_CURR_ADDR 0xFFC01DA4 117 #define DMA1_6_CURR_X_COUNT 0xFFC01DB0 118 #define DMA1_6_CURR_Y_COUNT 0xFFC01DB8 119 #define DMA1_6_IRQ_STATUS 0xFFC01DA8 120 #define DMA1_6_PERIPHERAL_MAP 0xFFC01DAC 121 #define DMA1_7_CONFIG 0xFFC01DC8 122 #define DMA1_7_NEXT_DESC_PTR 0xFFC01DC0 123 #define DMA1_7_START_ADDR 0xFFC01DC4 124 #define DMA1_7_X_COUNT 0xFFC01DD0 125 #define DMA1_7_Y_COUNT 0xFFC01DD8 126 #define DMA1_7_X_MODIFY 0xFFC01DD4 127 #define DMA1_7_Y_MODIFY 0xFFC01DDC 128 #define DMA1_7_CURR_DESC_PTR 0xFFC01DE0 129 #define DMA1_7_CURR_ADDR 0xFFC01DE4 130 #define DMA1_7_CURR_X_COUNT 0xFFC01DF0 131 #define DMA1_7_CURR_Y_COUNT 0xFFC01DF8 132 #define DMA1_7_IRQ_STATUS 0xFFC01DE8 133 #define DMA1_7_PERIPHERAL_MAP 0xFFC01DEC 134 #define DMA1_8_CONFIG 0xFFC01E08 135 #define DMA1_8_NEXT_DESC_PTR 0xFFC01E00 136 #define DMA1_8_START_ADDR 0xFFC01E04 137 #define DMA1_8_X_COUNT 0xFFC01E10 138 #define DMA1_8_Y_COUNT 0xFFC01E18 139 #define DMA1_8_X_MODIFY 0xFFC01E14 140 #define DMA1_8_Y_MODIFY 0xFFC01E1C 141 #define DMA1_8_CURR_DESC_PTR 0xFFC01E20 142 #define DMA1_8_CURR_ADDR 0xFFC01E24 143 #define DMA1_8_CURR_X_COUNT 0xFFC01E30 144 #define DMA1_8_CURR_Y_COUNT 0xFFC01E38 145 #define DMA1_8_IRQ_STATUS 0xFFC01E28 146 #define DMA1_8_PERIPHERAL_MAP 0xFFC01E2C 147 #define DMA1_9_CONFIG 0xFFC01E48 148 #define DMA1_9_NEXT_DESC_PTR 0xFFC01E40 149 #define DMA1_9_START_ADDR 0xFFC01E44 150 #define DMA1_9_X_COUNT 0xFFC01E50 151 #define DMA1_9_Y_COUNT 0xFFC01E58 152 #define DMA1_9_X_MODIFY 0xFFC01E54 153 #define DMA1_9_Y_MODIFY 0xFFC01E5C 154 #define DMA1_9_CURR_DESC_PTR 0xFFC01E60 155 #define DMA1_9_CURR_ADDR 0xFFC01E64 156 #define DMA1_9_CURR_X_COUNT 0xFFC01E70 157 #define DMA1_9_CURR_Y_COUNT 0xFFC01E78 158 #define DMA1_9_IRQ_STATUS 0xFFC01E68 159 #define DMA1_9_PERIPHERAL_MAP 0xFFC01E6C 160 #define DMA1_10_CONFIG 0xFFC01E88 161 #define DMA1_10_NEXT_DESC_PTR 0xFFC01E80 162 #define DMA1_10_START_ADDR 0xFFC01E84 163 #define DMA1_10_X_COUNT 0xFFC01E90 164 #define DMA1_10_Y_COUNT 0xFFC01E98 165 #define DMA1_10_X_MODIFY 0xFFC01E94 166 #define DMA1_10_Y_MODIFY 0xFFC01E9C 167 #define DMA1_10_CURR_DESC_PTR 0xFFC01EA0 168 #define DMA1_10_CURR_ADDR 0xFFC01EA4 169 #define DMA1_10_CURR_X_COUNT 0xFFC01EB0 170 #define DMA1_10_CURR_Y_COUNT 0xFFC01EB8 171 #define DMA1_10_IRQ_STATUS 0xFFC01EA8 172 #define DMA1_10_PERIPHERAL_MAP 0xFFC01EAC 173 #define DMA1_11_CONFIG 0xFFC01EC8 174 #define DMA1_11_NEXT_DESC_PTR 0xFFC01EC0 175 #define DMA1_11_START_ADDR 0xFFC01EC4 176 #define DMA1_11_X_COUNT 0xFFC01ED0 177 #define DMA1_11_Y_COUNT 0xFFC01ED8 178 #define DMA1_11_X_MODIFY 0xFFC01ED4 179 #define DMA1_11_Y_MODIFY 0xFFC01EDC 180 #define DMA1_11_CURR_DESC_PTR 0xFFC01EE0 181 #define DMA1_11_CURR_ADDR 0xFFC01EE4 182 #define DMA1_11_CURR_X_COUNT 0xFFC01EF0 183 #define DMA1_11_CURR_Y_COUNT 0xFFC01EF8 184 #define DMA1_11_IRQ_STATUS 0xFFC01EE8 185 #define DMA1_11_PERIPHERAL_MAP 0xFFC01EEC 186 #define DMA2_TC_PER 0xFFC00B0C 187 #define DMA2_TC_CNT 0xFFC01B10 /* Traffic Control Current Counts */ 188 #define DMA2_0_CONFIG 0xFFC00C08 189 #define DMA2_0_NEXT_DESC_PTR 0xFFC00C00 190 #define DMA2_0_START_ADDR 0xFFC00C04 191 #define DMA2_0_X_COUNT 0xFFC00C10 192 #define DMA2_0_Y_COUNT 0xFFC00C18 193 #define DMA2_0_X_MODIFY 0xFFC00C14 194 #define DMA2_0_Y_MODIFY 0xFFC00C1C 195 #define DMA2_0_CURR_DESC_PTR 0xFFC00C20 196 #define DMA2_0_CURR_ADDR 0xFFC00C24 197 #define DMA2_0_CURR_X_COUNT 0xFFC00C30 198 #define DMA2_0_CURR_Y_COUNT 0xFFC00C38 199 #define DMA2_0_IRQ_STATUS 0xFFC00C28 200 #define DMA2_0_PERIPHERAL_MAP 0xFFC00C2C 201 #define DMA2_1_CONFIG 0xFFC00C48 202 #define DMA2_1_NEXT_DESC_PTR 0xFFC00C40 203 #define DMA2_1_START_ADDR 0xFFC00C44 204 #define DMA2_1_X_COUNT 0xFFC00C50 205 #define DMA2_1_Y_COUNT 0xFFC00C58 206 #define DMA2_1_X_MODIFY 0xFFC00C54 207 #define DMA2_1_Y_MODIFY 0xFFC00C5C 208 #define DMA2_1_CURR_DESC_PTR 0xFFC00C60 209 #define DMA2_1_CURR_ADDR 0xFFC00C64 210 #define DMA2_1_CURR_X_COUNT 0xFFC00C70 211 #define DMA2_1_CURR_Y_COUNT 0xFFC00C78 212 #define DMA2_1_IRQ_STATUS 0xFFC00C68 213 #define DMA2_1_PERIPHERAL_MAP 0xFFC00C6C 214 #define DMA2_2_CONFIG 0xFFC00C88 215 #define DMA2_2_NEXT_DESC_PTR 0xFFC00C80 216 #define DMA2_2_START_ADDR 0xFFC00C84 217 #define DMA2_2_X_COUNT 0xFFC00C90 218 #define DMA2_2_Y_COUNT 0xFFC00C98 219 #define DMA2_2_X_MODIFY 0xFFC00C94 220 #define DMA2_2_Y_MODIFY 0xFFC00C9C 221 #define DMA2_2_CURR_DESC_PTR 0xFFC00CA0 222 #define DMA2_2_CURR_ADDR 0xFFC00CA4 223 #define DMA2_2_CURR_X_COUNT 0xFFC00CB0 224 #define DMA2_2_CURR_Y_COUNT 0xFFC00CB8 225 #define DMA2_2_IRQ_STATUS 0xFFC00CA8 226 #define DMA2_2_PERIPHERAL_MAP 0xFFC00CAC 227 #define DMA2_3_CONFIG 0xFFC00CC8 228 #define DMA2_3_NEXT_DESC_PTR 0xFFC00CC0 229 #define DMA2_3_START_ADDR 0xFFC00CC4 230 #define DMA2_3_X_COUNT 0xFFC00CD0 231 #define DMA2_3_Y_COUNT 0xFFC00CD8 232 #define DMA2_3_X_MODIFY 0xFFC00CD4 233 #define DMA2_3_Y_MODIFY 0xFFC00CDC 234 #define DMA2_3_CURR_DESC_PTR 0xFFC00CE0 235 #define DMA2_3_CURR_ADDR 0xFFC00CE4 236 #define DMA2_3_CURR_X_COUNT 0xFFC00CF0 237 #define DMA2_3_CURR_Y_COUNT 0xFFC00CF8 238 #define DMA2_3_IRQ_STATUS 0xFFC00CE8 239 #define DMA2_3_PERIPHERAL_MAP 0xFFC00CEC 240 #define DMA2_4_CONFIG 0xFFC00D08 241 #define DMA2_4_NEXT_DESC_PTR 0xFFC00D00 242 #define DMA2_4_START_ADDR 0xFFC00D04 243 #define DMA2_4_X_COUNT 0xFFC00D10 244 #define DMA2_4_Y_COUNT 0xFFC00D18 245 #define DMA2_4_X_MODIFY 0xFFC00D14 246 #define DMA2_4_Y_MODIFY 0xFFC00D1C 247 #define DMA2_4_CURR_DESC_PTR 0xFFC00D20 248 #define DMA2_4_CURR_ADDR 0xFFC00D24 249 #define DMA2_4_CURR_X_COUNT 0xFFC00D30 250 #define DMA2_4_CURR_Y_COUNT 0xFFC00D38 251 #define DMA2_4_IRQ_STATUS 0xFFC00D28 252 #define DMA2_4_PERIPHERAL_MAP 0xFFC00D2C 253 #define DMA2_5_CONFIG 0xFFC00D48 254 #define DMA2_5_NEXT_DESC_PTR 0xFFC00D40 255 #define DMA2_5_START_ADDR 0xFFC00D44 256 #define DMA2_5_X_COUNT 0xFFC00D50 257 #define DMA2_5_Y_COUNT 0xFFC00D58 258 #define DMA2_5_X_MODIFY 0xFFC00D54 259 #define DMA2_5_Y_MODIFY 0xFFC00D5C 260 #define DMA2_5_CURR_DESC_PTR 0xFFC00D60 261 #define DMA2_5_CURR_ADDR 0xFFC00D64 262 #define DMA2_5_CURR_X_COUNT 0xFFC00D70 263 #define DMA2_5_CURR_Y_COUNT 0xFFC00D78 264 #define DMA2_5_IRQ_STATUS 0xFFC00D68 265 #define DMA2_5_PERIPHERAL_MAP 0xFFC00D6C 266 #define DMA2_6_CONFIG 0xFFC00D88 267 #define DMA2_6_NEXT_DESC_PTR 0xFFC00D80 268 #define DMA2_6_START_ADDR 0xFFC00D84 269 #define DMA2_6_X_COUNT 0xFFC00D90 270 #define DMA2_6_Y_COUNT 0xFFC00D98 271 #define DMA2_6_X_MODIFY 0xFFC00D94 272 #define DMA2_6_Y_MODIFY 0xFFC00D9C 273 #define DMA2_6_CURR_DESC_PTR 0xFFC00DA0 274 #define DMA2_6_CURR_ADDR 0xFFC00DA4 275 #define DMA2_6_CURR_X_COUNT 0xFFC00DB0 276 #define DMA2_6_CURR_Y_COUNT 0xFFC00DB8 277 #define DMA2_6_IRQ_STATUS 0xFFC00DA8 278 #define DMA2_6_PERIPHERAL_MAP 0xFFC00DAC 279 #define DMA2_7_CONFIG 0xFFC00DC8 280 #define DMA2_7_NEXT_DESC_PTR 0xFFC00DC0 281 #define DMA2_7_START_ADDR 0xFFC00DC4 282 #define DMA2_7_X_COUNT 0xFFC00DD0 283 #define DMA2_7_Y_COUNT 0xFFC00DD8 284 #define DMA2_7_X_MODIFY 0xFFC00DD4 285 #define DMA2_7_Y_MODIFY 0xFFC00DDC 286 #define DMA2_7_CURR_DESC_PTR 0xFFC00DE0 287 #define DMA2_7_CURR_ADDR 0xFFC00DE4 288 #define DMA2_7_CURR_X_COUNT 0xFFC00DF0 289 #define DMA2_7_CURR_Y_COUNT 0xFFC00DF8 290 #define DMA2_7_IRQ_STATUS 0xFFC00DE8 291 #define DMA2_7_PERIPHERAL_MAP 0xFFC00DEC 292 #define DMA2_8_CONFIG 0xFFC00E08 293 #define DMA2_8_NEXT_DESC_PTR 0xFFC00E00 294 #define DMA2_8_START_ADDR 0xFFC00E04 295 #define DMA2_8_X_COUNT 0xFFC00E10 296 #define DMA2_8_Y_COUNT 0xFFC00E18 297 #define DMA2_8_X_MODIFY 0xFFC00E14 298 #define DMA2_8_Y_MODIFY 0xFFC00E1C 299 #define DMA2_8_CURR_DESC_PTR 0xFFC00E20 300 #define DMA2_8_CURR_ADDR 0xFFC00E24 301 #define DMA2_8_CURR_X_COUNT 0xFFC00E30 302 #define DMA2_8_CURR_Y_COUNT 0xFFC00E38 303 #define DMA2_8_IRQ_STATUS 0xFFC00E28 304 #define DMA2_8_PERIPHERAL_MAP 0xFFC00E2C 305 #define DMA2_9_CONFIG 0xFFC00E48 306 #define DMA2_9_NEXT_DESC_PTR 0xFFC00E40 307 #define DMA2_9_START_ADDR 0xFFC00E44 308 #define DMA2_9_X_COUNT 0xFFC00E50 309 #define DMA2_9_Y_COUNT 0xFFC00E58 310 #define DMA2_9_X_MODIFY 0xFFC00E54 311 #define DMA2_9_Y_MODIFY 0xFFC00E5C 312 #define DMA2_9_CURR_DESC_PTR 0xFFC00E60 313 #define DMA2_9_CURR_ADDR 0xFFC00E64 314 #define DMA2_9_CURR_X_COUNT 0xFFC00E70 315 #define DMA2_9_CURR_Y_COUNT 0xFFC00E78 316 #define DMA2_9_IRQ_STATUS 0xFFC00E68 317 #define DMA2_9_PERIPHERAL_MAP 0xFFC00E6C 318 #define DMA2_10_CONFIG 0xFFC00E88 319 #define DMA2_10_NEXT_DESC_PTR 0xFFC00E80 320 #define DMA2_10_START_ADDR 0xFFC00E84 321 #define DMA2_10_X_COUNT 0xFFC00E90 322 #define DMA2_10_Y_COUNT 0xFFC00E98 323 #define DMA2_10_X_MODIFY 0xFFC00E94 324 #define DMA2_10_Y_MODIFY 0xFFC00E9C 325 #define DMA2_10_CURR_DESC_PTR 0xFFC00EA0 326 #define DMA2_10_CURR_ADDR 0xFFC00EA4 327 #define DMA2_10_CURR_X_COUNT 0xFFC00EB0 328 #define DMA2_10_CURR_Y_COUNT 0xFFC00EB8 329 #define DMA2_10_IRQ_STATUS 0xFFC00EA8 330 #define DMA2_10_PERIPHERAL_MAP 0xFFC00EAC 331 #define DMA2_11_CONFIG 0xFFC00EC8 332 #define DMA2_11_NEXT_DESC_PTR 0xFFC00EC0 333 #define DMA2_11_START_ADDR 0xFFC00EC4 334 #define DMA2_11_X_COUNT 0xFFC00ED0 335 #define DMA2_11_Y_COUNT 0xFFC00ED8 336 #define DMA2_11_X_MODIFY 0xFFC00ED4 337 #define DMA2_11_Y_MODIFY 0xFFC00EDC 338 #define DMA2_11_CURR_DESC_PTR 0xFFC00EE0 339 #define DMA2_11_CURR_ADDR 0xFFC00EE4 340 #define DMA2_11_CURR_X_COUNT 0xFFC00EF0 341 #define DMA2_11_CURR_Y_COUNT 0xFFC00EF8 342 #define DMA2_11_IRQ_STATUS 0xFFC00EE8 343 #define DMA2_11_PERIPHERAL_MAP 0xFFC00EEC 344 #define IMDMA_S0_CONFIG 0xFFC01848 345 #define IMDMA_S0_NEXT_DESC_PTR 0xFFC01840 346 #define IMDMA_S0_START_ADDR 0xFFC01844 347 #define IMDMA_S0_X_COUNT 0xFFC01850 348 #define IMDMA_S0_Y_COUNT 0xFFC01858 349 #define IMDMA_S0_X_MODIFY 0xFFC01854 350 #define IMDMA_S0_Y_MODIFY 0xFFC0185C 351 #define IMDMA_S0_CURR_DESC_PTR 0xFFC01860 352 #define IMDMA_S0_CURR_ADDR 0xFFC01864 353 #define IMDMA_S0_CURR_X_COUNT 0xFFC01870 354 #define IMDMA_S0_CURR_Y_COUNT 0xFFC01878 355 #define IMDMA_S0_IRQ_STATUS 0xFFC01868 356 #define IMDMA_D0_CONFIG 0xFFC01808 357 #define IMDMA_D0_NEXT_DESC_PTR 0xFFC01800 358 #define IMDMA_D0_START_ADDR 0xFFC01804 359 #define IMDMA_D0_X_COUNT 0xFFC01810 360 #define IMDMA_D0_Y_COUNT 0xFFC01818 361 #define IMDMA_D0_X_MODIFY 0xFFC01814 362 #define IMDMA_D0_Y_MODIFY 0xFFC0181C 363 #define IMDMA_D0_CURR_DESC_PTR 0xFFC01820 364 #define IMDMA_D0_CURR_ADDR 0xFFC01824 365 #define IMDMA_D0_CURR_X_COUNT 0xFFC01830 366 #define IMDMA_D0_CURR_Y_COUNT 0xFFC01838 367 #define IMDMA_D0_IRQ_STATUS 0xFFC01828 368 #define IMDMA_S1_CONFIG 0xFFC018C8 369 #define IMDMA_S1_NEXT_DESC_PTR 0xFFC018C0 370 #define IMDMA_S1_START_ADDR 0xFFC018C4 371 #define IMDMA_S1_X_COUNT 0xFFC018D0 372 #define IMDMA_S1_Y_COUNT 0xFFC018D8 373 #define IMDMA_S1_X_MODIFY 0xFFC018D4 374 #define IMDMA_S1_Y_MODIFY 0xFFC018DC 375 #define IMDMA_S1_CURR_DESC_PTR 0xFFC018E0 376 #define IMDMA_S1_CURR_ADDR 0xFFC018E4 377 #define IMDMA_S1_CURR_X_COUNT 0xFFC018F0 378 #define IMDMA_S1_CURR_Y_COUNT 0xFFC018F8 379 #define IMDMA_S1_IRQ_STATUS 0xFFC018E8 380 #define IMDMA_D1_CONFIG 0xFFC01888 381 #define IMDMA_D1_NEXT_DESC_PTR 0xFFC01880 382 #define IMDMA_D1_START_ADDR 0xFFC01884 383 #define IMDMA_D1_X_COUNT 0xFFC01890 384 #define IMDMA_D1_Y_COUNT 0xFFC01898 385 #define IMDMA_D1_X_MODIFY 0xFFC01894 386 #define IMDMA_D1_Y_MODIFY 0xFFC0189C 387 #define IMDMA_D1_CURR_DESC_PTR 0xFFC018A0 388 #define IMDMA_D1_CURR_ADDR 0xFFC018A4 389 #define IMDMA_D1_CURR_X_COUNT 0xFFC018B0 390 #define IMDMA_D1_CURR_Y_COUNT 0xFFC018B8 391 #define IMDMA_D1_IRQ_STATUS 0xFFC018A8 392 #define MDMA1_S0_CONFIG 0xFFC01F48 393 #define MDMA1_S0_NEXT_DESC_PTR 0xFFC01F40 394 #define MDMA1_S0_START_ADDR 0xFFC01F44 395 #define MDMA1_S0_X_COUNT 0xFFC01F50 396 #define MDMA1_S0_Y_COUNT 0xFFC01F58 397 #define MDMA1_S0_X_MODIFY 0xFFC01F54 398 #define MDMA1_S0_Y_MODIFY 0xFFC01F5C 399 #define MDMA1_S0_CURR_DESC_PTR 0xFFC01F60 400 #define MDMA1_S0_CURR_ADDR 0xFFC01F64 401 #define MDMA1_S0_CURR_X_COUNT 0xFFC01F70 402 #define MDMA1_S0_CURR_Y_COUNT 0xFFC01F78 403 #define MDMA1_S0_IRQ_STATUS 0xFFC01F68 404 #define MDMA1_S0_PERIPHERAL_MAP 0xFFC01F6C 405 #define MDMA1_D0_CONFIG 0xFFC01F08 406 #define MDMA1_D0_NEXT_DESC_PTR 0xFFC01F00 407 #define MDMA1_D0_START_ADDR 0xFFC01F04 408 #define MDMA1_D0_X_COUNT 0xFFC01F10 409 #define MDMA1_D0_Y_COUNT 0xFFC01F18 410 #define MDMA1_D0_X_MODIFY 0xFFC01F14 411 #define MDMA1_D0_Y_MODIFY 0xFFC01F1C 412 #define MDMA1_D0_CURR_DESC_PTR 0xFFC01F20 413 #define MDMA1_D0_CURR_ADDR 0xFFC01F24 414 #define MDMA1_D0_CURR_X_COUNT 0xFFC01F30 415 #define MDMA1_D0_CURR_Y_COUNT 0xFFC01F38 416 #define MDMA1_D0_IRQ_STATUS 0xFFC01F28 417 #define MDMA1_D0_PERIPHERAL_MAP 0xFFC01F2C 418 #define MDMA1_S1_CONFIG 0xFFC01FC8 419 #define MDMA1_S1_NEXT_DESC_PTR 0xFFC01FC0 420 #define MDMA1_S1_START_ADDR 0xFFC01FC4 421 #define MDMA1_S1_X_COUNT 0xFFC01FD0 422 #define MDMA1_S1_Y_COUNT 0xFFC01FD8 423 #define MDMA1_S1_X_MODIFY 0xFFC01FD4 424 #define MDMA1_S1_Y_MODIFY 0xFFC01FDC 425 #define MDMA1_S1_CURR_DESC_PTR 0xFFC01FE0 426 #define MDMA1_S1_CURR_ADDR 0xFFC01FE4 427 #define MDMA1_S1_CURR_X_COUNT 0xFFC01FF0 428 #define MDMA1_S1_CURR_Y_COUNT 0xFFC01FF8 429 #define MDMA1_S1_IRQ_STATUS 0xFFC01FE8 430 #define MDMA1_S1_PERIPHERAL_MAP 0xFFC01FEC 431 #define MDMA1_D1_CONFIG 0xFFC01F88 432 #define MDMA1_D1_NEXT_DESC_PTR 0xFFC01F80 433 #define MDMA1_D1_START_ADDR 0xFFC01F84 434 #define MDMA1_D1_X_COUNT 0xFFC01F90 435 #define MDMA1_D1_Y_COUNT 0xFFC01F98 436 #define MDMA1_D1_X_MODIFY 0xFFC01F94 437 #define MDMA1_D1_Y_MODIFY 0xFFC01F9C 438 #define MDMA1_D1_CURR_DESC_PTR 0xFFC01FA0 439 #define MDMA1_D1_CURR_ADDR 0xFFC01FA4 440 #define MDMA1_D1_CURR_X_COUNT 0xFFC01FB0 441 #define MDMA1_D1_CURR_Y_COUNT 0xFFC01FB8 442 #define MDMA1_D1_IRQ_STATUS 0xFFC01FA8 443 #define MDMA1_D1_PERIPHERAL_MAP 0xFFC01FAC 444 #define MDMA2_S0_CONFIG 0xFFC00F48 445 #define MDMA2_S0_NEXT_DESC_PTR 0xFFC00F40 446 #define MDMA2_S0_START_ADDR 0xFFC00F44 447 #define MDMA2_S0_X_COUNT 0xFFC00F50 448 #define MDMA2_S0_Y_COUNT 0xFFC00F58 449 #define MDMA2_S0_X_MODIFY 0xFFC00F54 450 #define MDMA2_S0_Y_MODIFY 0xFFC00F5C 451 #define MDMA2_S0_CURR_DESC_PTR 0xFFC00F60 452 #define MDMA2_S0_CURR_ADDR 0xFFC00F64 453 #define MDMA2_S0_CURR_X_COUNT 0xFFC00F70 454 #define MDMA2_S0_CURR_Y_COUNT 0xFFC00F78 455 #define MDMA2_S0_IRQ_STATUS 0xFFC00F68 456 #define MDMA2_S0_PERIPHERAL_MAP 0xFFC00F6C 457 #define MDMA2_D0_CONFIG 0xFFC00F08 458 #define MDMA2_D0_NEXT_DESC_PTR 0xFFC00F00 459 #define MDMA2_D0_START_ADDR 0xFFC00F04 460 #define MDMA2_D0_X_COUNT 0xFFC00F10 461 #define MDMA2_D0_Y_COUNT 0xFFC00F18 462 #define MDMA2_D0_X_MODIFY 0xFFC00F14 463 #define MDMA2_D0_Y_MODIFY 0xFFC00F1C 464 #define MDMA2_D0_CURR_DESC_PTR 0xFFC00F20 465 #define MDMA2_D0_CURR_ADDR 0xFFC00F24 466 #define MDMA2_D0_CURR_X_COUNT 0xFFC00F30 467 #define MDMA2_D0_CURR_Y_COUNT 0xFFC00F38 468 #define MDMA2_D0_IRQ_STATUS 0xFFC00F28 469 #define MDMA2_D0_PERIPHERAL_MAP 0xFFC00F2C 470 #define MDMA2_S1_CONFIG 0xFFC00FC8 471 #define MDMA2_S1_NEXT_DESC_PTR 0xFFC00FC0 472 #define MDMA2_S1_START_ADDR 0xFFC00FC4 473 #define MDMA2_S1_X_COUNT 0xFFC00FD0 474 #define MDMA2_S1_Y_COUNT 0xFFC00FD8 475 #define MDMA2_S1_X_MODIFY 0xFFC00FD4 476 #define MDMA2_S1_Y_MODIFY 0xFFC00FDC 477 #define MDMA2_S1_CURR_DESC_PTR 0xFFC00FE0 478 #define MDMA2_S1_CURR_ADDR 0xFFC00FE4 479 #define MDMA2_S1_CURR_X_COUNT 0xFFC00FF0 480 #define MDMA2_S1_CURR_Y_COUNT 0xFFC00FF8 481 #define MDMA2_S1_IRQ_STATUS 0xFFC00FE8 482 #define MDMA2_S1_PERIPHERAL_MAP 0xFFC00FEC 483 #define MDMA2_D1_CONFIG 0xFFC00F88 484 #define MDMA2_D1_NEXT_DESC_PTR 0xFFC00F80 485 #define MDMA2_D1_START_ADDR 0xFFC00F84 486 #define MDMA2_D1_X_COUNT 0xFFC00F90 487 #define MDMA2_D1_Y_COUNT 0xFFC00F98 488 #define MDMA2_D1_X_MODIFY 0xFFC00F94 489 #define MDMA2_D1_Y_MODIFY 0xFFC00F9C 490 #define MDMA2_D1_CURR_DESC_PTR 0xFFC00FA0 491 #define MDMA2_D1_CURR_ADDR 0xFFC00FA4 492 #define MDMA2_D1_CURR_X_COUNT 0xFFC00FB0 493 #define MDMA2_D1_CURR_Y_COUNT 0xFFC00FB8 494 #define MDMA2_D1_IRQ_STATUS 0xFFC00FA8 495 #define MDMA2_D1_PERIPHERAL_MAP 0xFFC00FAC 496 #define TIMER0_CONFIG 0xFFC00600 497 #define TIMER0_COUNTER 0xFFC00604 498 #define TIMER0_PERIOD 0xFFC00608 499 #define TIMER0_WIDTH 0xFFC0060C 500 #define TIMER1_CONFIG 0xFFC00610 501 #define TIMER1_COUNTER 0xFFC00614 502 #define TIMER1_PERIOD 0xFFC00618 503 #define TIMER1_WIDTH 0xFFC0061C 504 #define TIMER2_CONFIG 0xFFC00620 505 #define TIMER2_COUNTER 0xFFC00624 506 #define TIMER2_PERIOD 0xFFC00628 507 #define TIMER2_WIDTH 0xFFC0062C 508 #define TIMER3_CONFIG 0xFFC00630 509 #define TIMER3_COUNTER 0xFFC00634 510 #define TIMER3_PERIOD 0xFFC00638 511 #define TIMER3_WIDTH 0xFFC0063C 512 #define TIMER4_CONFIG 0xFFC00640 513 #define TIMER4_COUNTER 0xFFC00644 514 #define TIMER4_PERIOD 0xFFC00648 515 #define TIMER4_WIDTH 0xFFC0064C 516 #define TIMER5_CONFIG 0xFFC00650 517 #define TIMER5_COUNTER 0xFFC00654 518 #define TIMER5_PERIOD 0xFFC00658 519 #define TIMER5_WIDTH 0xFFC0065C 520 #define TIMER6_CONFIG 0xFFC00660 521 #define TIMER6_COUNTER 0xFFC00664 522 #define TIMER6_PERIOD 0xFFC00668 523 #define TIMER6_WIDTH 0xFFC0066C 524 #define TIMER7_CONFIG 0xFFC00670 525 #define TIMER7_COUNTER 0xFFC00674 526 #define TIMER7_PERIOD 0xFFC00678 527 #define TIMER7_WIDTH 0xFFC0067C 528 #define TIMER8_CONFIG 0xFFC01600 529 #define TIMER8_COUNTER 0xFFC01604 530 #define TIMER8_PERIOD 0xFFC01608 531 #define TIMER8_WIDTH 0xFFC0160C 532 #define TIMER9_CONFIG 0xFFC01610 533 #define TIMER9_COUNTER 0xFFC01614 534 #define TIMER9_PERIOD 0xFFC01618 535 #define TIMER9_WIDTH 0xFFC0161C 536 #define TIMER10_CONFIG 0xFFC01620 537 #define TIMER10_COUNTER 0xFFC01624 538 #define TIMER10_PERIOD 0xFFC01628 539 #define TIMER10_WIDTH 0xFFC0162C 540 #define TIMER11_CONFIG 0xFFC01630 541 #define TIMER11_COUNTER 0xFFC01634 542 #define TIMER11_PERIOD 0xFFC01638 543 #define TIMER11_WIDTH 0xFFC0163C 544 #define TMRS4_ENABLE 0xFFC01640 545 #define TMRS4_DISABLE 0xFFC01644 546 #define TMRS4_STATUS 0xFFC01648 547 #define TMRS8_ENABLE 0xFFC00680 548 #define TMRS8_DISABLE 0xFFC00684 549 #define TMRS8_STATUS 0xFFC00688 550 #define FIO0_FLAG_D 0xFFC00700 551 #define FIO0_FLAG_C 0xFFC00704 552 #define FIO0_FLAG_S 0xFFC00708 553 #define FIO0_FLAG_T 0xFFC0070C 554 #define FIO0_MASKA_D 0xFFC00710 555 #define FIO0_MASKA_C 0xFFC00714 556 #define FIO0_MASKA_S 0xFFC00718 557 #define FIO0_MASKA_T 0xFFC0071C 558 #define FIO0_MASKB_D 0xFFC00720 559 #define FIO0_MASKB_C 0xFFC00724 560 #define FIO0_MASKB_S 0xFFC00728 561 #define FIO0_MASKB_T 0xFFC0072C 562 #define FIO0_DIR 0xFFC00730 563 #define FIO0_POLAR 0xFFC00734 564 #define FIO0_EDGE 0xFFC00738 565 #define FIO0_BOTH 0xFFC0073C 566 #define FIO0_INEN 0xFFC00740 567 #define FIO1_FLAG_D 0xFFC01500 568 #define FIO1_FLAG_C 0xFFC01504 569 #define FIO1_FLAG_S 0xFFC01508 570 #define FIO1_FLAG_T 0xFFC0150C 571 #define FIO1_MASKA_D 0xFFC01510 572 #define FIO1_MASKA_C 0xFFC01514 573 #define FIO1_MASKA_S 0xFFC01518 574 #define FIO1_MASKA_T 0xFFC0151C 575 #define FIO1_MASKB_D 0xFFC01520 576 #define FIO1_MASKB_C 0xFFC01524 577 #define FIO1_MASKB_S 0xFFC01528 578 #define FIO1_MASKB_T 0xFFC0152C 579 #define FIO1_DIR 0xFFC01530 580 #define FIO1_POLAR 0xFFC01534 581 #define FIO1_EDGE 0xFFC01538 582 #define FIO1_BOTH 0xFFC0153C 583 #define FIO1_INEN 0xFFC01540 584 #define FIO2_FLAG_D 0xFFC01700 585 #define FIO2_FLAG_C 0xFFC01704 586 #define FIO2_FLAG_S 0xFFC01708 587 #define FIO2_FLAG_T 0xFFC0170C 588 #define FIO2_MASKA_D 0xFFC01710 589 #define FIO2_MASKA_C 0xFFC01714 590 #define FIO2_MASKA_S 0xFFC01718 591 #define FIO2_MASKA_T 0xFFC0171C 592 #define FIO2_MASKB_D 0xFFC01720 593 #define FIO2_MASKB_C 0xFFC01724 594 #define FIO2_MASKB_S 0xFFC01728 595 #define FIO2_MASKB_T 0xFFC0172C 596 #define FIO2_DIR 0xFFC01730 597 #define FIO2_POLAR 0xFFC01734 598 #define FIO2_EDGE 0xFFC01738 599 #define FIO2_BOTH 0xFFC0173C 600 #define FIO2_INEN 0xFFC01740 601 #define SPORT0_TCR1 0xFFC00800 602 #define SPORT0_TCR2 0xFFC00804 603 #define SPORT0_TCLKDIV 0xFFC00808 604 #define SPORT0_TFSDIV 0xFFC0080C 605 #define SPORT0_TX 0xFFC00810 606 #define SPORT0_RX 0xFFC00818 607 #define SPORT0_RCR1 0xFFC00820 608 #define SPORT0_RCR2 0xFFC00824 609 #define SPORT0_RCLKDIV 0xFFC00828 610 #define SPORT0_RFSDIV 0xFFC0082C 611 #define SPORT0_STAT 0xFFC00830 612 #define SPORT0_CHNL 0xFFC00834 613 #define SPORT0_MCMC1 0xFFC00838 614 #define SPORT0_MCMC2 0xFFC0083C 615 #define SPORT0_MTCS0 0xFFC00840 616 #define SPORT0_MTCS1 0xFFC00844 617 #define SPORT0_MTCS2 0xFFC00848 618 #define SPORT0_MTCS3 0xFFC0084C 619 #define SPORT0_MRCS0 0xFFC00850 620 #define SPORT0_MRCS1 0xFFC00854 621 #define SPORT0_MRCS2 0xFFC00858 622 #define SPORT0_MRCS3 0xFFC0085C 623 #define SPORT1_TCR1 0xFFC00900 624 #define SPORT1_TCR2 0xFFC00904 625 #define SPORT1_TCLKDIV 0xFFC00908 626 #define SPORT1_TFSDIV 0xFFC0090C 627 #define SPORT1_TX 0xFFC00910 628 #define SPORT1_RX 0xFFC00918 629 #define SPORT1_RCR1 0xFFC00920 630 #define SPORT1_RCR2 0xFFC00924 631 #define SPORT1_RCLKDIV 0xFFC00928 632 #define SPORT1_RFSDIV 0xFFC0092C 633 #define SPORT1_STAT 0xFFC00930 634 #define SPORT1_CHNL 0xFFC00934 635 #define SPORT1_MCMC1 0xFFC00938 636 #define SPORT1_MCMC2 0xFFC0093C 637 #define SPORT1_MTCS0 0xFFC00940 638 #define SPORT1_MTCS1 0xFFC00944 639 #define SPORT1_MTCS2 0xFFC00948 640 #define SPORT1_MTCS3 0xFFC0094C 641 #define SPORT1_MRCS0 0xFFC00950 642 #define SPORT1_MRCS1 0xFFC00954 643 #define SPORT1_MRCS2 0xFFC00958 644 #define SPORT1_MRCS3 0xFFC0095C 645 #define EVT0 0xFFE02000 646 #define EVT1 0xFFE02004 647 #define EVT2 0xFFE02008 648 #define EVT3 0xFFE0200C 649 #define EVT4 0xFFE02010 650 #define EVT5 0xFFE02014 651 #define EVT6 0xFFE02018 652 #define EVT7 0xFFE0201C 653 #define EVT8 0xFFE02020 654 #define EVT9 0xFFE02024 655 #define EVT10 0xFFE02028 656 #define EVT11 0xFFE0202C 657 #define EVT12 0xFFE02030 658 #define EVT13 0xFFE02034 659 #define EVT14 0xFFE02038 660 #define EVT15 0xFFE0203C 661 #define ILAT 0xFFE0210C /* Interrupt Latch Register */ 662 #define IMASK 0xFFE02104 /* Interrupt Mask Register */ 663 #define IPEND 0xFFE02108 /* Interrupt Pending Register */ 664 #define IPRIO 0xFFE02110 /* Interrupt Priority Register */ 665 #define TCNTL 0xFFE03000 666 #define TPERIOD 0xFFE03004 667 #define TSCALE 0xFFE03008 668 #define TCOUNT 0xFFE0300C 669 670 #endif /* __BFIN_DEF_ADSP_EDN_DUAL_CORE_extended__ */ 671