1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2010-2011 Freescale Semiconductor, Inc.
4 */
5
6 #include <common.h>
7 #include <asm/mmu.h>
8 #include <asm/immap_85xx.h>
9 #include <asm/processor.h>
10 #include <fsl_ddr_sdram.h>
11 #include <fsl_ddr_dimm_params.h>
12 #include <asm/io.h>
13 #include <asm/fsl_law.h>
14
15 DECLARE_GLOBAL_DATA_PTR;
16
17 #ifndef CONFIG_SYS_DDR_RAW_TIMING
18 #define CONFIG_SYS_DRAM_SIZE 1024
19
20 fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
21 .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
22 .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
23 .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
24 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
25 .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
26 .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
27 .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
28 .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
29 .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
30 .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
31 .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
32 .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
33 .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
34 .ddr_data_init = CONFIG_MEM_INIT_VALUE,
35 .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
36 .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
37 .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
38 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
39 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
40 .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
41 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_800,
42 .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
43 .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
44 .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
45 };
46
47 fsl_ddr_cfg_regs_t ddr_cfg_regs_667 = {
48 .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
49 .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
50 .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
51 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_667,
52 .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_667,
53 .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_667,
54 .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_667,
55 .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
56 .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
57 .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_667,
58 .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_667,
59 .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
60 .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_667,
61 .ddr_data_init = CONFIG_MEM_INIT_VALUE,
62 .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_667,
63 .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
64 .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
65 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
66 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
67 .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
68 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_667,
69 .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
70 .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
71 .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
72 };
73
74 fixed_ddr_parm_t fixed_ddr_parm_0[] = {
75 {750, 850, &ddr_cfg_regs_800},
76 {607, 749, &ddr_cfg_regs_667},
77 {0, 0, NULL}
78 };
79
get_sdram_size(void)80 unsigned long get_sdram_size(void)
81 {
82 struct cpu_type *cpu;
83 phys_size_t ddr_size;
84
85 cpu = gd->arch.cpu;
86 /* P1014 and it's derivatives support max 16it DDR width */
87 if (cpu->soc_ver == SVR_P1014)
88 ddr_size = (CONFIG_SYS_DRAM_SIZE / 2);
89 else
90 ddr_size = CONFIG_SYS_DRAM_SIZE;
91
92 return ddr_size;
93 }
94
95 /*
96 * Fixed sdram init -- doesn't use serial presence detect.
97 */
fixed_sdram(void)98 phys_size_t fixed_sdram(void)
99 {
100 int i;
101 char buf[32];
102 fsl_ddr_cfg_regs_t ddr_cfg_regs;
103 phys_size_t ddr_size;
104 ulong ddr_freq, ddr_freq_mhz;
105 struct cpu_type *cpu;
106
107 #if defined(CONFIG_SYS_RAMBOOT)
108 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
109 #endif
110
111 ddr_freq = get_ddr_freq(0);
112 ddr_freq_mhz = ddr_freq / 1000000;
113
114 printf("Configuring DDR for %s MT/s data rate\n",
115 strmhz(buf, ddr_freq));
116
117 for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {
118 if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) &&
119 (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) {
120 memcpy(&ddr_cfg_regs, fixed_ddr_parm_0[i].ddr_settings,
121 sizeof(ddr_cfg_regs));
122 break;
123 }
124 }
125
126 if (fixed_ddr_parm_0[i].max_freq == 0)
127 panic("Unsupported DDR data rate %s MT/s data rate\n",
128 strmhz(buf, ddr_freq));
129
130 cpu = gd->arch.cpu;
131 /* P1014 and it's derivatives support max 16bit DDR width */
132 if (cpu->soc_ver == SVR_P1014) {
133 ddr_cfg_regs.ddr_sdram_cfg &= ~SDRAM_CFG_DBW_MASK;
134 ddr_cfg_regs.ddr_sdram_cfg |= SDRAM_CFG_16_BE;
135 /* divide SA and EA by two and then mask the rest so we don't
136 * write to reserved fields */
137 ddr_cfg_regs.cs[0].bnds = (CONFIG_SYS_DDR_CS0_BNDS >> 1) & 0x0fff0fff;
138 }
139
140 ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
141 fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
142
143 if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, ddr_size,
144 LAW_TRGT_IF_DDR_1) < 0) {
145 printf("ERROR setting Local Access Windows for DDR\n");
146 return 0;
147 }
148
149 return ddr_size;
150 }
151
152 #else /* CONFIG_SYS_DDR_RAW_TIMING */
153 /*
154 * Samsung K4B2G0846C-HCF8
155 * The following timing are for "downshift"
156 * i.e. to use CL9 part as CL7
157 * otherwise, tAA, tRCD, tRP will be 13500ps
158 * and tRC will be 49500ps
159 */
160 dimm_params_t ddr_raw_timing = {
161 .n_ranks = 1,
162 .rank_density = 1073741824u,
163 .capacity = 1073741824u,
164 .primary_sdram_width = 32,
165 .ec_sdram_width = 0,
166 .registered_dimm = 0,
167 .mirrored_dimm = 0,
168 .n_row_addr = 15,
169 .n_col_addr = 10,
170 .n_banks_per_sdram_device = 8,
171 .edc_config = 0,
172 .burst_lengths_bitmask = 0x0c,
173
174 .tckmin_x_ps = 1875,
175 .caslat_x = 0x1e << 4, /* 5,6,7,8 */
176 .taa_ps = 13125,
177 .twr_ps = 15000,
178 .trcd_ps = 13125,
179 .trrd_ps = 7500,
180 .trp_ps = 13125,
181 .tras_ps = 37500,
182 .trc_ps = 50625,
183 .trfc_ps = 160000,
184 .twtr_ps = 7500,
185 .trtp_ps = 7500,
186 .refresh_rate_ps = 7800000,
187 .tfaw_ps = 37500,
188 };
189
fsl_ddr_get_dimm_params(dimm_params_t * pdimm,unsigned int controller_number,unsigned int dimm_number)190 int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
191 unsigned int controller_number,
192 unsigned int dimm_number)
193 {
194 const char dimm_model[] = "Fixed DDR on board";
195
196 if ((controller_number == 0) && (dimm_number == 0)) {
197 memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
198 memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
199 memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
200 }
201
202 return 0;
203 }
204
fsl_ddr_board_options(memctl_options_t * popts,dimm_params_t * pdimm,unsigned int ctrl_num)205 void fsl_ddr_board_options(memctl_options_t *popts,
206 dimm_params_t *pdimm,
207 unsigned int ctrl_num)
208 {
209 struct cpu_type *cpu;
210 int i;
211 popts->clk_adjust = 6;
212 popts->cpo_override = 0x1f;
213 popts->write_data_delay = 2;
214 popts->half_strength_driver_enable = 1;
215 /* Write leveling override */
216 popts->wrlvl_en = 1;
217 popts->wrlvl_override = 1;
218 popts->wrlvl_sample = 0xf;
219 popts->wrlvl_start = 0x8;
220 popts->trwt_override = 1;
221 popts->trwt = 0;
222
223 cpu = gd->arch.cpu;
224 /* P1014 and it's derivatives support max 16it DDR width */
225 if (cpu->soc_ver == SVR_P1014)
226 popts->data_bus_width = DDR_DATA_BUS_WIDTH_16;
227
228 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
229 popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
230 popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
231 }
232 }
233
234 #endif /* CONFIG_SYS_DDR_RAW_TIMING */
235