1 /*===-- X86DisassemblerDecoderCommon.h - Disassembler decoder -----*- C -*-===* 2 * 3 * The LLVM Compiler Infrastructure 4 * 5 * This file is distributed under the University of Illinois Open Source 6 * License. See LICENSE.TXT for details. 7 * 8 *===----------------------------------------------------------------------===* 9 * 10 * This file is part of the X86 Disassembler. 11 * It contains common definitions used by both the disassembler and the table 12 * generator. 13 * Documentation for the disassembler can be found in X86Disassembler.h. 14 * 15 *===----------------------------------------------------------------------===*/ 16 17 /* Capstone Disassembly Engine */ 18 /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */ 19 20 /* 21 * This header file provides those definitions that need to be shared between 22 * the decoder and the table generator in a C-friendly manner. 23 */ 24 25 #ifndef CS_X86_DISASSEMBLERDECODERCOMMON_H 26 #define CS_X86_DISASSEMBLERDECODERCOMMON_H 27 28 #define INSTRUCTIONS_SYM x86DisassemblerInstrSpecifiers 29 #define CONTEXTS_SYM x86DisassemblerContexts 30 #define ONEBYTE_SYM x86DisassemblerOneByteOpcodes 31 #define TWOBYTE_SYM x86DisassemblerTwoByteOpcodes 32 #define THREEBYTE38_SYM x86DisassemblerThreeByte38Opcodes 33 #define THREEBYTE3A_SYM x86DisassemblerThreeByte3AOpcodes 34 #define XOP8_MAP_SYM x86DisassemblerXOP8Opcodes 35 #define XOP9_MAP_SYM x86DisassemblerXOP9Opcodes 36 #define XOPA_MAP_SYM x86DisassemblerXOPAOpcodes 37 #define THREEDNOW_MAP_SYM x86Disassembler3DNowOpcodes 38 39 40 /* 41 * Attributes of an instruction that must be known before the opcode can be 42 * processed correctly. Most of these indicate the presence of particular 43 * prefixes, but ATTR_64BIT is simply an attribute of the decoding context. 44 */ 45 #define ATTRIBUTE_BITS \ 46 ENUM_ENTRY(ATTR_NONE, 0x00) \ 47 ENUM_ENTRY(ATTR_64BIT, (0x1 << 0)) \ 48 ENUM_ENTRY(ATTR_XS, (0x1 << 1)) \ 49 ENUM_ENTRY(ATTR_XD, (0x1 << 2)) \ 50 ENUM_ENTRY(ATTR_REXW, (0x1 << 3)) \ 51 ENUM_ENTRY(ATTR_OPSIZE, (0x1 << 4)) \ 52 ENUM_ENTRY(ATTR_ADSIZE, (0x1 << 5)) \ 53 ENUM_ENTRY(ATTR_VEX, (0x1 << 6)) \ 54 ENUM_ENTRY(ATTR_VEXL, (0x1 << 7)) \ 55 ENUM_ENTRY(ATTR_EVEX, (0x1 << 8)) \ 56 ENUM_ENTRY(ATTR_EVEXL, (0x1 << 9)) \ 57 ENUM_ENTRY(ATTR_EVEXL2, (0x1 << 10)) \ 58 ENUM_ENTRY(ATTR_EVEXK, (0x1 << 11)) \ 59 ENUM_ENTRY(ATTR_EVEXKZ, (0x1 << 12)) \ 60 ENUM_ENTRY(ATTR_EVEXB, (0x1 << 13)) 61 62 #define ENUM_ENTRY(n, v) n = v, 63 enum attributeBits { 64 ATTRIBUTE_BITS 65 ATTR_max 66 }; 67 #undef ENUM_ENTRY 68 69 /* 70 * Combinations of the above attributes that are relevant to instruction 71 * decode. Although other combinations are possible, they can be reduced to 72 * these without affecting the ultimately decoded instruction. 73 */ 74 75 // Class name Rank Rationale for rank assignment 76 #define INSTRUCTION_CONTEXTS \ 77 ENUM_ENTRY(IC, 0, "says nothing about the instruction") \ 78 ENUM_ENTRY(IC_64BIT, 1, "says the instruction applies in " \ 79 "64-bit mode but no more") \ 80 ENUM_ENTRY(IC_OPSIZE, 3, "requires an OPSIZE prefix, so " \ 81 "operands change width") \ 82 ENUM_ENTRY(IC_ADSIZE, 3, "requires an ADSIZE prefix, so " \ 83 "operands change width") \ 84 ENUM_ENTRY(IC_OPSIZE_ADSIZE, 4, "requires ADSIZE and OPSIZE prefixes") \ 85 ENUM_ENTRY(IC_XD, 2, "may say something about the opcode " \ 86 "but not the operands") \ 87 ENUM_ENTRY(IC_XS, 2, "may say something about the opcode " \ 88 "but not the operands") \ 89 ENUM_ENTRY(IC_XD_OPSIZE, 3, "requires an OPSIZE prefix, so " \ 90 "operands change width") \ 91 ENUM_ENTRY(IC_XS_OPSIZE, 3, "requires an OPSIZE prefix, so " \ 92 "operands change width") \ 93 ENUM_ENTRY(IC_XD_ADSIZE, 3, "requires an ADSIZE prefix, so " \ 94 "operands change width") \ 95 ENUM_ENTRY(IC_XS_ADSIZE, 3, "requires an ADSIZE prefix, so " \ 96 "operands change width") \ 97 ENUM_ENTRY(IC_64BIT_REXW, 5, "requires a REX.W prefix, so operands "\ 98 "change width; overrides IC_OPSIZE") \ 99 ENUM_ENTRY(IC_64BIT_REXW_ADSIZE, 6, "requires a REX.W prefix and 0x67 " \ 100 "prefix") \ 101 ENUM_ENTRY(IC_64BIT_OPSIZE, 3, "Just as meaningful as IC_OPSIZE") \ 102 ENUM_ENTRY(IC_64BIT_ADSIZE, 3, "Just as meaningful as IC_ADSIZE") \ 103 ENUM_ENTRY(IC_64BIT_OPSIZE_ADSIZE, 4, "Just as meaningful as IC_OPSIZE/" \ 104 "IC_ADSIZE") \ 105 ENUM_ENTRY(IC_64BIT_XD, 6, "XD instructions are SSE; REX.W is " \ 106 "secondary") \ 107 ENUM_ENTRY(IC_64BIT_XS, 6, "Just as meaningful as IC_64BIT_XD") \ 108 ENUM_ENTRY(IC_64BIT_XD_OPSIZE, 3, "Just as meaningful as IC_XD_OPSIZE") \ 109 ENUM_ENTRY(IC_64BIT_XS_OPSIZE, 3, "Just as meaningful as IC_XS_OPSIZE") \ 110 ENUM_ENTRY(IC_64BIT_XD_ADSIZE, 3, "Just as meaningful as IC_XD_ADSIZE") \ 111 ENUM_ENTRY(IC_64BIT_XS_ADSIZE, 3, "Just as meaningful as IC_XS_ADSIZE") \ 112 ENUM_ENTRY(IC_64BIT_REXW_XS, 7, "OPSIZE could mean a different " \ 113 "opcode") \ 114 ENUM_ENTRY(IC_64BIT_REXW_XD, 7, "Just as meaningful as " \ 115 "IC_64BIT_REXW_XS") \ 116 ENUM_ENTRY(IC_64BIT_REXW_OPSIZE, 8, "The Dynamic Duo! Prefer over all " \ 117 "else because this changes most " \ 118 "operands' meaning") \ 119 ENUM_ENTRY(IC_VEX, 1, "requires a VEX prefix") \ 120 ENUM_ENTRY(IC_VEX_XS, 2, "requires VEX and the XS prefix") \ 121 ENUM_ENTRY(IC_VEX_XD, 2, "requires VEX and the XD prefix") \ 122 ENUM_ENTRY(IC_VEX_OPSIZE, 2, "requires VEX and the OpSize prefix") \ 123 ENUM_ENTRY(IC_VEX_W, 3, "requires VEX and the W prefix") \ 124 ENUM_ENTRY(IC_VEX_W_XS, 4, "requires VEX, W, and XS prefix") \ 125 ENUM_ENTRY(IC_VEX_W_XD, 4, "requires VEX, W, and XD prefix") \ 126 ENUM_ENTRY(IC_VEX_W_OPSIZE, 4, "requires VEX, W, and OpSize") \ 127 ENUM_ENTRY(IC_VEX_L, 3, "requires VEX and the L prefix") \ 128 ENUM_ENTRY(IC_VEX_L_XS, 4, "requires VEX and the L and XS prefix")\ 129 ENUM_ENTRY(IC_VEX_L_XD, 4, "requires VEX and the L and XD prefix")\ 130 ENUM_ENTRY(IC_VEX_L_OPSIZE, 4, "requires VEX, L, and OpSize") \ 131 ENUM_ENTRY(IC_VEX_L_W, 4, "requires VEX, L and W") \ 132 ENUM_ENTRY(IC_VEX_L_W_XS, 5, "requires VEX, L, W and XS prefix") \ 133 ENUM_ENTRY(IC_VEX_L_W_XD, 5, "requires VEX, L, W and XD prefix") \ 134 ENUM_ENTRY(IC_VEX_L_W_OPSIZE, 5, "requires VEX, L, W and OpSize") \ 135 ENUM_ENTRY(IC_EVEX, 1, "requires an EVEX prefix") \ 136 ENUM_ENTRY(IC_EVEX_XS, 2, "requires EVEX and the XS prefix") \ 137 ENUM_ENTRY(IC_EVEX_XD, 2, "requires EVEX and the XD prefix") \ 138 ENUM_ENTRY(IC_EVEX_OPSIZE, 2, "requires EVEX and the OpSize prefix") \ 139 ENUM_ENTRY(IC_EVEX_W, 3, "requires EVEX and the W prefix") \ 140 ENUM_ENTRY(IC_EVEX_W_XS, 4, "requires EVEX, W, and XS prefix") \ 141 ENUM_ENTRY(IC_EVEX_W_XD, 4, "requires EVEX, W, and XD prefix") \ 142 ENUM_ENTRY(IC_EVEX_W_OPSIZE, 4, "requires EVEX, W, and OpSize") \ 143 ENUM_ENTRY(IC_EVEX_L, 3, "requires EVEX and the L prefix") \ 144 ENUM_ENTRY(IC_EVEX_L_XS, 4, "requires EVEX and the L and XS prefix")\ 145 ENUM_ENTRY(IC_EVEX_L_XD, 4, "requires EVEX and the L and XD prefix")\ 146 ENUM_ENTRY(IC_EVEX_L_OPSIZE, 4, "requires EVEX, L, and OpSize") \ 147 ENUM_ENTRY(IC_EVEX_L_W, 3, "requires EVEX, L and W") \ 148 ENUM_ENTRY(IC_EVEX_L_W_XS, 4, "requires EVEX, L, W and XS prefix") \ 149 ENUM_ENTRY(IC_EVEX_L_W_XD, 4, "requires EVEX, L, W and XD prefix") \ 150 ENUM_ENTRY(IC_EVEX_L_W_OPSIZE, 4, "requires EVEX, L, W and OpSize") \ 151 ENUM_ENTRY(IC_EVEX_L2, 3, "requires EVEX and the L2 prefix") \ 152 ENUM_ENTRY(IC_EVEX_L2_XS, 4, "requires EVEX and the L2 and XS prefix")\ 153 ENUM_ENTRY(IC_EVEX_L2_XD, 4, "requires EVEX and the L2 and XD prefix")\ 154 ENUM_ENTRY(IC_EVEX_L2_OPSIZE, 4, "requires EVEX, L2, and OpSize") \ 155 ENUM_ENTRY(IC_EVEX_L2_W, 3, "requires EVEX, L2 and W") \ 156 ENUM_ENTRY(IC_EVEX_L2_W_XS, 4, "requires EVEX, L2, W and XS prefix") \ 157 ENUM_ENTRY(IC_EVEX_L2_W_XD, 4, "requires EVEX, L2, W and XD prefix") \ 158 ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE, 4, "requires EVEX, L2, W and OpSize") \ 159 ENUM_ENTRY(IC_EVEX_K, 1, "requires an EVEX_K prefix") \ 160 ENUM_ENTRY(IC_EVEX_XS_K, 2, "requires EVEX_K and the XS prefix") \ 161 ENUM_ENTRY(IC_EVEX_XD_K, 2, "requires EVEX_K and the XD prefix") \ 162 ENUM_ENTRY(IC_EVEX_OPSIZE_K, 2, "requires EVEX_K and the OpSize prefix") \ 163 ENUM_ENTRY(IC_EVEX_W_K, 3, "requires EVEX_K and the W prefix") \ 164 ENUM_ENTRY(IC_EVEX_W_XS_K, 4, "requires EVEX_K, W, and XS prefix") \ 165 ENUM_ENTRY(IC_EVEX_W_XD_K, 4, "requires EVEX_K, W, and XD prefix") \ 166 ENUM_ENTRY(IC_EVEX_W_OPSIZE_K, 4, "requires EVEX_K, W, and OpSize") \ 167 ENUM_ENTRY(IC_EVEX_L_K, 3, "requires EVEX_K and the L prefix") \ 168 ENUM_ENTRY(IC_EVEX_L_XS_K, 4, "requires EVEX_K and the L and XS prefix")\ 169 ENUM_ENTRY(IC_EVEX_L_XD_K, 4, "requires EVEX_K and the L and XD prefix")\ 170 ENUM_ENTRY(IC_EVEX_L_OPSIZE_K, 4, "requires EVEX_K, L, and OpSize") \ 171 ENUM_ENTRY(IC_EVEX_L_W_K, 3, "requires EVEX_K, L and W") \ 172 ENUM_ENTRY(IC_EVEX_L_W_XS_K, 4, "requires EVEX_K, L, W and XS prefix") \ 173 ENUM_ENTRY(IC_EVEX_L_W_XD_K, 4, "requires EVEX_K, L, W and XD prefix") \ 174 ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_K, 4, "requires EVEX_K, L, W and OpSize") \ 175 ENUM_ENTRY(IC_EVEX_L2_K, 3, "requires EVEX_K and the L2 prefix") \ 176 ENUM_ENTRY(IC_EVEX_L2_XS_K, 4, "requires EVEX_K and the L2 and XS prefix")\ 177 ENUM_ENTRY(IC_EVEX_L2_XD_K, 4, "requires EVEX_K and the L2 and XD prefix")\ 178 ENUM_ENTRY(IC_EVEX_L2_OPSIZE_K, 4, "requires EVEX_K, L2, and OpSize") \ 179 ENUM_ENTRY(IC_EVEX_L2_W_K, 3, "requires EVEX_K, L2 and W") \ 180 ENUM_ENTRY(IC_EVEX_L2_W_XS_K, 4, "requires EVEX_K, L2, W and XS prefix") \ 181 ENUM_ENTRY(IC_EVEX_L2_W_XD_K, 4, "requires EVEX_K, L2, W and XD prefix") \ 182 ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_K, 4, "requires EVEX_K, L2, W and OpSize") \ 183 ENUM_ENTRY(IC_EVEX_B, 1, "requires an EVEX_B prefix") \ 184 ENUM_ENTRY(IC_EVEX_XS_B, 2, "requires EVEX_B and the XS prefix") \ 185 ENUM_ENTRY(IC_EVEX_XD_B, 2, "requires EVEX_B and the XD prefix") \ 186 ENUM_ENTRY(IC_EVEX_OPSIZE_B, 2, "requires EVEX_B and the OpSize prefix") \ 187 ENUM_ENTRY(IC_EVEX_W_B, 3, "requires EVEX_B and the W prefix") \ 188 ENUM_ENTRY(IC_EVEX_W_XS_B, 4, "requires EVEX_B, W, and XS prefix") \ 189 ENUM_ENTRY(IC_EVEX_W_XD_B, 4, "requires EVEX_B, W, and XD prefix") \ 190 ENUM_ENTRY(IC_EVEX_W_OPSIZE_B, 4, "requires EVEX_B, W, and OpSize") \ 191 ENUM_ENTRY(IC_EVEX_L_B, 3, "requires EVEX_B and the L prefix") \ 192 ENUM_ENTRY(IC_EVEX_L_XS_B, 4, "requires EVEX_B and the L and XS prefix")\ 193 ENUM_ENTRY(IC_EVEX_L_XD_B, 4, "requires EVEX_B and the L and XD prefix")\ 194 ENUM_ENTRY(IC_EVEX_L_OPSIZE_B, 4, "requires EVEX_B, L, and OpSize") \ 195 ENUM_ENTRY(IC_EVEX_L_W_B, 3, "requires EVEX_B, L and W") \ 196 ENUM_ENTRY(IC_EVEX_L_W_XS_B, 4, "requires EVEX_B, L, W and XS prefix") \ 197 ENUM_ENTRY(IC_EVEX_L_W_XD_B, 4, "requires EVEX_B, L, W and XD prefix") \ 198 ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_B, 4, "requires EVEX_B, L, W and OpSize") \ 199 ENUM_ENTRY(IC_EVEX_L2_B, 3, "requires EVEX_B and the L2 prefix") \ 200 ENUM_ENTRY(IC_EVEX_L2_XS_B, 4, "requires EVEX_B and the L2 and XS prefix")\ 201 ENUM_ENTRY(IC_EVEX_L2_XD_B, 4, "requires EVEX_B and the L2 and XD prefix")\ 202 ENUM_ENTRY(IC_EVEX_L2_OPSIZE_B, 4, "requires EVEX_B, L2, and OpSize") \ 203 ENUM_ENTRY(IC_EVEX_L2_W_B, 3, "requires EVEX_B, L2 and W") \ 204 ENUM_ENTRY(IC_EVEX_L2_W_XS_B, 4, "requires EVEX_B, L2, W and XS prefix") \ 205 ENUM_ENTRY(IC_EVEX_L2_W_XD_B, 4, "requires EVEX_B, L2, W and XD prefix") \ 206 ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_B, 4, "requires EVEX_B, L2, W and OpSize") \ 207 ENUM_ENTRY(IC_EVEX_K_B, 1, "requires EVEX_B and EVEX_K prefix") \ 208 ENUM_ENTRY(IC_EVEX_XS_K_B, 2, "requires EVEX_B, EVEX_K and the XS prefix") \ 209 ENUM_ENTRY(IC_EVEX_XD_K_B, 2, "requires EVEX_B, EVEX_K and the XD prefix") \ 210 ENUM_ENTRY(IC_EVEX_OPSIZE_K_B, 2, "requires EVEX_B, EVEX_K and the OpSize prefix") \ 211 ENUM_ENTRY(IC_EVEX_W_K_B, 3, "requires EVEX_B, EVEX_K and the W prefix") \ 212 ENUM_ENTRY(IC_EVEX_W_XS_K_B, 4, "requires EVEX_B, EVEX_K, W, and XS prefix") \ 213 ENUM_ENTRY(IC_EVEX_W_XD_K_B, 4, "requires EVEX_B, EVEX_K, W, and XD prefix") \ 214 ENUM_ENTRY(IC_EVEX_W_OPSIZE_K_B, 4, "requires EVEX_B, EVEX_K, W, and OpSize") \ 215 ENUM_ENTRY(IC_EVEX_L_K_B, 3, "requires EVEX_B, EVEX_K and the L prefix") \ 216 ENUM_ENTRY(IC_EVEX_L_XS_K_B, 4, "requires EVEX_B, EVEX_K and the L and XS prefix")\ 217 ENUM_ENTRY(IC_EVEX_L_XD_K_B, 4, "requires EVEX_B, EVEX_K and the L and XD prefix")\ 218 ENUM_ENTRY(IC_EVEX_L_OPSIZE_K_B, 4, "requires EVEX_B, EVEX_K, L, and OpSize") \ 219 ENUM_ENTRY(IC_EVEX_L_W_K_B, 3, "requires EVEX_B, EVEX_K, L and W") \ 220 ENUM_ENTRY(IC_EVEX_L_W_XS_K_B, 4, "requires EVEX_B, EVEX_K, L, W and XS prefix") \ 221 ENUM_ENTRY(IC_EVEX_L_W_XD_K_B, 4, "requires EVEX_B, EVEX_K, L, W and XD prefix") \ 222 ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_K_B,4, "requires EVEX_B, EVEX_K, L, W and OpSize") \ 223 ENUM_ENTRY(IC_EVEX_L2_K_B, 3, "requires EVEX_B, EVEX_K and the L2 prefix") \ 224 ENUM_ENTRY(IC_EVEX_L2_XS_K_B, 4, "requires EVEX_B, EVEX_K and the L2 and XS prefix")\ 225 ENUM_ENTRY(IC_EVEX_L2_XD_K_B, 4, "requires EVEX_B, EVEX_K and the L2 and XD prefix")\ 226 ENUM_ENTRY(IC_EVEX_L2_OPSIZE_K_B, 4, "requires EVEX_B, EVEX_K, L2, and OpSize") \ 227 ENUM_ENTRY(IC_EVEX_L2_W_K_B, 3, "requires EVEX_B, EVEX_K, L2 and W") \ 228 ENUM_ENTRY(IC_EVEX_L2_W_XS_K_B, 4, "requires EVEX_B, EVEX_K, L2, W and XS prefix") \ 229 ENUM_ENTRY(IC_EVEX_L2_W_XD_K_B, 4, "requires EVEX_B, EVEX_K, L2, W and XD prefix") \ 230 ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_K_B,4, "requires EVEX_B, EVEX_K, L2, W and OpSize") \ 231 ENUM_ENTRY(IC_EVEX_KZ_B, 1, "requires EVEX_B and EVEX_KZ prefix") \ 232 ENUM_ENTRY(IC_EVEX_XS_KZ_B, 2, "requires EVEX_B, EVEX_KZ and the XS prefix") \ 233 ENUM_ENTRY(IC_EVEX_XD_KZ_B, 2, "requires EVEX_B, EVEX_KZ and the XD prefix") \ 234 ENUM_ENTRY(IC_EVEX_OPSIZE_KZ_B, 2, "requires EVEX_B, EVEX_KZ and the OpSize prefix") \ 235 ENUM_ENTRY(IC_EVEX_W_KZ_B, 3, "requires EVEX_B, EVEX_KZ and the W prefix") \ 236 ENUM_ENTRY(IC_EVEX_W_XS_KZ_B, 4, "requires EVEX_B, EVEX_KZ, W, and XS prefix") \ 237 ENUM_ENTRY(IC_EVEX_W_XD_KZ_B, 4, "requires EVEX_B, EVEX_KZ, W, and XD prefix") \ 238 ENUM_ENTRY(IC_EVEX_W_OPSIZE_KZ_B, 4, "requires EVEX_B, EVEX_KZ, W, and OpSize") \ 239 ENUM_ENTRY(IC_EVEX_L_KZ_B, 3, "requires EVEX_B, EVEX_KZ and the L prefix") \ 240 ENUM_ENTRY(IC_EVEX_L_XS_KZ_B, 4, "requires EVEX_B, EVEX_KZ and the L and XS prefix")\ 241 ENUM_ENTRY(IC_EVEX_L_XD_KZ_B, 4, "requires EVEX_B, EVEX_KZ and the L and XD prefix")\ 242 ENUM_ENTRY(IC_EVEX_L_OPSIZE_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L, and OpSize") \ 243 ENUM_ENTRY(IC_EVEX_L_W_KZ_B, 3, "requires EVEX_B, EVEX_KZ, L and W") \ 244 ENUM_ENTRY(IC_EVEX_L_W_XS_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L, W and XS prefix") \ 245 ENUM_ENTRY(IC_EVEX_L_W_XD_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L, W and XD prefix") \ 246 ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L, W and OpSize") \ 247 ENUM_ENTRY(IC_EVEX_L2_KZ_B, 3, "requires EVEX_B, EVEX_KZ and the L2 prefix") \ 248 ENUM_ENTRY(IC_EVEX_L2_XS_KZ_B, 4, "requires EVEX_B, EVEX_KZ and the L2 and XS prefix")\ 249 ENUM_ENTRY(IC_EVEX_L2_XD_KZ_B, 4, "requires EVEX_B, EVEX_KZ and the L2 and XD prefix")\ 250 ENUM_ENTRY(IC_EVEX_L2_OPSIZE_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L2, and OpSize") \ 251 ENUM_ENTRY(IC_EVEX_L2_W_KZ_B, 3, "requires EVEX_B, EVEX_KZ, L2 and W") \ 252 ENUM_ENTRY(IC_EVEX_L2_W_XS_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L2, W and XS prefix") \ 253 ENUM_ENTRY(IC_EVEX_L2_W_XD_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L2, W and XD prefix") \ 254 ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L2, W and OpSize") \ 255 ENUM_ENTRY(IC_EVEX_KZ, 1, "requires an EVEX_KZ prefix") \ 256 ENUM_ENTRY(IC_EVEX_XS_KZ, 2, "requires EVEX_KZ and the XS prefix") \ 257 ENUM_ENTRY(IC_EVEX_XD_KZ, 2, "requires EVEX_KZ and the XD prefix") \ 258 ENUM_ENTRY(IC_EVEX_OPSIZE_KZ, 2, "requires EVEX_KZ and the OpSize prefix") \ 259 ENUM_ENTRY(IC_EVEX_W_KZ, 3, "requires EVEX_KZ and the W prefix") \ 260 ENUM_ENTRY(IC_EVEX_W_XS_KZ, 4, "requires EVEX_KZ, W, and XS prefix") \ 261 ENUM_ENTRY(IC_EVEX_W_XD_KZ, 4, "requires EVEX_KZ, W, and XD prefix") \ 262 ENUM_ENTRY(IC_EVEX_W_OPSIZE_KZ, 4, "requires EVEX_KZ, W, and OpSize") \ 263 ENUM_ENTRY(IC_EVEX_L_KZ, 3, "requires EVEX_KZ and the L prefix") \ 264 ENUM_ENTRY(IC_EVEX_L_XS_KZ, 4, "requires EVEX_KZ and the L and XS prefix")\ 265 ENUM_ENTRY(IC_EVEX_L_XD_KZ, 4, "requires EVEX_KZ and the L and XD prefix")\ 266 ENUM_ENTRY(IC_EVEX_L_OPSIZE_KZ, 4, "requires EVEX_KZ, L, and OpSize") \ 267 ENUM_ENTRY(IC_EVEX_L_W_KZ, 3, "requires EVEX_KZ, L and W") \ 268 ENUM_ENTRY(IC_EVEX_L_W_XS_KZ, 4, "requires EVEX_KZ, L, W and XS prefix") \ 269 ENUM_ENTRY(IC_EVEX_L_W_XD_KZ, 4, "requires EVEX_KZ, L, W and XD prefix") \ 270 ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_KZ, 4, "requires EVEX_KZ, L, W and OpSize") \ 271 ENUM_ENTRY(IC_EVEX_L2_KZ, 3, "requires EVEX_KZ and the L2 prefix") \ 272 ENUM_ENTRY(IC_EVEX_L2_XS_KZ, 4, "requires EVEX_KZ and the L2 and XS prefix")\ 273 ENUM_ENTRY(IC_EVEX_L2_XD_KZ, 4, "requires EVEX_KZ and the L2 and XD prefix")\ 274 ENUM_ENTRY(IC_EVEX_L2_OPSIZE_KZ, 4, "requires EVEX_KZ, L2, and OpSize") \ 275 ENUM_ENTRY(IC_EVEX_L2_W_KZ, 3, "requires EVEX_KZ, L2 and W") \ 276 ENUM_ENTRY(IC_EVEX_L2_W_XS_KZ, 4, "requires EVEX_KZ, L2, W and XS prefix") \ 277 ENUM_ENTRY(IC_EVEX_L2_W_XD_KZ, 4, "requires EVEX_KZ, L2, W and XD prefix") \ 278 ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_KZ, 4, "requires EVEX_KZ, L2, W and OpSize") 279 280 #define ENUM_ENTRY(n, r, d) n, 281 typedef enum { 282 INSTRUCTION_CONTEXTS 283 IC_max 284 } InstructionContext; 285 #undef ENUM_ENTRY 286 287 /* 288 * Opcode types, which determine which decode table to use, both in the Intel 289 * manual and also for the decoder. 290 */ 291 typedef enum { 292 ONEBYTE = 0, 293 TWOBYTE = 1, 294 THREEBYTE_38 = 2, 295 THREEBYTE_3A = 3, 296 XOP8_MAP = 4, 297 XOP9_MAP = 5, 298 XOPA_MAP = 6, 299 THREEDNOW_MAP = 7 300 } OpcodeType; 301 302 /* 303 * The following structs are used for the hierarchical decode table. After 304 * determining the instruction's class (i.e., which IC_* constant applies to 305 * it), the decoder reads the opcode. Some instructions require specific 306 * values of the ModR/M byte, so the ModR/M byte indexes into the final table. 307 * 308 * If a ModR/M byte is not required, "required" is left unset, and the values 309 * for each instructionID are identical. 310 */ 311 312 typedef uint16_t InstrUID; 313 314 /* 315 * ModRMDecisionType - describes the type of ModR/M decision, allowing the 316 * consumer to determine the number of entries in it. 317 * 318 * MODRM_ONEENTRY - No matter what the value of the ModR/M byte is, the decoded 319 * instruction is the same. 320 * MODRM_SPLITRM - If the ModR/M byte is between 0x00 and 0xbf, the opcode 321 * corresponds to one instruction; otherwise, it corresponds to 322 * a different instruction. 323 * MODRM_SPLITMISC- If the ModR/M byte is between 0x00 and 0xbf, ModR/M byte 324 * divided by 8 is used to select instruction; otherwise, each 325 * value of the ModR/M byte could correspond to a different 326 * instruction. 327 * MODRM_SPLITREG - ModR/M byte divided by 8 is used to select instruction. This 328 corresponds to instructions that use reg field as opcode 329 * MODRM_FULL - Potentially, each value of the ModR/M byte could correspond 330 * to a different instruction. 331 */ 332 333 #define MODRMTYPES \ 334 ENUM_ENTRY(MODRM_ONEENTRY) \ 335 ENUM_ENTRY(MODRM_SPLITRM) \ 336 ENUM_ENTRY(MODRM_SPLITMISC) \ 337 ENUM_ENTRY(MODRM_SPLITREG) \ 338 ENUM_ENTRY(MODRM_FULL) 339 340 #define ENUM_ENTRY(n) n, 341 typedef enum { 342 MODRMTYPES 343 MODRM_max 344 } ModRMDecisionType; 345 #undef ENUM_ENTRY 346 347 #define CASE_ENCODING_RM \ 348 case ENCODING_RM: \ 349 case ENCODING_RM_CD2: \ 350 case ENCODING_RM_CD4: \ 351 case ENCODING_RM_CD8: \ 352 case ENCODING_RM_CD16: \ 353 case ENCODING_RM_CD32: \ 354 case ENCODING_RM_CD64 355 356 #define CASE_ENCODING_VSIB \ 357 case ENCODING_VSIB: \ 358 case ENCODING_VSIB_CD2: \ 359 case ENCODING_VSIB_CD4: \ 360 case ENCODING_VSIB_CD8: \ 361 case ENCODING_VSIB_CD16: \ 362 case ENCODING_VSIB_CD32: \ 363 case ENCODING_VSIB_CD64 364 365 // Physical encodings of instruction operands. 366 367 #define ENCODINGS \ 368 ENUM_ENTRY(ENCODING_NONE, "") \ 369 ENUM_ENTRY(ENCODING_REG, "Register operand in ModR/M byte.") \ 370 ENUM_ENTRY(ENCODING_RM, "R/M operand in ModR/M byte.") \ 371 ENUM_ENTRY(ENCODING_RM_CD2, "R/M operand with CDisp scaling of 2") \ 372 ENUM_ENTRY(ENCODING_RM_CD4, "R/M operand with CDisp scaling of 4") \ 373 ENUM_ENTRY(ENCODING_RM_CD8, "R/M operand with CDisp scaling of 8") \ 374 ENUM_ENTRY(ENCODING_RM_CD16,"R/M operand with CDisp scaling of 16") \ 375 ENUM_ENTRY(ENCODING_RM_CD32,"R/M operand with CDisp scaling of 32") \ 376 ENUM_ENTRY(ENCODING_RM_CD64,"R/M operand with CDisp scaling of 64") \ 377 ENUM_ENTRY(ENCODING_VSIB, "VSIB operand in ModR/M byte.") \ 378 ENUM_ENTRY(ENCODING_VSIB_CD2, "VSIB operand with CDisp scaling of 2") \ 379 ENUM_ENTRY(ENCODING_VSIB_CD4, "VSIB operand with CDisp scaling of 4") \ 380 ENUM_ENTRY(ENCODING_VSIB_CD8, "VSIB operand with CDisp scaling of 8") \ 381 ENUM_ENTRY(ENCODING_VSIB_CD16,"VSIB operand with CDisp scaling of 16") \ 382 ENUM_ENTRY(ENCODING_VSIB_CD32,"VSIB operand with CDisp scaling of 32") \ 383 ENUM_ENTRY(ENCODING_VSIB_CD64,"VSIB operand with CDisp scaling of 64") \ 384 ENUM_ENTRY(ENCODING_VVVV, "Register operand in VEX.vvvv byte.") \ 385 ENUM_ENTRY(ENCODING_WRITEMASK, "Register operand in EVEX.aaa byte.") \ 386 ENUM_ENTRY(ENCODING_IB, "1-byte immediate") \ 387 ENUM_ENTRY(ENCODING_IW, "2-byte") \ 388 ENUM_ENTRY(ENCODING_ID, "4-byte") \ 389 ENUM_ENTRY(ENCODING_IO, "8-byte") \ 390 ENUM_ENTRY(ENCODING_RB, "(AL..DIL, R8L..R15L) Register code added to " \ 391 "the opcode byte") \ 392 ENUM_ENTRY(ENCODING_RW, "(AX..DI, R8W..R15W)") \ 393 ENUM_ENTRY(ENCODING_RD, "(EAX..EDI, R8D..R15D)") \ 394 ENUM_ENTRY(ENCODING_RO, "(RAX..RDI, R8..R15)") \ 395 ENUM_ENTRY(ENCODING_FP, "Position on floating-point stack in ModR/M " \ 396 "byte.") \ 397 ENUM_ENTRY(ENCODING_Iv, "Immediate of operand size") \ 398 ENUM_ENTRY(ENCODING_Ia, "Immediate of address size") \ 399 ENUM_ENTRY(ENCODING_IRC, "Immediate for static rounding control") \ 400 ENUM_ENTRY(ENCODING_Rv, "Register code of operand size added to the " \ 401 "opcode byte") \ 402 ENUM_ENTRY(ENCODING_DUP, "Duplicate of another operand; ID is encoded " \ 403 "in type") \ 404 ENUM_ENTRY(ENCODING_SI, "Source index; encoded in OpSize/Adsize prefix") \ 405 ENUM_ENTRY(ENCODING_DI, "Destination index; encoded in prefixes") 406 407 #define ENUM_ENTRY(n, d) n, 408 typedef enum { 409 ENCODINGS 410 ENCODING_max 411 } OperandEncoding; 412 #undef ENUM_ENTRY 413 414 /* 415 * Semantic interpretations of instruction operands. 416 */ 417 #define TYPES \ 418 ENUM_ENTRY(TYPE_NONE, "") \ 419 ENUM_ENTRY(TYPE_REL, "immediate address") \ 420 ENUM_ENTRY(TYPE_R8, "1-byte register operand") \ 421 ENUM_ENTRY(TYPE_R16, "2-byte") \ 422 ENUM_ENTRY(TYPE_R32, "4-byte") \ 423 ENUM_ENTRY(TYPE_R64, "8-byte") \ 424 ENUM_ENTRY(TYPE_IMM, "immediate operand") \ 425 ENUM_ENTRY(TYPE_IMM3, "1-byte immediate operand between 0 and 7") \ 426 ENUM_ENTRY(TYPE_IMM5, "1-byte immediate operand between 0 and 31") \ 427 ENUM_ENTRY(TYPE_AVX512ICC, "1-byte immediate operand for AVX512 icmp") \ 428 ENUM_ENTRY(TYPE_UIMM8, "1-byte unsigned immediate operand") \ 429 ENUM_ENTRY(TYPE_M, "Memory operand") \ 430 ENUM_ENTRY(TYPE_MVSIBX, "Memory operand using XMM index") \ 431 ENUM_ENTRY(TYPE_MVSIBY, "Memory operand using YMM index") \ 432 ENUM_ENTRY(TYPE_MVSIBZ, "Memory operand using ZMM index") \ 433 ENUM_ENTRY(TYPE_SRCIDX, "memory at source index") \ 434 ENUM_ENTRY(TYPE_DSTIDX, "memory at destination index") \ 435 ENUM_ENTRY(TYPE_MOFFS, "memory offset (relative to segment base)") \ 436 ENUM_ENTRY(TYPE_ST, "Position on the floating-point stack") \ 437 ENUM_ENTRY(TYPE_MM64, "8-byte MMX register") \ 438 ENUM_ENTRY(TYPE_XMM, "16-byte") \ 439 ENUM_ENTRY(TYPE_YMM, "32-byte") \ 440 ENUM_ENTRY(TYPE_ZMM, "64-byte") \ 441 ENUM_ENTRY(TYPE_VK, "mask register") \ 442 ENUM_ENTRY(TYPE_SEGMENTREG, "Segment register operand") \ 443 ENUM_ENTRY(TYPE_DEBUGREG, "Debug register operand") \ 444 ENUM_ENTRY(TYPE_CONTROLREG, "Control register operand") \ 445 ENUM_ENTRY(TYPE_BNDR, "MPX bounds register") \ 446 \ 447 ENUM_ENTRY(TYPE_Rv, "Register operand of operand size") \ 448 ENUM_ENTRY(TYPE_RELv, "Immediate address of operand size") \ 449 ENUM_ENTRY(TYPE_DUP0, "Duplicate of operand 0") \ 450 ENUM_ENTRY(TYPE_DUP1, "operand 1") \ 451 ENUM_ENTRY(TYPE_DUP2, "operand 2") \ 452 ENUM_ENTRY(TYPE_DUP3, "operand 3") \ 453 ENUM_ENTRY(TYPE_DUP4, "operand 4") \ 454 455 #define ENUM_ENTRY(n, d) n, 456 typedef enum { 457 TYPES 458 TYPE_max 459 } OperandType; 460 #undef ENUM_ENTRY 461 462 /* 463 * The specification for how to extract and interpret one operand. 464 */ 465 typedef struct OperandSpecifier { 466 uint8_t encoding; 467 uint8_t type; 468 } OperandSpecifier; 469 470 #define X86_MAX_OPERANDS 6 471 472 /* 473 * Decoding mode for the Intel disassembler. 16-bit, 32-bit, and 64-bit mode 474 * are supported, and represent real mode, IA-32e, and IA-32e in 64-bit mode, 475 * respectively. 476 */ 477 typedef enum { 478 MODE_16BIT, 479 MODE_32BIT, 480 MODE_64BIT 481 } DisassemblerMode; 482 483 #endif 484