1
2 /*
3 * QEMU OldWorld PowerMac (currently ~G3 Beige) hardware System Emulator
4 *
5 * Copyright (c) 2004-2007 Fabrice Bellard
6 * Copyright (c) 2007 Jocelyn Mayer
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 */
26
27 #include "qemu/osdep.h"
28 #include "qemu-common.h"
29 #include "qemu/units.h"
30 #include "qapi/error.h"
31 #include "hw/ppc/ppc.h"
32 #include "hw/qdev-properties.h"
33 #include "mac.h"
34 #include "hw/input/adb.h"
35 #include "sysemu/sysemu.h"
36 #include "net/net.h"
37 #include "hw/isa/isa.h"
38 #include "hw/pci/pci.h"
39 #include "hw/pci/pci_host.h"
40 #include "hw/boards.h"
41 #include "hw/nvram/fw_cfg.h"
42 #include "hw/char/escc.h"
43 #include "hw/misc/macio/macio.h"
44 #include "hw/loader.h"
45 #include "hw/fw-path-provider.h"
46 #include "elf.h"
47 #include "qemu/error-report.h"
48 #include "sysemu/kvm.h"
49 #include "sysemu/reset.h"
50 #include "kvm_ppc.h"
51 #include "exec/address-spaces.h"
52
53 #define MAX_IDE_BUS 2
54 #define CFG_ADDR 0xf0000510
55 #define TBFREQ 16600000UL
56 #define CLOCKFREQ 266000000UL
57 #define BUSFREQ 66000000UL
58
59 #define NDRV_VGA_FILENAME "qemu_vga.ndrv"
60
61 #define GRACKLE_BASE 0xfec00000
62 #define PROM_BASE 0xffc00000
63 #define PROM_SIZE (4 * MiB)
64
65 /* FreeBSD headers define this */
66 #ifdef round_page
67 #undef round_page
68 #endif
69
fw_cfg_boot_set(void * opaque,const char * boot_device,Error ** errp)70 static void fw_cfg_boot_set(void *opaque, const char *boot_device,
71 Error **errp)
72 {
73 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
74 }
75
translate_kernel_address(void * opaque,uint64_t addr)76 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
77 {
78 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
79 }
80
ppc_heathrow_reset(void * opaque)81 static void ppc_heathrow_reset(void *opaque)
82 {
83 PowerPCCPU *cpu = opaque;
84
85 cpu_reset(CPU(cpu));
86 }
87
ppc_heathrow_init(MachineState * machine)88 static void ppc_heathrow_init(MachineState *machine)
89 {
90 ram_addr_t ram_size = machine->ram_size;
91 const char *boot_device = machine->boot_order;
92 PowerPCCPU *cpu = NULL;
93 CPUPPCState *env = NULL;
94 char *filename;
95 int i;
96 MemoryRegion *bios = g_new(MemoryRegion, 1);
97 uint32_t kernel_base, initrd_base, cmdline_base = 0;
98 int32_t kernel_size, initrd_size;
99 PCIBus *pci_bus;
100 PCIDevice *macio;
101 MACIOIDEState *macio_ide;
102 ESCCState *escc;
103 SysBusDevice *s;
104 DeviceState *dev, *pic_dev;
105 BusState *adb_bus;
106 uint64_t bios_addr;
107 int bios_size;
108 unsigned int smp_cpus = machine->smp.cpus;
109 uint16_t ppc_boot_device;
110 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
111 void *fw_cfg;
112 uint64_t tbfreq;
113
114 /* init CPUs */
115 for (i = 0; i < smp_cpus; i++) {
116 cpu = POWERPC_CPU(cpu_create(machine->cpu_type));
117 env = &cpu->env;
118
119 /* Set time-base frequency to 16.6 Mhz */
120 cpu_ppc_tb_init(env, TBFREQ);
121 qemu_register_reset(ppc_heathrow_reset, cpu);
122 }
123
124 /* allocate RAM */
125 if (ram_size > 2047 * MiB) {
126 error_report("Too much memory for this machine: %" PRId64 " MB, "
127 "maximum 2047 MB", ram_size / MiB);
128 exit(1);
129 }
130
131 memory_region_add_subregion(get_system_memory(), 0, machine->ram);
132
133 /* allocate and load firmware ROM */
134 memory_region_init_rom(bios, NULL, "ppc_heathrow.bios", PROM_SIZE,
135 &error_fatal);
136 memory_region_add_subregion(get_system_memory(), PROM_BASE, bios);
137
138 if (!bios_name) {
139 bios_name = PROM_FILENAME;
140 }
141 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
142 if (filename) {
143 /* Load OpenBIOS (ELF) */
144 bios_size = load_elf(filename, NULL, NULL, NULL, NULL, &bios_addr,
145 NULL, NULL, 1, PPC_ELF_MACHINE, 0, 0);
146 /* Unfortunately, load_elf sign-extends reading elf32 */
147 bios_addr = (uint32_t)bios_addr;
148
149 if (bios_size <= 0) {
150 /* or if could not load ELF try loading a binary ROM image */
151 bios_size = load_image_targphys(filename, PROM_BASE, PROM_SIZE);
152 bios_addr = PROM_BASE;
153 }
154 g_free(filename);
155 } else {
156 bios_size = -1;
157 }
158 if (bios_size < 0 || bios_addr - PROM_BASE + bios_size > PROM_SIZE) {
159 error_report("could not load PowerPC bios '%s'", bios_name);
160 exit(1);
161 }
162
163 if (machine->kernel_filename) {
164 int bswap_needed;
165
166 #ifdef BSWAP_NEEDED
167 bswap_needed = 1;
168 #else
169 bswap_needed = 0;
170 #endif
171 kernel_base = KERNEL_LOAD_ADDR;
172 kernel_size = load_elf(machine->kernel_filename, NULL,
173 translate_kernel_address, NULL, NULL, NULL,
174 NULL, NULL, 1, PPC_ELF_MACHINE, 0, 0);
175 if (kernel_size < 0)
176 kernel_size = load_aout(machine->kernel_filename, kernel_base,
177 ram_size - kernel_base, bswap_needed,
178 TARGET_PAGE_SIZE);
179 if (kernel_size < 0)
180 kernel_size = load_image_targphys(machine->kernel_filename,
181 kernel_base,
182 ram_size - kernel_base);
183 if (kernel_size < 0) {
184 error_report("could not load kernel '%s'",
185 machine->kernel_filename);
186 exit(1);
187 }
188 /* load initrd */
189 if (machine->initrd_filename) {
190 initrd_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size +
191 KERNEL_GAP);
192 initrd_size = load_image_targphys(machine->initrd_filename,
193 initrd_base,
194 ram_size - initrd_base);
195 if (initrd_size < 0) {
196 error_report("could not load initial ram disk '%s'",
197 machine->initrd_filename);
198 exit(1);
199 }
200 cmdline_base = TARGET_PAGE_ALIGN(initrd_base + initrd_size);
201 } else {
202 initrd_base = 0;
203 initrd_size = 0;
204 cmdline_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + KERNEL_GAP);
205 }
206 ppc_boot_device = 'm';
207 } else {
208 kernel_base = 0;
209 kernel_size = 0;
210 initrd_base = 0;
211 initrd_size = 0;
212 ppc_boot_device = '\0';
213 for (i = 0; boot_device[i] != '\0'; i++) {
214 /* TOFIX: for now, the second IDE channel is not properly
215 * used by OHW. The Mac floppy disk are not emulated.
216 * For now, OHW cannot boot from the network.
217 */
218 #if 0
219 if (boot_device[i] >= 'a' && boot_device[i] <= 'f') {
220 ppc_boot_device = boot_device[i];
221 break;
222 }
223 #else
224 if (boot_device[i] >= 'c' && boot_device[i] <= 'd') {
225 ppc_boot_device = boot_device[i];
226 break;
227 }
228 #endif
229 }
230 if (ppc_boot_device == '\0') {
231 error_report("No valid boot device for G3 Beige machine");
232 exit(1);
233 }
234 }
235
236 /* XXX: we register only 1 output pin for heathrow PIC */
237 pic_dev = qdev_new(TYPE_HEATHROW);
238 sysbus_realize_and_unref(SYS_BUS_DEVICE(pic_dev), &error_fatal);
239
240 /* Connect the heathrow PIC outputs to the 6xx bus */
241 for (i = 0; i < smp_cpus; i++) {
242 switch (PPC_INPUT(env)) {
243 case PPC_FLAGS_INPUT_6xx:
244 qdev_connect_gpio_out(pic_dev, 0,
245 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]);
246 break;
247 default:
248 error_report("Bus model not supported on OldWorld Mac machine");
249 exit(1);
250 }
251 }
252
253 /* Timebase Frequency */
254 if (kvm_enabled()) {
255 tbfreq = kvmppc_get_tbfreq();
256 } else {
257 tbfreq = TBFREQ;
258 }
259
260 /* init basic PC hardware */
261 if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
262 error_report("Only 6xx bus is supported on heathrow machine");
263 exit(1);
264 }
265
266 /* Grackle PCI host bridge */
267 dev = qdev_new(TYPE_GRACKLE_PCI_HOST_BRIDGE);
268 qdev_prop_set_uint32(dev, "ofw-addr", 0x80000000);
269 s = SYS_BUS_DEVICE(dev);
270 sysbus_realize_and_unref(s, &error_fatal);
271
272 sysbus_mmio_map(s, 0, GRACKLE_BASE);
273 sysbus_mmio_map(s, 1, GRACKLE_BASE + 0x200000);
274 /* PCI hole */
275 memory_region_add_subregion(get_system_memory(), 0x80000000ULL,
276 sysbus_mmio_get_region(s, 2));
277 /* Register 2 MB of ISA IO space */
278 memory_region_add_subregion(get_system_memory(), 0xfe000000,
279 sysbus_mmio_get_region(s, 3));
280
281 for (i = 0; i < 4; i++) {
282 qdev_connect_gpio_out(dev, i, qdev_get_gpio_in(pic_dev, 0x15 + i));
283 }
284
285 pci_bus = PCI_HOST_BRIDGE(dev)->bus;
286
287 pci_vga_init(pci_bus);
288
289 for (i = 0; i < nb_nics; i++) {
290 pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL);
291 }
292
293 ide_drive_get(hd, ARRAY_SIZE(hd));
294
295 /* MacIO */
296 macio = pci_new(PCI_DEVFN(16, 0), TYPE_OLDWORLD_MACIO);
297 dev = DEVICE(macio);
298 qdev_prop_set_uint64(dev, "frequency", tbfreq);
299 object_property_set_link(OBJECT(macio), "pic", OBJECT(pic_dev),
300 &error_abort);
301
302 escc = ESCC(object_resolve_path_component(OBJECT(macio), "escc"));
303 qdev_prop_set_chr(DEVICE(escc), "chrA", serial_hd(0));
304 qdev_prop_set_chr(DEVICE(escc), "chrB", serial_hd(1));
305
306 pci_realize_and_unref(macio, pci_bus, &error_fatal);
307
308 macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio),
309 "ide[0]"));
310 macio_ide_init_drives(macio_ide, hd);
311
312 macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio),
313 "ide[1]"));
314 macio_ide_init_drives(macio_ide, &hd[MAX_IDE_DEVS]);
315
316 dev = DEVICE(object_resolve_path_component(OBJECT(macio), "cuda"));
317 adb_bus = qdev_get_child_bus(dev, "adb.0");
318 dev = qdev_new(TYPE_ADB_KEYBOARD);
319 qdev_realize_and_unref(dev, adb_bus, &error_fatal);
320 dev = qdev_new(TYPE_ADB_MOUSE);
321 qdev_realize_and_unref(dev, adb_bus, &error_fatal);
322
323 if (machine_usb(machine)) {
324 pci_create_simple(pci_bus, -1, "pci-ohci");
325 }
326
327 if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8)
328 graphic_depth = 15;
329
330 /* No PCI init: the BIOS will do it */
331
332 dev = qdev_new(TYPE_FW_CFG_MEM);
333 fw_cfg = FW_CFG(dev);
334 qdev_prop_set_uint32(dev, "data_width", 1);
335 qdev_prop_set_bit(dev, "dma_enabled", false);
336 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG,
337 OBJECT(fw_cfg));
338 s = SYS_BUS_DEVICE(dev);
339 sysbus_realize_and_unref(s, &error_fatal);
340 sysbus_mmio_map(s, 0, CFG_ADDR);
341 sysbus_mmio_map(s, 1, CFG_ADDR + 2);
342
343 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
344 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)machine->smp.max_cpus);
345 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
346 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_HEATHROW);
347 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base);
348 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
349 if (machine->kernel_cmdline) {
350 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base);
351 pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE,
352 machine->kernel_cmdline);
353 } else {
354 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
355 }
356 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base);
357 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
358 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device);
359
360 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width);
361 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height);
362 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth);
363
364 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled());
365 if (kvm_enabled()) {
366 uint8_t *hypercall;
367
368 hypercall = g_malloc(16);
369 kvmppc_get_hypercall(env, hypercall, 16);
370 fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16);
371 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid());
372 }
373 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, tbfreq);
374 /* Mac OS X requires a "known good" clock-frequency value; pass it one. */
375 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_CLOCKFREQ, CLOCKFREQ);
376 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_BUSFREQ, BUSFREQ);
377
378 /* MacOS NDRV VGA driver */
379 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, NDRV_VGA_FILENAME);
380 if (filename) {
381 gchar *ndrv_file;
382 gsize ndrv_size;
383
384 if (g_file_get_contents(filename, &ndrv_file, &ndrv_size, NULL)) {
385 fw_cfg_add_file(fw_cfg, "ndrv/qemu_vga.ndrv", ndrv_file, ndrv_size);
386 }
387 g_free(filename);
388 }
389
390 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
391 }
392
393 /*
394 * Implementation of an interface to adjust firmware path
395 * for the bootindex property handling.
396 */
heathrow_fw_dev_path(FWPathProvider * p,BusState * bus,DeviceState * dev)397 static char *heathrow_fw_dev_path(FWPathProvider *p, BusState *bus,
398 DeviceState *dev)
399 {
400 PCIDevice *pci;
401 IDEBus *ide_bus;
402 IDEState *ide_s;
403 MACIOIDEState *macio_ide;
404
405 if (!strcmp(object_get_typename(OBJECT(dev)), "macio-oldworld")) {
406 pci = PCI_DEVICE(dev);
407 return g_strdup_printf("mac-io@%x", PCI_SLOT(pci->devfn));
408 }
409
410 if (!strcmp(object_get_typename(OBJECT(dev)), "macio-ide")) {
411 macio_ide = MACIO_IDE(dev);
412 return g_strdup_printf("ata-3@%x", macio_ide->addr);
413 }
414
415 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-drive")) {
416 ide_bus = IDE_BUS(qdev_get_parent_bus(dev));
417 ide_s = idebus_active_if(ide_bus);
418
419 if (ide_s->drive_kind == IDE_CD) {
420 return g_strdup("cdrom");
421 }
422
423 return g_strdup("disk");
424 }
425
426 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-hd")) {
427 return g_strdup("disk");
428 }
429
430 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-cd")) {
431 return g_strdup("cdrom");
432 }
433
434 if (!strcmp(object_get_typename(OBJECT(dev)), "virtio-blk-device")) {
435 return g_strdup("disk");
436 }
437
438 return NULL;
439 }
440
heathrow_kvm_type(MachineState * machine,const char * arg)441 static int heathrow_kvm_type(MachineState *machine, const char *arg)
442 {
443 /* Always force PR KVM */
444 return 2;
445 }
446
heathrow_class_init(ObjectClass * oc,void * data)447 static void heathrow_class_init(ObjectClass *oc, void *data)
448 {
449 MachineClass *mc = MACHINE_CLASS(oc);
450 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc);
451
452 mc->desc = "Heathrow based PowerMAC";
453 mc->init = ppc_heathrow_init;
454 mc->block_default_type = IF_IDE;
455 mc->max_cpus = MAX_CPUS;
456 #ifndef TARGET_PPC64
457 mc->is_default = true;
458 #endif
459 /* TOFIX "cad" when Mac floppy is implemented */
460 mc->default_boot_order = "cd";
461 mc->kvm_type = heathrow_kvm_type;
462 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("750_v3.1");
463 mc->default_display = "std";
464 mc->ignore_boot_device_suffixes = true;
465 mc->default_ram_id = "ppc_heathrow.ram";
466 fwc->get_dev_path = heathrow_fw_dev_path;
467 }
468
469 static const TypeInfo ppc_heathrow_machine_info = {
470 .name = MACHINE_TYPE_NAME("g3beige"),
471 .parent = TYPE_MACHINE,
472 .class_init = heathrow_class_init,
473 .interfaces = (InterfaceInfo[]) {
474 { TYPE_FW_PATH_PROVIDER },
475 { }
476 },
477 };
478
ppc_heathrow_register_types(void)479 static void ppc_heathrow_register_types(void)
480 {
481 type_register_static(&ppc_heathrow_machine_info);
482 }
483
484 type_init(ppc_heathrow_register_types);
485