1 /** @file 2 Private Header file for Usb Host Controller PEIM 3 4 Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR> 5 6 SPDX-License-Identifier: BSD-2-Clause-Patent 7 8 **/ 9 10 #ifndef _EFI_PEI_XHCI_REG_H_ 11 #define _EFI_PEI_XHCI_REG_H_ 12 13 // 14 // Capability registers offset 15 // 16 #define XHC_CAPLENGTH_OFFSET 0x00 // Capability register length offset 17 #define XHC_HCIVERSION_OFFSET 0x02 // Interface Version Number 02-03h 18 #define XHC_HCSPARAMS1_OFFSET 0x04 // Structural Parameters 1 19 #define XHC_HCSPARAMS2_OFFSET 0x08 // Structural Parameters 2 20 #define XHC_HCSPARAMS3_OFFSET 0x0c // Structural Parameters 3 21 #define XHC_HCCPARAMS_OFFSET 0x10 // Capability Parameters 22 #define XHC_DBOFF_OFFSET 0x14 // Doorbell Offset 23 #define XHC_RTSOFF_OFFSET 0x18 // Runtime Register Space Offset 24 25 // 26 // Operational registers offset 27 // 28 #define XHC_USBCMD_OFFSET 0x0000 // USB Command Register Offset 29 #define XHC_USBSTS_OFFSET 0x0004 // USB Status Register Offset 30 #define XHC_PAGESIZE_OFFSET 0x0008 // USB Page Size Register Offset 31 #define XHC_DNCTRL_OFFSET 0x0014 // Device Notification Control Register Offset 32 #define XHC_CRCR_OFFSET 0x0018 // Command Ring Control Register Offset 33 #define XHC_DCBAAP_OFFSET 0x0030 // Device Context Base Address Array Pointer Register Offset 34 #define XHC_CONFIG_OFFSET 0x0038 // Configure Register Offset 35 #define XHC_PORTSC_OFFSET 0x0400 // Port Status and Control Register Offset 36 37 // 38 // Runtime registers offset 39 // 40 #define XHC_MFINDEX_OFFSET 0x00 // Microframe Index Register Offset 41 #define XHC_IMAN_OFFSET 0x20 // Interrupter X Management Register Offset 42 #define XHC_IMOD_OFFSET 0x24 // Interrupter X Moderation Register Offset 43 #define XHC_ERSTSZ_OFFSET 0x28 // Event Ring Segment Table Size Register Offset 44 #define XHC_ERSTBA_OFFSET 0x30 // Event Ring Segment Table Base Address Register Offset 45 #define XHC_ERDP_OFFSET 0x38 // Event Ring Dequeue Pointer Register Offset 46 47 // 48 // Register Bit Definition 49 // 50 #define XHC_USBCMD_RUN BIT0 // Run/Stop 51 #define XHC_USBCMD_RESET BIT1 // Host Controller Reset 52 #define XHC_USBCMD_INTE BIT2 // Interrupter Enable 53 #define XHC_USBCMD_HSEE BIT3 // Host System Error Enable 54 55 #define XHC_USBSTS_HALT BIT0 // Host Controller Halted 56 #define XHC_USBSTS_HSE BIT2 // Host System Error 57 #define XHC_USBSTS_EINT BIT3 // Event Interrupt 58 #define XHC_USBSTS_PCD BIT4 // Port Change Detect 59 #define XHC_USBSTS_SSS BIT8 // Save State Status 60 #define XHC_USBSTS_RSS BIT9 // Restore State Status 61 #define XHC_USBSTS_SRE BIT10 // Save/Restore Error 62 #define XHC_USBSTS_CNR BIT11 // Host Controller Not Ready 63 #define XHC_USBSTS_HCE BIT12 // Host Controller Error 64 65 #define XHC_PAGESIZE_MASK 0xFFFF // Page Size 66 67 #define XHC_CRCR_RCS BIT0 // Ring Cycle State 68 #define XHC_CRCR_CS BIT1 // Command Stop 69 #define XHC_CRCR_CA BIT2 // Command Abort 70 #define XHC_CRCR_CRR BIT3 // Command Ring Running 71 72 #define XHC_CONFIG_MASK 0xFF // Max Device Slots Enabled 73 74 #define XHC_PORTSC_CCS BIT0 // Current Connect Status 75 #define XHC_PORTSC_PED BIT1 // Port Enabled/Disabled 76 #define XHC_PORTSC_OCA BIT3 // Over-current Active 77 #define XHC_PORTSC_RESET BIT4 // Port Reset 78 #define XHC_PORTSC_PLS (BIT5|BIT6|BIT7|BIT8) // Port Link State 79 #define XHC_PORTSC_PP BIT9 // Port Power 80 #define XHC_PORTSC_PS (BIT10|BIT11|BIT12|BIT13) // Port Speed 81 #define XHC_PORTSC_LWS BIT16 // Port Link State Write Strobe 82 #define XHC_PORTSC_CSC BIT17 // Connect Status Change 83 #define XHC_PORTSC_PEC BIT18 // Port Enabled/Disabled Change 84 #define XHC_PORTSC_WRC BIT19 // Warm Port Reset Change 85 #define XHC_PORTSC_OCC BIT20 // Over-Current Change 86 #define XHC_PORTSC_PRC BIT21 // Port Reset Change 87 #define XHC_PORTSC_PLC BIT22 // Port Link State Change 88 #define XHC_PORTSC_CEC BIT23 // Port Config Error Change 89 #define XHC_PORTSC_CAS BIT24 // Cold Attach Status 90 91 #define XHC_HUB_PORTSC_CCS BIT0 // Hub's Current Connect Status 92 #define XHC_HUB_PORTSC_PED BIT1 // Hub's Port Enabled/Disabled 93 #define XHC_HUB_PORTSC_OCA BIT3 // Hub's Over-current Active 94 #define XHC_HUB_PORTSC_RESET BIT4 // Hub's Port Reset 95 #define XHC_HUB_PORTSC_PP BIT9 // Hub's Port Power 96 #define XHC_HUB_PORTSC_CSC BIT16 // Hub's Connect Status Change 97 #define XHC_HUB_PORTSC_PEC BIT17 // Hub's Port Enabled/Disabled Change 98 #define XHC_HUB_PORTSC_OCC BIT19 // Hub's Over-Current Change 99 #define XHC_HUB_PORTSC_PRC BIT20 // Hub's Port Reset Change 100 #define XHC_HUB_PORTSC_BHRC BIT21 // Hub's Port Warm Reset Change 101 102 #define XHC_IMAN_IP BIT0 // Interrupt Pending 103 #define XHC_IMAN_IE BIT1 // Interrupt Enable 104 105 #define XHC_IMODI_MASK 0x0000FFFF // Interrupt Moderation Interval 106 #define XHC_IMODC_MASK 0xFFFF0000 // Interrupt Moderation Counter 107 108 109 #pragma pack (1) 110 typedef struct { 111 UINT8 MaxSlots; // Number of Device Slots 112 UINT16 MaxIntrs:11; // Number of Interrupters 113 UINT16 Rsvd:5; 114 UINT8 MaxPorts; // Number of Ports 115 } HCSPARAMS1; 116 117 // 118 // Structural Parameters 1 Register Bitmap Definition 119 // 120 typedef union { 121 UINT32 Dword; 122 HCSPARAMS1 Data; 123 } XHC_HCSPARAMS1; 124 125 typedef struct { 126 UINT32 Ist:4; // Isochronous Scheduling Threshold 127 UINT32 Erst:4; // Event Ring Segment Table Max 128 UINT32 Rsvd:13; 129 UINT32 ScratchBufHi:5; // Max Scratchpad Buffers Hi 130 UINT32 Spr:1; // Scratchpad Restore 131 UINT32 ScratchBufLo:5; // Max Scratchpad Buffers Lo 132 } HCSPARAMS2; 133 134 // 135 // Structural Parameters 2 Register Bitmap Definition 136 // 137 typedef union { 138 UINT32 Dword; 139 HCSPARAMS2 Data; 140 } XHC_HCSPARAMS2; 141 142 typedef struct { 143 UINT16 Ac64:1; // 64-bit Addressing Capability 144 UINT16 Bnc:1; // BW Negotiation Capability 145 UINT16 Csz:1; // Context Size 146 UINT16 Ppc:1; // Port Power Control 147 UINT16 Pind:1; // Port Indicators 148 UINT16 Lhrc:1; // Light HC Reset Capability 149 UINT16 Ltc:1; // Latency Tolerance Messaging Capability 150 UINT16 Nss:1; // No Secondary SID Support 151 UINT16 Pae:1; // Parse All Event Data 152 UINT16 Rsvd:3; 153 UINT16 MaxPsaSize:4; // Maximum Primary Stream Array Size 154 UINT16 ExtCapReg; // xHCI Extended Capabilities Pointer 155 } HCCPARAMS; 156 157 // 158 // Capability Parameters Register Bitmap Definition 159 // 160 typedef union { 161 UINT32 Dword; 162 HCCPARAMS Data; 163 } XHC_HCCPARAMS; 164 165 #pragma pack () 166 167 // 168 // XHCi Data and Ctrl Structures 169 // 170 #pragma pack(1) 171 typedef struct { 172 UINT8 Pi; 173 UINT8 SubClassCode; 174 UINT8 BaseCode; 175 } USB_CLASSC; 176 177 typedef struct { 178 UINT8 Length; 179 UINT8 DescType; 180 UINT8 NumPorts; 181 UINT16 HubCharacter; 182 UINT8 PwrOn2PwrGood; 183 UINT8 HubContrCurrent; 184 UINT8 Filler[16]; 185 } EFI_USB_HUB_DESCRIPTOR; 186 #pragma pack() 187 188 // 189 // Hub Class Feature Selector for Clear Port Feature Request 190 // It's the extension of hub class feature selector of USB 2.0 in USB 3.0 Spec. 191 // For more details, Please refer to USB 3.0 Spec Table 10-7. 192 // 193 typedef enum { 194 Usb3PortBHPortReset = 28, 195 Usb3PortBHPortResetChange = 29 196 } XHC_PORT_FEATURE; 197 198 // 199 // Structure to map the hardware port states to the 200 // UEFI's port states. 201 // 202 typedef struct { 203 UINT32 HwState; 204 UINT16 UefiState; 205 } USB_PORT_STATE_MAP; 206 207 // 208 // Structure to map the hardware port states to feature selector for clear port feature request. 209 // 210 typedef struct { 211 UINT32 HwState; 212 UINT16 Selector; 213 } USB_CLEAR_PORT_MAP; 214 215 /** 216 Read XHCI Operation register. 217 218 @param Xhc The XHCI device. 219 @param Offset The operation register offset. 220 221 @retval the register content read. 222 223 **/ 224 UINT32 225 XhcPeiReadOpReg ( 226 IN PEI_XHC_DEV *Xhc, 227 IN UINT32 Offset 228 ); 229 230 /** 231 Write the data to the XHCI operation register. 232 233 @param Xhc The XHCI device. 234 @param Offset The operation register offset. 235 @param Data The data to write. 236 237 **/ 238 VOID 239 XhcPeiWriteOpReg ( 240 IN PEI_XHC_DEV *Xhc, 241 IN UINT32 Offset, 242 IN UINT32 Data 243 ); 244 245 /** 246 Set one bit of the operational register while keeping other bits. 247 248 @param Xhc The XHCI device. 249 @param Offset The offset of the operational register. 250 @param Bit The bit mask of the register to set. 251 252 **/ 253 VOID 254 XhcPeiSetOpRegBit ( 255 IN PEI_XHC_DEV *Xhc, 256 IN UINT32 Offset, 257 IN UINT32 Bit 258 ); 259 260 /** 261 Clear one bit of the operational register while keeping other bits. 262 263 @param Xhc The XHCI device. 264 @param Offset The offset of the operational register. 265 @param Bit The bit mask of the register to clear. 266 267 **/ 268 VOID 269 XhcPeiClearOpRegBit ( 270 IN PEI_XHC_DEV *Xhc, 271 IN UINT32 Offset, 272 IN UINT32 Bit 273 ); 274 275 /** 276 Wait the operation register's bit as specified by Bit 277 to be set (or clear). 278 279 @param Xhc The XHCI device. 280 @param Offset The offset of the operational register. 281 @param Bit The bit of the register to wait for. 282 @param WaitToSet Wait the bit to set or clear. 283 @param Timeout The time to wait before abort (in millisecond, ms). 284 285 @retval EFI_SUCCESS The bit successfully changed by host controller. 286 @retval EFI_TIMEOUT The time out occurred. 287 288 **/ 289 EFI_STATUS 290 XhcPeiWaitOpRegBit ( 291 IN PEI_XHC_DEV *Xhc, 292 IN UINT32 Offset, 293 IN UINT32 Bit, 294 IN BOOLEAN WaitToSet, 295 IN UINT32 Timeout 296 ); 297 298 299 /** 300 Write the data to the XHCI door bell register. 301 302 @param Xhc The XHCI device. 303 @param Offset The offset of the door bell register. 304 @param Data The data to write. 305 306 **/ 307 VOID 308 XhcPeiWriteDoorBellReg ( 309 IN PEI_XHC_DEV *Xhc, 310 IN UINT32 Offset, 311 IN UINT32 Data 312 ); 313 314 /** 315 Read XHCI runtime register. 316 317 @param Xhc The XHCI device. 318 @param Offset The offset of the runtime register. 319 320 @return The register content read 321 322 **/ 323 UINT32 324 XhcPeiReadRuntimeReg ( 325 IN PEI_XHC_DEV *Xhc, 326 IN UINT32 Offset 327 ); 328 329 /** 330 Write the data to the XHCI runtime register. 331 332 @param Xhc The XHCI device. 333 @param Offset The offset of the runtime register. 334 @param Data The data to write. 335 336 **/ 337 VOID 338 XhcPeiWriteRuntimeReg ( 339 IN PEI_XHC_DEV *Xhc, 340 IN UINT32 Offset, 341 IN UINT32 Data 342 ); 343 344 /** 345 Set one bit of the runtime register while keeping other bits. 346 347 @param Xhc The XHCI device. 348 @param Offset The offset of the runtime register. 349 @param Bit The bit mask of the register to set. 350 351 **/ 352 VOID 353 XhcPeiSetRuntimeRegBit ( 354 IN PEI_XHC_DEV *Xhc, 355 IN UINT32 Offset, 356 IN UINT32 Bit 357 ); 358 359 /** 360 Clear one bit of the runtime register while keeping other bits. 361 362 @param Xhc The XHCI device. 363 @param Offset The offset of the runtime register. 364 @param Bit The bit mask of the register to set. 365 366 **/ 367 VOID 368 XhcPeiClearRuntimeRegBit ( 369 IN PEI_XHC_DEV *Xhc, 370 IN UINT32 Offset, 371 IN UINT32 Bit 372 ); 373 374 /** 375 Check whether Xhc is halted. 376 377 @param Xhc The XHCI device. 378 379 @retval TRUE The controller is halted. 380 @retval FALSE The controller isn't halted. 381 382 **/ 383 BOOLEAN 384 XhcPeiIsHalt ( 385 IN PEI_XHC_DEV *Xhc 386 ); 387 388 /** 389 Check whether system error occurred. 390 391 @param Xhc The XHCI device. 392 393 @retval TRUE System error happened. 394 @retval FALSE No system error. 395 396 **/ 397 BOOLEAN 398 XhcPeiIsSysError ( 399 IN PEI_XHC_DEV *Xhc 400 ); 401 402 /** 403 Reset the host controller. 404 405 @param Xhc The XHCI device. 406 @param Timeout Time to wait before abort (in millisecond, ms). 407 408 @retval EFI_TIMEOUT The transfer failed due to time out. 409 @retval Others Failed to reset the host. 410 411 **/ 412 EFI_STATUS 413 XhcPeiResetHC ( 414 IN PEI_XHC_DEV *Xhc, 415 IN UINT32 Timeout 416 ); 417 418 /** 419 Halt the host controller. 420 421 @param Xhc The XHCI device. 422 @param Timeout Time to wait before abort. 423 424 @retval EFI_TIMEOUT Failed to halt the controller before Timeout. 425 @retval EFI_SUCCESS The XHCI is halt. 426 427 **/ 428 EFI_STATUS 429 XhcPeiHaltHC ( 430 IN PEI_XHC_DEV *Xhc, 431 IN UINT32 Timeout 432 ); 433 434 /** 435 Set the XHCI to run. 436 437 @param Xhc The XHCI device. 438 @param Timeout Time to wait before abort. 439 440 @retval EFI_SUCCESS The XHCI is running. 441 @retval Others Failed to set the XHCI to run. 442 443 **/ 444 EFI_STATUS 445 XhcPeiRunHC ( 446 IN PEI_XHC_DEV *Xhc, 447 IN UINT32 Timeout 448 ); 449 450 #endif 451