1 #ifndef TPM_DRIVERS_H 2 #define TPM_DRIVERS_H 3 4 #include "types.h" // u32 5 6 7 enum tpmDurationType { 8 TPM_DURATION_TYPE_SHORT = 0, 9 TPM_DURATION_TYPE_MEDIUM, 10 TPM_DURATION_TYPE_LONG, 11 }; 12 13 typedef u8 TPMVersion; 14 15 #define TPM_VERSION_NONE 0 16 #define TPM_VERSION_1_2 1 17 #define TPM_VERSION_2 2 18 19 TPMVersion tpmhw_probe(void); 20 int tpmhw_is_present(void); 21 struct tpm_req_header; 22 int tpmhw_transmit(u8 locty, struct tpm_req_header *req, 23 void *respbuffer, u32 *respbufferlen, 24 enum tpmDurationType to_t); 25 void tpmhw_set_timeouts(u32 timeouts[4], u32 durations[3]); 26 27 /* CRB driver */ 28 /* address of locality 0 (CRB) */ 29 #define TPM_CRB_BASE_ADDRESS 0xfed40000 30 31 #define CRB_REG(LOCTY, REG) \ 32 (void *)(TPM_CRB_BASE_ADDRESS + (LOCTY << 12) + REG) 33 34 /* hardware registers */ 35 #define CRB_REG_LOC_STATE 0x0 36 #define CRB_REG_LOC_CTRL 0x8 37 #define CRB_REG_LOC_STS 0xC 38 #define CRB_REG_INTF_ID 0x30 39 #define CRB_REG_CTRL_EXT 0x38 40 #define CRB_REG_CTRL_REQ 0x40 41 #define CRB_REG_CTRL_STS 0x44 42 #define CRB_REG_CTRL_CANCEL 0x48 43 #define CRB_REG_CTRL_START 0x4C 44 #define CRB_REG_INT_ENABLE 0x50 45 #define CRB_REG_INT_STS 0x54 46 #define CRB_REG_CTRL_CMD_SIZE 0x58 47 #define CRB_REG_CTRL_CMD_LADDR 0x5C 48 #define CRB_REG_CTRL_CMD_HADDR 0x60 49 #define CRB_REG_CTRL_RSP_SIZE 0x64 50 #define CRB_REG_CTRL_RSP_ADDR 0x68 51 #define CRB_REG_DATA_BUFFER 0x80 52 53 /* TIS driver */ 54 /* address of locality 0 (TIS) */ 55 #define TPM_TIS_BASE_ADDRESS 0xfed40000 56 57 #define TIS_REG(LOCTY, REG) \ 58 (void *)(TPM_TIS_BASE_ADDRESS + (LOCTY << 12) + REG) 59 60 /* hardware registers */ 61 #define TIS_REG_ACCESS 0x0 62 #define TIS_REG_INT_ENABLE 0x8 63 #define TIS_REG_INT_VECTOR 0xc 64 #define TIS_REG_INT_STATUS 0x10 65 #define TIS_REG_INTF_CAPABILITY 0x14 66 #define TIS_REG_STS 0x18 67 #define TIS_REG_DATA_FIFO 0x24 68 #define TIS_REG_IFACE_ID 0x30 69 #define TIS_REG_DID_VID 0xf00 70 #define TIS_REG_RID 0xf04 71 72 #define TIS_STS_VALID (1 << 7) /* 0x80 */ 73 #define TIS_STS_COMMAND_READY (1 << 6) /* 0x40 */ 74 #define TIS_STS_TPM_GO (1 << 5) /* 0x20 */ 75 #define TIS_STS_DATA_AVAILABLE (1 << 4) /* 0x10 */ 76 #define TIS_STS_EXPECT (1 << 3) /* 0x08 */ 77 #define TIS_STS_RESPONSE_RETRY (1 << 1) /* 0x02 */ 78 79 #define TIS_ACCESS_TPM_REG_VALID_STS (1 << 7) /* 0x80 */ 80 #define TIS_ACCESS_ACTIVE_LOCALITY (1 << 5) /* 0x20 */ 81 #define TIS_ACCESS_BEEN_SEIZED (1 << 4) /* 0x10 */ 82 #define TIS_ACCESS_SEIZE (1 << 3) /* 0x08 */ 83 #define TIS_ACCESS_PENDING_REQUEST (1 << 2) /* 0x04 */ 84 #define TIS_ACCESS_REQUEST_USE (1 << 1) /* 0x02 */ 85 #define TIS_ACCESS_TPM_ESTABLISHMENT (1 << 0) /* 0x01 */ 86 87 /* 88 * Default TIS timeouts used before getting them from the TPM itself 89 */ 90 #define TIS_DEFAULT_TIMEOUT_A 750000 /* us */ 91 #define TIS_DEFAULT_TIMEOUT_B 2000000 /* us */ 92 #define TIS_DEFAULT_TIMEOUT_C 750000 /* us */ 93 #define TIS_DEFAULT_TIMEOUT_D 750000 /* us */ 94 95 /* 96 * Default TIS 2 timeouts given in TPM Profile (TPT) Spec 97 */ 98 #define TIS2_DEFAULT_TIMEOUT_A 750000 /* us */ 99 #define TIS2_DEFAULT_TIMEOUT_B 2000000 /* us */ 100 #define TIS2_DEFAULT_TIMEOUT_C 200000 /* us */ 101 #define TIS2_DEFAULT_TIMEOUT_D 30000 /* us */ 102 103 enum tisTimeoutType { 104 TIS_TIMEOUT_TYPE_A = 0, 105 TIS_TIMEOUT_TYPE_B, 106 TIS_TIMEOUT_TYPE_C, 107 TIS_TIMEOUT_TYPE_D, 108 }; 109 110 /* 111 * Default command durations used before getting them from the 112 * TPM itself 113 */ 114 #define TPM_DEFAULT_DURATION_SHORT 2000000 /* us */ 115 #define TPM_DEFAULT_DURATION_MEDIUM 20000000 /* us */ 116 #define TPM_DEFAULT_DURATION_LONG 60000000 /* us */ 117 118 /* 119 * TPM 2 command durations; we set them to the timeout values 120 * given in TPM Profile (PTP) Specification; exceeding those 121 * timeout values indicates a faulty TPM. 122 */ 123 #define TPM2_DEFAULT_DURATION_SHORT 750000 /* us */ 124 #define TPM2_DEFAULT_DURATION_MEDIUM 2000000 /* us */ 125 #define TPM2_DEFAULT_DURATION_LONG 2000000 /* us */ 126 127 #endif /* TPM_DRIVERS_H */ 128