1 /* DO NOT EDIT THIS FILE 2 * Automatically generated by generate-def-headers.xsl 3 * DO NOT EDIT THIS FILE 4 */ 5 6 #ifndef __BFIN_DEF_ADSP_BF524_proc__ 7 #define __BFIN_DEF_ADSP_BF524_proc__ 8 9 #include "../mach-common/ADSP-EDN-core_def.h" 10 11 #include "ADSP-EDN-BF52x-extended_def.h" 12 13 #define PLL_CTL 0xFFC00000 /* PLL Control Register */ 14 #define PLL_DIV 0xFFC00004 /* PLL Divide Register */ 15 #define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */ 16 #define PLL_STAT 0xFFC0000C /* PLL Status Register */ 17 #define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */ 18 #define CHIPID 0xFFC00014 19 #define SWRST 0xFFC00100 /* Software Reset Register */ 20 #define SYSCR 0xFFC00104 /* System Configuration register */ 21 #define SRAM_BASE_ADDR 0xFFE00000 /* SRAM Base Address (Read Only) */ 22 #define DMEM_CONTROL 0xFFE00004 /* Data memory control */ 23 #define DCPLB_STATUS 0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */ 24 #define DCPLB_FAULT_ADDR 0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */ 25 #define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */ 26 #define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */ 27 #define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */ 28 #define DCPLB_ADDR3 0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */ 29 #define DCPLB_ADDR4 0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */ 30 #define DCPLB_ADDR5 0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */ 31 #define DCPLB_ADDR6 0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */ 32 #define DCPLB_ADDR7 0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */ 33 #define DCPLB_ADDR8 0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */ 34 #define DCPLB_ADDR9 0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */ 35 #define DCPLB_ADDR10 0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */ 36 #define DCPLB_ADDR11 0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */ 37 #define DCPLB_ADDR12 0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */ 38 #define DCPLB_ADDR13 0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */ 39 #define DCPLB_ADDR14 0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */ 40 #define DCPLB_ADDR15 0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */ 41 #define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */ 42 #define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */ 43 #define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */ 44 #define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */ 45 #define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */ 46 #define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */ 47 #define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */ 48 #define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */ 49 #define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */ 50 #define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */ 51 #define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */ 52 #define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */ 53 #define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */ 54 #define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */ 55 #define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */ 56 #define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */ 57 #define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */ 58 #define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */ 59 #define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */ 60 #define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */ 61 #define ICPLB_STATUS 0xFFE01008 /* Instruction Cache Programmable Look-Aside Buffer Status */ 62 #define ICPLB_FAULT_ADDR 0xFFE0100C /* Instruction Cache Programmable Look-Aside Buffer Fault Address */ 63 #define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */ 64 #define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */ 65 #define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */ 66 #define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */ 67 #define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */ 68 #define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */ 69 #define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */ 70 #define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */ 71 #define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */ 72 #define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */ 73 #define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */ 74 #define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */ 75 #define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */ 76 #define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */ 77 #define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */ 78 #define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */ 79 #define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */ 80 #define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */ 81 #define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */ 82 #define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */ 83 #define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */ 84 #define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */ 85 #define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */ 86 #define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */ 87 #define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */ 88 #define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */ 89 #define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */ 90 #define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */ 91 #define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */ 92 #define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */ 93 #define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */ 94 #define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */ 95 #define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */ 96 #define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */ 97 #define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */ 98 #define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */ 99 #define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */ 100 #define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */ 101 #define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */ 102 #define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */ 103 #define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */ 104 #define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */ 105 #define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */ 106 #define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */ 107 #define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */ 108 #define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */ 109 #define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */ 110 #define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */ 111 #define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */ 112 #define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */ 113 #define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */ 114 #define ILAT 0xFFE0210C /* Interrupt Latch Register */ 115 #define IMASK 0xFFE02104 /* Interrupt Mask Register */ 116 #define IPEND 0xFFE02108 /* Interrupt Pending Register */ 117 #define IPRIO 0xFFE02110 /* Interrupt Priority Register */ 118 #define TCNTL 0xFFE03000 /* Core Timer Control Register */ 119 #define TPERIOD 0xFFE03004 /* Core Timer Period Register */ 120 #define TSCALE 0xFFE03008 /* Core Timer Scale Register */ 121 #define TCOUNT 0xFFE0300C /* Core Timer Count Register */ 122 #define USB_FADDR 0xFFC03800 /* Function address register */ 123 #define USB_POWER 0xFFC03804 /* Power management register */ 124 #define USB_INTRTX 0xFFC03808 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */ 125 #define USB_INTRRX 0xFFC0380C /* Interrupt register for Rx endpoints 1 to 7 */ 126 #define USB_INTRTXE 0xFFC03810 /* Interrupt enable register for IntrTx */ 127 #define USB_INTRRXE 0xFFC03814 /* Interrupt enable register for IntrRx */ 128 #define USB_INTRUSB 0xFFC03818 /* Interrupt register for common USB interrupts */ 129 #define USB_INTRUSBE 0xFFC0381C /* Interrupt enable register for IntrUSB */ 130 #define USB_FRAME 0xFFC03820 /* USB frame number */ 131 #define USB_INDEX 0xFFC03824 /* Index register for selecting the indexed endpoint registers */ 132 #define USB_TESTMODE 0xFFC03828 /* Enabled USB 20 test modes */ 133 #define USB_GLOBINTR 0xFFC0382C /* Global Interrupt Mask register and Wakeup Exception Interrupt */ 134 #define USB_GLOBAL_CTL 0xFFC03830 /* Global Clock Control for the core */ 135 #define USB_TX_MAX_PACKET 0xFFC03840 /* Maximum packet size for Host Tx endpoint */ 136 #define USB_CSR0 0xFFC03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ 137 #define USB_TXCSR 0xFFC03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ 138 #define USB_RX_MAX_PACKET 0xFFC03848 /* Maximum packet size for Host Rx endpoint */ 139 #define USB_RXCSR 0xFFC0384C /* Control Status register for Host Rx endpoint */ 140 #define USB_COUNT0 0xFFC03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ 141 #define USB_RXCOUNT 0xFFC03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ 142 #define USB_TXTYPE 0xFFC03854 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */ 143 #define USB_NAKLIMIT0 0xFFC03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ 144 #define USB_TXINTERVAL 0xFFC03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ 145 #define USB_RXTYPE 0xFFC0385C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */ 146 #define USB_RXINTERVAL 0xFFC03860 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */ 147 #define USB_TXCOUNT 0xFFC03868 /* Number of bytes to be written to the selected endpoint Tx FIFO */ 148 #define USB_EP0_FIFO 0xFFC03880 /* Endpoint 0 FIFO */ 149 #define USB_EP1_FIFO 0xFFC03888 /* Endpoint 1 FIFO */ 150 #define USB_EP2_FIFO 0xFFC03890 /* Endpoint 2 FIFO */ 151 #define USB_EP3_FIFO 0xFFC03898 /* Endpoint 3 FIFO */ 152 #define USB_EP4_FIFO 0xFFC038A0 /* Endpoint 4 FIFO */ 153 #define USB_EP5_FIFO 0xFFC038A8 /* Endpoint 5 FIFO */ 154 #define USB_EP6_FIFO 0xFFC038B0 /* Endpoint 6 FIFO */ 155 #define USB_EP7_FIFO 0xFFC038B8 /* Endpoint 7 FIFO */ 156 #define USB_OTG_DEV_CTL 0xFFC03900 /* OTG Device Control Register */ 157 #define USB_OTG_VBUS_IRQ 0xFFC03904 /* OTG VBUS Control Interrupts */ 158 #define USB_OTG_VBUS_MASK 0xFFC03908 /* VBUS Control Interrupt Enable */ 159 #define USB_LINKINFO 0xFFC03948 /* Enables programming of some PHY-side delays */ 160 #define USB_VPLEN 0xFFC0394C /* Determines duration of VBUS pulse for VBUS charging */ 161 #define USB_HS_EOF1 0xFFC03950 /* Time buffer for High-Speed transactions */ 162 #define USB_FS_EOF1 0xFFC03954 /* Time buffer for Full-Speed transactions */ 163 #define USB_LS_EOF1 0xFFC03958 /* Time buffer for Low-Speed transactions */ 164 #define USB_APHY_CNTRL 0xFFC039E0 /* Register that increases visibility of Analog PHY */ 165 #define USB_APHY_CALIB 0xFFC039E4 /* Register used to set some calibration values */ 166 #define USB_APHY_CNTRL2 0xFFC039E8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */ 167 #define USB_PHY_TEST 0xFFC039EC /* Used for reducing simulation time and simplifies FIFO testability */ 168 #define USB_PLLOSC_CTRL 0xFFC039F0 /* Used to program different parameters for USB PLL and Oscillator */ 169 #define USB_SRP_CLKDIV 0xFFC039F4 /* Used to program clock divide value for the clock fed to the SRP detection logic */ 170 #define USB_EP_NI0_TXMAXP 0xFFC03A00 /* Maximum packet size for Host Tx endpoint0 */ 171 #define USB_EP_NI0_TXCSR 0xFFC03A04 /* Control Status register for endpoint 0 */ 172 #define USB_EP_NI0_RXMAXP 0xFFC03A08 /* Maximum packet size for Host Rx endpoint0 */ 173 #define USB_EP_NI0_RXCSR 0xFFC03A0C /* Control Status register for Host Rx endpoint0 */ 174 #define USB_EP_NI0_RXCOUNT 0xFFC03A10 /* Number of bytes received in endpoint 0 FIFO */ 175 #define USB_EP_NI0_TXTYPE 0xFFC03A14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */ 176 #define USB_EP_NI0_TXINTERVAL 0xFFC03A18 /* Sets the NAK response timeout on Endpoint 0 */ 177 #define USB_EP_NI0_RXTYPE 0xFFC03A1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */ 178 #define USB_EP_NI0_RXINTERVAL 0xFFC03A20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */ 179 #define USB_EP_NI0_TXCOUNT 0xFFC03A28 /* Number of bytes to be written to the endpoint0 Tx FIFO */ 180 #define USB_EP_NI1_TXMAXP 0xFFC03A40 /* Maximum packet size for Host Tx endpoint1 */ 181 #define USB_EP_NI1_TXCSR 0xFFC03A44 /* Control Status register for endpoint1 */ 182 #define USB_EP_NI1_RXMAXP 0xFFC03A48 /* Maximum packet size for Host Rx endpoint1 */ 183 #define USB_EP_NI1_RXCSR 0xFFC03A4C /* Control Status register for Host Rx endpoint1 */ 184 #define USB_EP_NI1_RXCOUNT 0xFFC03A50 /* Number of bytes received in endpoint1 FIFO */ 185 #define USB_EP_NI1_TXTYPE 0xFFC03A54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */ 186 #define USB_EP_NI1_TXINTERVAL 0xFFC03A58 /* Sets the NAK response timeout on Endpoint1 */ 187 #define USB_EP_NI1_RXTYPE 0xFFC03A5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */ 188 #define USB_EP_NI1_RXINTERVAL 0xFFC03A60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */ 189 #define USB_EP_NI1_TXCOUNT 0xFFC03A68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */ 190 #define USB_EP_NI2_TXMAXP 0xFFC03A80 /* Maximum packet size for Host Tx endpoint2 */ 191 #define USB_EP_NI2_TXCSR 0xFFC03A84 /* Control Status register for endpoint2 */ 192 #define USB_EP_NI2_RXMAXP 0xFFC03A88 /* Maximum packet size for Host Rx endpoint2 */ 193 #define USB_EP_NI2_RXCSR 0xFFC03A8C /* Control Status register for Host Rx endpoint2 */ 194 #define USB_EP_NI2_RXCOUNT 0xFFC03A90 /* Number of bytes received in endpoint2 FIFO */ 195 #define USB_EP_NI2_TXTYPE 0xFFC03A94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */ 196 #define USB_EP_NI2_TXINTERVAL 0xFFC03A98 /* Sets the NAK response timeout on Endpoint2 */ 197 #define USB_EP_NI2_RXTYPE 0xFFC03A9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */ 198 #define USB_EP_NI2_RXINTERVAL 0xFFC03AA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */ 199 #define USB_EP_NI2_TXCOUNT 0xFFC03AA8 /* Number of bytes to be written to the endpoint2 Tx FIFO */ 200 #define USB_EP_NI3_TXMAXP 0xFFC03AC0 /* Maximum packet size for Host Tx endpoint3 */ 201 #define USB_EP_NI3_TXCSR 0xFFC03AC4 /* Control Status register for endpoint3 */ 202 #define USB_EP_NI3_RXMAXP 0xFFC03AC8 /* Maximum packet size for Host Rx endpoint3 */ 203 #define USB_EP_NI3_RXCSR 0xFFC03ACC /* Control Status register for Host Rx endpoint3 */ 204 #define USB_EP_NI3_RXCOUNT 0xFFC03AD0 /* Number of bytes received in endpoint3 FIFO */ 205 #define USB_EP_NI3_TXTYPE 0xFFC03AD4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */ 206 #define USB_EP_NI3_TXINTERVAL 0xFFC03AD8 /* Sets the NAK response timeout on Endpoint3 */ 207 #define USB_EP_NI3_RXTYPE 0xFFC03ADC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */ 208 #define USB_EP_NI3_RXINTERVAL 0xFFC03AE0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */ 209 #define USB_EP_NI3_TXCOUNT 0xFFC03AE8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */ 210 #define USB_EP_NI4_TXMAXP 0xFFC03B00 /* Maximum packet size for Host Tx endpoint4 */ 211 #define USB_EP_NI4_TXCSR 0xFFC03B04 /* Control Status register for endpoint4 */ 212 #define USB_EP_NI4_RXMAXP 0xFFC03B08 /* Maximum packet size for Host Rx endpoint4 */ 213 #define USB_EP_NI4_RXCSR 0xFFC03B0C /* Control Status register for Host Rx endpoint4 */ 214 #define USB_EP_NI4_RXCOUNT 0xFFC03B10 /* Number of bytes received in endpoint4 FIFO */ 215 #define USB_EP_NI4_TXTYPE 0xFFC03B14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */ 216 #define USB_EP_NI4_TXINTERVAL 0xFFC03B18 /* Sets the NAK response timeout on Endpoint4 */ 217 #define USB_EP_NI4_RXTYPE 0xFFC03B1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */ 218 #define USB_EP_NI4_RXINTERVAL 0xFFC03B20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */ 219 #define USB_EP_NI4_TXCOUNT 0xFFC03B28 /* Number of bytes to be written to the endpoint4 Tx FIFO */ 220 #define USB_EP_NI5_TXMAXP 0xFFC03B40 /* Maximum packet size for Host Tx endpoint5 */ 221 #define USB_EP_NI5_TXCSR 0xFFC03B44 /* Control Status register for endpoint5 */ 222 #define USB_EP_NI5_RXMAXP 0xFFC03B48 /* Maximum packet size for Host Rx endpoint5 */ 223 #define USB_EP_NI5_RXCSR 0xFFC03B4C /* Control Status register for Host Rx endpoint5 */ 224 #define USB_EP_NI5_RXCOUNT 0xFFC03B50 /* Number of bytes received in endpoint5 FIFO */ 225 #define USB_EP_NI5_TXTYPE 0xFFC03B54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */ 226 #define USB_EP_NI5_TXINTERVAL 0xFFC03B58 /* Sets the NAK response timeout on Endpoint5 */ 227 #define USB_EP_NI5_RXTYPE 0xFFC03B5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */ 228 #define USB_EP_NI5_RXINTERVAL 0xFFC03B60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */ 229 #define USB_EP_NI5_TXCOUNT 0xFFC03B68 /* Number of bytes to be written to the endpoint5 Tx FIFO */ 230 #define USB_EP_NI6_TXMAXP 0xFFC03B80 /* Maximum packet size for Host Tx endpoint6 */ 231 #define USB_EP_NI6_TXCSR 0xFFC03B84 /* Control Status register for endpoint6 */ 232 #define USB_EP_NI6_RXMAXP 0xFFC03B88 /* Maximum packet size for Host Rx endpoint6 */ 233 #define USB_EP_NI6_RXCSR 0xFFC03B8C /* Control Status register for Host Rx endpoint6 */ 234 #define USB_EP_NI6_RXCOUNT 0xFFC03B90 /* Number of bytes received in endpoint6 FIFO */ 235 #define USB_EP_NI6_TXTYPE 0xFFC03B94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */ 236 #define USB_EP_NI6_TXINTERVAL 0xFFC03B98 /* Sets the NAK response timeout on Endpoint6 */ 237 #define USB_EP_NI6_RXTYPE 0xFFC03B9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */ 238 #define USB_EP_NI6_RXINTERVAL 0xFFC03BA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */ 239 #define USB_EP_NI6_TXCOUNT 0xFFC03BA8 /* Number of bytes to be written to the endpoint6 Tx FIFO */ 240 #define USB_EP_NI7_TXMAXP 0xFFC03BC0 /* Maximum packet size for Host Tx endpoint7 */ 241 #define USB_EP_NI7_TXCSR 0xFFC03BC4 /* Control Status register for endpoint7 */ 242 #define USB_EP_NI7_RXMAXP 0xFFC03BC8 /* Maximum packet size for Host Rx endpoint7 */ 243 #define USB_EP_NI7_RXCSR 0xFFC03BCC /* Control Status register for Host Rx endpoint7 */ 244 #define USB_EP_NI7_RXCOUNT 0xFFC03BD0 /* Number of bytes received in endpoint7 FIFO */ 245 #define USB_EP_NI7_TXTYPE 0xFFC03BD4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */ 246 #define USB_EP_NI7_TXINTERVAL 0xFFC03BD8 /* Sets the NAK response timeout on Endpoint7 */ 247 #define USB_EP_NI7_RXTYPE 0xFFC03BDC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */ 248 #define USB_EP_NI7_RXINTERVAL 0xFFC03BF0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */ 249 #define USB_EP_NI7_TXCOUNT 0xFFC03BF8 /* Number of bytes to be written to the endpoint7 Tx FIFO */ 250 #define USB_DMA_INTERRUPT 0xFFC03C00 /* Indicates pending interrupts for the DMA channels */ 251 #define USB_DMA0_CONTROL 0xFFC03C04 /* DMA master channel 0 configuration */ 252 #define USB_DMA0_ADDRLOW 0xFFC03C08 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */ 253 #define USB_DMA0_ADDRHIGH 0xFFC03C0C /* Upper 16-bits of memory source/destination address for DMA master channel 0 */ 254 #define USB_DMA0_COUNTLOW 0xFFC03C10 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */ 255 #define USB_DMA0_COUNTHIGH 0xFFC03C14 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */ 256 #define USB_DMA1_CONTROL 0xFFC03C24 /* DMA master channel 1 configuration */ 257 #define USB_DMA1_ADDRLOW 0xFFC03C28 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */ 258 #define USB_DMA1_ADDRHIGH 0xFFC03C2C /* Upper 16-bits of memory source/destination address for DMA master channel 1 */ 259 #define USB_DMA1_COUNTLOW 0xFFC03C30 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */ 260 #define USB_DMA1_COUNTHIGH 0xFFC03C34 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */ 261 #define USB_DMA2_CONTROL 0xFFC03C44 /* DMA master channel 2 configuration */ 262 #define USB_DMA2_ADDRLOW 0xFFC03C48 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */ 263 #define USB_DMA2_ADDRHIGH 0xFFC03C4C /* Upper 16-bits of memory source/destination address for DMA master channel 2 */ 264 #define USB_DMA2_COUNTLOW 0xFFC03C50 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */ 265 #define USB_DMA2_COUNTHIGH 0xFFC03C54 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */ 266 #define USB_DMA3_CONTROL 0xFFC03C64 /* DMA master channel 3 configuration */ 267 #define USB_DMA3_ADDRLOW 0xFFC03C68 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */ 268 #define USB_DMA3_ADDRHIGH 0xFFC03C6C /* Upper 16-bits of memory source/destination address for DMA master channel 3 */ 269 #define USB_DMA3_COUNTLOW 0xFFC03C70 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */ 270 #define USB_DMA3_COUNTHIGH 0xFFC03C74 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */ 271 #define USB_DMA4_CONTROL 0xFFC03C84 /* DMA master channel 4 configuration */ 272 #define USB_DMA4_ADDRLOW 0xFFC03C88 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */ 273 #define USB_DMA4_ADDRHIGH 0xFFC03C8C /* Upper 16-bits of memory source/destination address for DMA master channel 4 */ 274 #define USB_DMA4_COUNTLOW 0xFFC03C90 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */ 275 #define USB_DMA4_COUNTHIGH 0xFFC03C94 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */ 276 #define USB_DMA5_CONTROL 0xFFC03CA4 /* DMA master channel 5 configuration */ 277 #define USB_DMA5_ADDRLOW 0xFFC03CA8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */ 278 #define USB_DMA5_ADDRHIGH 0xFFC03CAC /* Upper 16-bits of memory source/destination address for DMA master channel 5 */ 279 #define USB_DMA5_COUNTLOW 0xFFC03CB0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */ 280 #define USB_DMA5_COUNTHIGH 0xFFC03CB4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */ 281 #define USB_DMA6_CONTROL 0xFFC03CC4 /* DMA master channel 6 configuration */ 282 #define USB_DMA6_ADDRLOW 0xFFC03CC8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */ 283 #define USB_DMA6_ADDRHIGH 0xFFC03CCC /* Upper 16-bits of memory source/destination address for DMA master channel 6 */ 284 #define USB_DMA6_COUNTLOW 0xFFC03CD0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */ 285 #define USB_DMA6_COUNTHIGH 0xFFC03CD4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */ 286 #define USB_DMA7_CONTROL 0xFFC03CE4 /* DMA master channel 7 configuration */ 287 #define USB_DMA7_ADDRLOW 0xFFC03CE8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */ 288 #define USB_DMA7_ADDRHIGH 0xFFC03CEC /* Upper 16-bits of memory source/destination address for DMA master channel 7 */ 289 #define USB_DMA7_COUNTLOW 0xFFC03CF0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */ 290 #define USB_DMA7_COUNTHIGH 0xFFC03CF4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */ 291 292 #endif /* __BFIN_DEF_ADSP_BF524_proc__ */ 293