1AVR32 Port multiplexer configuration 2==================================== 3 4On AVR32 chips, most external I/O pins are routed through a port 5multiplexer. There are currently two kinds of port multiplexer 6hardware around with different register interfaces: 7 8 * PIO (AT32AP700x; this is also used on ARM AT91 chips) 9 * GPIO (all other AVR32 chips) 10 11The "PIO" variant supports multiplexing up to two peripherals per pin 12in addition to GPIO (software control). Each pin has configurable 13pull-up, glitch filter, interrupt and multi-drive capabilities. 14 15The "GPIO" variant supports multiplexing up to four peripherals per 16pin in addition to GPIO. Each pin has configurable 17pull-up/pull-down/buskeeper, glitch filter, interrupt, open-drain and 18schmitt-trigger capabilities, as well as configurable drive strength 19and slew rate control. 20 21Both controllers are configured using the same API, but the functions 22may accept different values for some parameters depending on the 23actual portmux implementation, and some parameters may be ignored by 24one of the implementation (e.g. the "PIO" implementation will ignore 25the drive strength flags since the hardware doesn't support 26configurable drive strength.) 27 28Selecting the portmux implementation 29------------------------------------ 30Since u-boot is lacking a Kconfig-style configuration engine, the 31portmux implementation must be selected manually by defining one of 32the following symbols: 33 34 CONFIG_PORTMUX_PIO 35 CONFIG_PORTMUX_GPIO 36 37depending on which implementation the chip in question uses. 38 39Identifying pins 40---------------- 41The portmux configuration functions described below identify the pins 42to act on based on two parameters: A "port" (i.e. a block of pins 43that somehow belong together) and a pin mask. Both are defined in an 44implementation-specific manner. 45 46The available ports are defined on the form 47 48 #define PORTMUX_PORT_A (something) 49 50where "A" matches the identifier given in the chip's data sheet, and 51"something" is whatever the portmux implementation needs to identify 52the port (usually a memory address). 53 54The pin mask is a bitmask where each '1' bit indicates a pin to apply 55the current operation to. The width of the bitmask may vary from port 56to port, but it is never wider than 32 bits (which is the width of 57'unsigned long' on avr32). 58 59Selecting functions 60------------------- 61Each pin can either be assigned to one of a predefined set of on-chip 62peripherals, or it can be set up to be controlled by software. For the 63former case, the portmux implementation defines an enum containing all 64the possible peripheral functions that can be selected. For example, 65the PIO implementation, which allows multiplexing two peripherals per 66pin, defines it like this: 67 68 enum portmux_function { 69 PORTMUX_FUNC_A, 70 PORTMUX_FUNC_B, 71 }; 72 73To configure a set of pins to be connected to a given peripheral 74function, the following function is used. 75 76 void portmux_select_peripheral(void *port, unsigned long pin_mask, 77 enum portmux_function func, unsigned long flags); 78 79To configure a set of pins to be controlled by software (GPIO), the 80following function is used. In this case, no "function" argument is 81required since "GPIO" is a function in its own right. 82 83 void portmux_select_gpio(void *port, unsigned int pin_mask, 84 unsigned long flags); 85 86Both of these functions take a "flags" parameter which may be used to 87alter the default configuration of the pin. This is a bitmask of 88various flags defined in an implementation-specific way, but the names 89of the flags are the same on all implementations. 90 91 PORTMUX_DIR_OUTPUT 92 PORTMUX_DIR_INPUT 93 94These mutually-exlusive flags configure the initial direction of the 95pins. PORTMUX_DIR_OUTPUT means that the pins are driven by the CPU, 96while PORTMUX_DIR_INPUT means that the pins are tristated by the CPU. 97These flags are ignored by portmux_select_peripheral(). 98 99 PORTMUX_INIT_HIGH 100 PORTMUX_INIT_LOW 101 102These mutually-exclusive flags configure the initial state of the 103pins: High (Vdd) or low (Vss). They are only effective when 104portmux_select_gpio() is called with the PORTMUX_DIR_OUTPUT flag set. 105 106 PORTMUX_PULL_UP 107 PORTMUX_PULL_DOWN 108 PORTMUX_BUSKEEPER 109 110These mutually-exclusive flags are used to enable any on-chip CMOS 111resistors connected to the pins. PORTMUX_PULL_UP causes the pins to be 112pulled up to Vdd, PORTMUX_PULL_DOWN causes the pins to be pulled down 113to Vss, and PORTMUX_BUSKEEPER will keep the pins in whatever state 114they were left in by whatever was driving them last. If none of the 115flags are specified, the pins are left floating if no one are driving 116them; this is only recommended for always-output pins (e.g. extern 117address and control lines driven by the CPU.) 118 119Note that the "PIO" implementation will silently ignore the 120PORTMUX_PULL_DOWN flag and interpret PORTMUX_BUSKEEPER as 121PORTMUX_PULL_UP. 122 123 PORTMUX_DRIVE_MIN 124 PORTMUX_DRIVE_LOW 125 PORTMUX_DRIVE_HIGH 126 PORTMUX_DRIVE_MAX 127 128These mutually-exlusive flags determine the drive strength of the 129pins. PORTMUX_DRIVE_MIN will give low power-consumption, but may cause 130corruption of high-speed signals. PORTMUX_DRIVE_MAX will give high 131power-consumption, but may be necessary on pins toggling at very high 132speeds. PORTMUX_DRIVE_LOW and PORTMUX_DRIVE_HIGH specify something in 133between the other two. 134 135Note that setting the drive strength too high may cause excessive 136overshoot and EMI problems, which may in turn cause signal corruption. 137Also note that the "PIO" implementation will silently ignore these 138flags. 139 140 PORTMUX_OPEN_DRAIN 141 142This flag will configure the pins as "open drain", i.e. setting the 143pin state to 0 will drive it low, while setting it to 1 will leave it 144floating (or, in most cases, let it be pulled high by an internal or 145external pull-up resistor.) In the data sheet for chips using the 146"PIO" variant, this mode is called "multi-driver". 147 148Enabling specific peripherals 149----------------------------- 150In addition to the above functions, each chip provides a set of 151functions for setting up the port multiplexer to use a given 152peripheral. The following are some of the functions available. 153 154All the functions below take a "drive_strength" parameter, which must 155be one of the PORTMUX_DRIVE_x flags specified above. Any other 156portmux flags will be silently filtered out. 157 158To set up the External Bus Interface (EBI), call 159 160 void portmux_enable_ebi(unsigned int bus_width, 161 unsigned long flags, unsigned long drive_strength) 162 163where "bus_width" must be either 16 or 32. "flags" can be any 164combination of the following flags. 165 166 PORTMUX_EBI_CS(x) /* Enable chip select x */ 167 PORTMUX_EBI_NAND /* Enable NAND flash interface */ 168 PORTMUX_EBI_CF(x) /* Enable CompactFlash interface x */ 169 PORTMUX_EBI_NWAIT /* Enable NWAIT signal */ 170 171To set up a USART, call 172 173 void portmux_enable_usartX(unsigned long drive_strength); 174 175where X is replaced by the USART instance to be configured. 176 177To set up an ethernet MAC: 178 179 void portmux_enable_macbX(unsigned long flags, 180 unsigned long drive_strength); 181 182where X is replaced by the MACB instance to be configured. "flags" can 183be any combination of the following flags. 184 185 PORTMUX_MACB_RMII /* Just set up the RMII interface */ 186 PORTMUX_MACB_MII /* Set up full MII interface */ 187 PORTMUX_MACB_SPEED /* Enable the SPEED pin */ 188 189To set up the MMC controller: 190 191 void portmux_enable_mmci(unsigned long slot, unsigned long flags 192 unsigned long drive_strength); 193 194where "slot" identifies which of the alternative SD card slots to 195enable. "flags" can be any combination of the following flags: 196 197 PORTMUX_MMCI_4BIT /* Enable 4-bit SD card interface */ 198 PORTMUX_MMCI_8BIT /* Enable 8-bit MMC+ interface */ 199 PORTMUX_MMCI_EXT_PULLUP /* Board has external pull-ups */ 200 201To set up a SPI controller: 202 203 void portmux_enable_spiX(unsigned long cs_mask, 204 unsigned long drive_strength); 205 206where X is replaced by the SPI instance to be configured. "cs_mask" is 207a 4-bit bitmask specifying which of the four standard chip select 208lines to set up as GPIOs. 209