1 /* 2 * Copyright (C) Freescale Semiconductor, Inc. 2006. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 /* 23 * mpc8313epb board configuration file 24 */ 25 26 #ifndef __CONFIG_H 27 #define __CONFIG_H 28 29 /* 30 * High Level Configuration Options 31 */ 32 #define CONFIG_E300 1 33 #define CONFIG_MPC83xx 1 34 #define CONFIG_MPC831x 1 35 #define CONFIG_MPC8313 1 36 #define CONFIG_MPC8313ERDB 1 37 38 #define CONFIG_PCI 39 40 #define CONFIG_MISC_INIT_R 41 42 /* 43 * On-board devices 44 * 45 * TSEC1 is VSC switch 46 * TSEC2 is SoC TSEC 47 */ 48 #define CONFIG_VSC7385_ENET 49 #define CONFIG_TSEC2 50 51 #ifdef CONFIG_SYS_66MHZ 52 #define CONFIG_83XX_CLKIN 66666667 /* in Hz */ 53 #elif defined(CONFIG_SYS_33MHZ) 54 #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 55 #else 56 #error Unknown oscillator frequency. 57 #endif 58 59 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 60 61 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ 62 63 #define CONFIG_SYS_IMMR 0xE0000000 64 65 #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) 66 #define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR 67 #endif 68 69 #define CONFIG_SYS_MEMTEST_START 0x00001000 70 #define CONFIG_SYS_MEMTEST_END 0x07f00000 71 72 /* Early revs of this board will lock up hard when attempting 73 * to access the PMC registers, unless a JTAG debugger is 74 * connected, or some resistor modifications are made. 75 */ 76 #define CONFIG_SYS_8313ERDB_BROKEN_PMC 1 77 78 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 79 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 80 81 /* 82 * Device configurations 83 */ 84 85 /* Vitesse 7385 */ 86 87 #ifdef CONFIG_VSC7385_ENET 88 89 #define CONFIG_TSEC1 90 91 /* The flash address and size of the VSC7385 firmware image */ 92 #define CONFIG_VSC7385_IMAGE 0xFE7FE000 93 #define CONFIG_VSC7385_IMAGE_SIZE 8192 94 95 #endif 96 97 /* 98 * DDR Setup 99 */ 100 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ 101 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 102 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 103 104 /* 105 * Manually set up DDR parameters, as this board does not 106 * seem to have the SPD connected to I2C. 107 */ 108 #define CONFIG_SYS_DDR_SIZE 128 /* MB */ 109 #define CONFIG_SYS_DDR_CONFIG ( CSCONFIG_EN \ 110 | 0x00010000 /* TODO */ \ 111 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 ) 112 /* 0x80010102 */ 113 114 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 115 #define CONFIG_SYS_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \ 116 | ( 0 << TIMING_CFG0_WRT_SHIFT ) \ 117 | ( 0 << TIMING_CFG0_RRT_SHIFT ) \ 118 | ( 0 << TIMING_CFG0_WWT_SHIFT ) \ 119 | ( 2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \ 120 | ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \ 121 | ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \ 122 | ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) ) 123 /* 0x00220802 */ 124 #define CONFIG_SYS_DDR_TIMING_1 ( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \ 125 | ( 8 << TIMING_CFG1_ACTTOPRE_SHIFT ) \ 126 | ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \ 127 | ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \ 128 | (10 << TIMING_CFG1_REFREC_SHIFT ) \ 129 | ( 3 << TIMING_CFG1_WRREC_SHIFT ) \ 130 | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \ 131 | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) ) 132 /* 0x3835a322 */ 133 #define CONFIG_SYS_DDR_TIMING_2 ( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \ 134 | ( 5 << TIMING_CFG2_CPO_SHIFT ) \ 135 | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \ 136 | ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \ 137 | ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \ 138 | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \ 139 | ( 6 << TIMING_CFG2_FOUR_ACT_SHIFT) ) 140 /* 0x129048c6 */ /* P9-45,may need tuning */ 141 #define CONFIG_SYS_DDR_INTERVAL ( ( 1296 << SDRAM_INTERVAL_REFINT_SHIFT ) \ 142 | ( 1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) ) 143 /* 0x05100500 */ 144 #if defined(CONFIG_DDR_2T_TIMING) 145 #define CONFIG_SYS_SDRAM_CFG ( SDRAM_CFG_SREN \ 146 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 147 | SDRAM_CFG_2T_EN \ 148 | SDRAM_CFG_DBW_32 ) 149 #else 150 #define CONFIG_SYS_SDRAM_CFG ( SDRAM_CFG_SREN \ 151 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 152 | SDRAM_CFG_32_BE ) 153 /* 0x43080000 */ 154 #endif 155 #define CONFIG_SYS_SDRAM_CFG2 0x00401000 156 /* set burst length to 8 for 32-bit data path */ 157 #define CONFIG_SYS_DDR_MODE ( ( 0x4448 << SDRAM_MODE_ESD_SHIFT ) \ 158 | ( 0x0632 << SDRAM_MODE_SD_SHIFT ) ) 159 /* 0x44480632 */ 160 #define CONFIG_SYS_DDR_MODE_2 0x8000C000 161 162 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 163 /*0x02000000*/ 164 #define CONFIG_SYS_DDRCDR_VALUE ( DDRCDR_EN \ 165 | DDRCDR_PZ_NOMZ \ 166 | DDRCDR_NZ_NOMZ \ 167 | DDRCDR_M_ODR ) 168 169 /* 170 * FLASH on the Local Bus 171 */ 172 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 173 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 174 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ 175 #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */ 176 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 177 #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */ 178 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */ 179 180 #define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE | /* flash Base address */ \ 181 (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ 182 BR_V) /* valid */ 183 #define CONFIG_SYS_NOR_OR_PRELIM ( 0xFF800000 /* 8 MByte */ \ 184 | OR_GPCM_XACS \ 185 | OR_GPCM_SCY_9 \ 186 | OR_GPCM_EHTR \ 187 | OR_GPCM_EAD ) 188 /* 0xFF006FF7 TODO SLOW 16 MB flash size */ 189 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* window base at flash base */ 190 #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000017 /* 16 MB window size */ 191 192 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 193 #define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */ 194 195 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 196 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 197 198 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ 199 200 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && !defined(CONFIG_NAND_SPL) 201 #define CONFIG_SYS_RAMBOOT 202 #endif 203 204 #define CONFIG_SYS_INIT_RAM_LOCK 1 205 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ 206 #define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM*/ 207 208 #define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */ 209 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 210 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 211 212 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ 213 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 214 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 215 216 /* 217 * Local Bus LCRR and LBCR regs 218 */ 219 #define CONFIG_SYS_LCRR_EADC LCRR_EADC_1 220 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 221 #define CONFIG_SYS_LBC_LBCR ( 0x00040000 /* TODO */ \ 222 | (0xFF << LBCR_BMT_SHIFT) \ 223 | 0xF ) /* 0x0004ff0f */ 224 225 #define CONFIG_SYS_LBC_MRTPR 0x20000000 /*TODO */ /* LB refresh timer prescal, 266MHz/32 */ 226 227 /* drivers/mtd/nand/nand.c */ 228 #ifdef CONFIG_NAND_SPL 229 #define CONFIG_SYS_NAND_BASE 0xFFF00000 230 #else 231 #define CONFIG_SYS_NAND_BASE 0xE2800000 232 #endif 233 234 #define CONFIG_SYS_MAX_NAND_DEVICE 1 235 #define CONFIG_MTD_NAND_VERIFY_WRITE 236 #define CONFIG_CMD_NAND 1 237 #define CONFIG_NAND_FSL_ELBC 1 238 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384 239 240 #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) 241 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000 242 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100 243 #define CONFIG_SYS_NAND_U_BOOT_OFFS 16384 244 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 245 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000) 246 247 #define CONFIG_SYS_NAND_BR_PRELIM ( CONFIG_SYS_NAND_BASE \ 248 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 249 | BR_PS_8 /* Port Size = 8 bit */ \ 250 | BR_MS_FCM /* MSEL = FCM */ \ 251 | BR_V ) /* valid */ 252 #define CONFIG_SYS_NAND_OR_PRELIM ( 0xFFFF8000 /* length 32K */ \ 253 | OR_FCM_CSCT \ 254 | OR_FCM_CST \ 255 | OR_FCM_CHT \ 256 | OR_FCM_SCY_1 \ 257 | OR_FCM_TRLX \ 258 | OR_FCM_EHTR ) 259 /* 0xFFFF8396 */ 260 261 #ifdef CONFIG_NAND_U_BOOT 262 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM 263 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM 264 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM 265 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM 266 #else 267 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM 268 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM 269 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM 270 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM 271 #endif 272 273 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE 274 #define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* 32KB */ 275 276 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM 277 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM 278 279 /* local bus read write buffer mapping */ 280 #define CONFIG_SYS_BR3_PRELIM 0xFA000801 /* map at 0xFA000000 */ 281 #define CONFIG_SYS_OR3_PRELIM 0xFFFF8FF7 /* 32kB */ 282 #define CONFIG_SYS_LBLAWBAR3_PRELIM 0xFA000000 283 #define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000000E /* 32KB */ 284 285 /* Vitesse 7385 */ 286 287 #define CONFIG_SYS_VSC7385_BASE 0xF0000000 288 289 #ifdef CONFIG_VSC7385_ENET 290 291 #define CONFIG_SYS_BR2_PRELIM 0xf0000801 /* VSC7385 Base address */ 292 #define CONFIG_SYS_OR2_PRELIM 0xfffe09ff /* VSC7385, 128K bytes*/ 293 #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE/* Access window base at VSC7385 base */ 294 #define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000010 /* Access window size 128K */ 295 296 #endif 297 298 /* pass open firmware flat tree */ 299 #define CONFIG_OF_LIBFDT 1 300 #define CONFIG_OF_BOARD_SETUP 1 301 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 302 303 /* 304 * Serial Port 305 */ 306 #define CONFIG_CONS_INDEX 1 307 #define CONFIG_SYS_NS16550 308 #define CONFIG_SYS_NS16550_SERIAL 309 #define CONFIG_SYS_NS16550_REG_SIZE 1 310 311 #define CONFIG_SYS_BAUDRATE_TABLE \ 312 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 313 314 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 315 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 316 317 /* Use the HUSH parser */ 318 #define CONFIG_SYS_HUSH_PARSER 319 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 320 321 /* I2C */ 322 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 323 #define CONFIG_FSL_I2C 324 #define CONFIG_I2C_MULTI_BUS 325 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 326 #define CONFIG_SYS_I2C_SLAVE 0x7F 327 #define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ 328 #define CONFIG_SYS_I2C_OFFSET 0x3000 329 #define CONFIG_SYS_I2C2_OFFSET 0x3100 330 331 /* 332 * General PCI 333 * Addresses are mapped 1-1. 334 */ 335 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 336 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 337 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 338 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 339 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 340 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 341 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 342 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 343 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 344 345 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 346 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 347 348 /* 349 * TSEC 350 */ 351 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 352 353 #define CONFIG_NET_MULTI 354 #define CONFIG_GMII /* MII PHY management */ 355 356 #ifdef CONFIG_TSEC1 357 #define CONFIG_HAS_ETH0 358 #define CONFIG_TSEC1_NAME "TSEC0" 359 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 360 #define TSEC1_PHY_ADDR 0x1c 361 #define TSEC1_FLAGS TSEC_GIGABIT 362 #define TSEC1_PHYIDX 0 363 #endif 364 365 #ifdef CONFIG_TSEC2 366 #define CONFIG_HAS_ETH1 367 #define CONFIG_TSEC2_NAME "TSEC1" 368 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 369 #define TSEC2_PHY_ADDR 4 370 #define TSEC2_FLAGS TSEC_GIGABIT 371 #define TSEC2_PHYIDX 0 372 #endif 373 374 375 /* Options are: TSEC[0-1] */ 376 #define CONFIG_ETHPRIME "TSEC1" 377 378 /* 379 * Configure on-board RTC 380 */ 381 #define CONFIG_RTC_DS1337 382 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 383 384 /* 385 * Environment 386 */ 387 #if defined(CONFIG_NAND_U_BOOT) 388 #define CONFIG_ENV_IS_IN_NAND 1 389 #define CONFIG_ENV_OFFSET (512 * 1024) 390 #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 391 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 392 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 393 #define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4) 394 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) 395 #elif !defined(CONFIG_SYS_RAMBOOT) 396 #define CONFIG_ENV_IS_IN_FLASH 1 397 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 398 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 399 #define CONFIG_ENV_SIZE 0x2000 400 401 /* Address and size of Redundant Environment Sector */ 402 #else 403 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 404 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 405 #define CONFIG_ENV_SIZE 0x2000 406 #endif 407 408 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 409 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 410 411 /* 412 * BOOTP options 413 */ 414 #define CONFIG_BOOTP_BOOTFILESIZE 415 #define CONFIG_BOOTP_BOOTPATH 416 #define CONFIG_BOOTP_GATEWAY 417 #define CONFIG_BOOTP_HOSTNAME 418 419 420 /* 421 * Command line configuration. 422 */ 423 #include <config_cmd_default.h> 424 425 #define CONFIG_CMD_PING 426 #define CONFIG_CMD_DHCP 427 #define CONFIG_CMD_I2C 428 #define CONFIG_CMD_MII 429 #define CONFIG_CMD_DATE 430 #define CONFIG_CMD_PCI 431 432 #if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT) 433 #undef CONFIG_CMD_SAVEENV 434 #undef CONFIG_CMD_LOADS 435 #endif 436 437 #define CONFIG_CMDLINE_EDITING 1 438 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 439 440 /* 441 * Miscellaneous configurable options 442 */ 443 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 444 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 445 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 446 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 447 448 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 449 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 450 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 451 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 452 453 /* 454 * For booting Linux, the board info and command line data 455 * have to be in the first 8 MB of memory, since this is 456 * the maximum mapped by the Linux kernel during initialization. 457 */ 458 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 459 460 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ 461 462 #ifdef CONFIG_SYS_66MHZ 463 464 /* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */ 465 /* 0x62040000 */ 466 #define CONFIG_SYS_HRCW_LOW (\ 467 0x20000000 /* reserved, must be set */ |\ 468 HRCWL_DDRCM |\ 469 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 470 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 471 HRCWL_CSB_TO_CLKIN_2X1 |\ 472 HRCWL_CORE_TO_CSB_2X1) 473 474 #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2) 475 476 #elif defined(CONFIG_SYS_33MHZ) 477 478 /* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */ 479 /* 0x65040000 */ 480 #define CONFIG_SYS_HRCW_LOW (\ 481 0x20000000 /* reserved, must be set */ |\ 482 HRCWL_DDRCM |\ 483 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 484 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 485 HRCWL_CSB_TO_CLKIN_5X1 |\ 486 HRCWL_CORE_TO_CSB_2X1) 487 488 #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 5) 489 490 #endif 491 492 #define CONFIG_SYS_HRCW_HIGH_BASE (\ 493 HRCWH_PCI_HOST |\ 494 HRCWH_PCI1_ARBITER_ENABLE |\ 495 HRCWH_CORE_ENABLE |\ 496 HRCWH_BOOTSEQ_DISABLE |\ 497 HRCWH_SW_WATCHDOG_DISABLE |\ 498 HRCWH_TSEC1M_IN_RGMII |\ 499 HRCWH_TSEC2M_IN_RGMII |\ 500 HRCWH_BIG_ENDIAN) 501 502 #ifdef CONFIG_NAND_SPL 503 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ 504 HRCWH_FROM_0XFFF00100 |\ 505 HRCWH_ROM_LOC_NAND_SP_8BIT |\ 506 HRCWH_RL_EXT_NAND) 507 #else 508 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ 509 HRCWH_FROM_0X00000100 |\ 510 HRCWH_ROM_LOC_LOCAL_16BIT |\ 511 HRCWH_RL_EXT_LEGACY) 512 #endif 513 514 /* System IO Config */ 515 #define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */ 516 #define CONFIG_SYS_SICRL SICRL_USBDR_10 /* Enable Internal USB Phy */ 517 518 #define CONFIG_SYS_HID0_INIT 0x000000000 519 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 520 HID0_ENABLE_INSTRUCTION_CACHE | \ 521 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) 522 523 #define CONFIG_SYS_HID2 HID2_HBE 524 525 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 526 527 /* DDR @ 0x00000000 */ 528 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10) 529 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 530 531 /* PCI @ 0x80000000 */ 532 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10) 533 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 534 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 535 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 536 537 /* PCI2 not supported on 8313 */ 538 #define CONFIG_SYS_IBAT3L (0) 539 #define CONFIG_SYS_IBAT3U (0) 540 #define CONFIG_SYS_IBAT4L (0) 541 #define CONFIG_SYS_IBAT4U (0) 542 543 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ 544 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 545 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) 546 547 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 548 #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_GUARDEDSTORAGE) 549 #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 550 551 #define CONFIG_SYS_IBAT7L (0) 552 #define CONFIG_SYS_IBAT7U (0) 553 554 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 555 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 556 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 557 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 558 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 559 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 560 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 561 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 562 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 563 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 564 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 565 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 566 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 567 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 568 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 569 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 570 571 /* 572 * Internal Definitions 573 * 574 * Boot Flags 575 */ 576 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 577 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 578 579 /* 580 * Environment Configuration 581 */ 582 #define CONFIG_ENV_OVERWRITE 583 584 #define CONFIG_NETDEV eth1 585 586 #define CONFIG_HOSTNAME mpc8313erdb 587 #define CONFIG_ROOTPATH /nfs/root/path 588 #define CONFIG_BOOTFILE uImage 589 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 590 #define CONFIG_FDTFILE mpc8313erdb.dtb 591 592 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 593 #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ 594 #define CONFIG_BAUDRATE 115200 595 596 #define XMK_STR(x) #x 597 #define MK_STR(x) XMK_STR(x) 598 599 #define CONFIG_EXTRA_ENV_SETTINGS \ 600 "netdev=" MK_STR(CONFIG_NETDEV) "\0" \ 601 "ethprime=TSEC1\0" \ 602 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 603 "tftpflash=tftpboot $loadaddr $uboot; " \ 604 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ 605 "erase " MK_STR(TEXT_BASE) " +$filesize; " \ 606 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ 607 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ 608 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ 609 "fdtaddr=780000\0" \ 610 "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \ 611 "console=ttyS0\0" \ 612 "setbootargs=setenv bootargs " \ 613 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ 614 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ 615 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 616 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" 617 618 #define CONFIG_NFSBOOTCOMMAND \ 619 "setenv rootdev /dev/nfs;" \ 620 "run setbootargs;" \ 621 "run setipargs;" \ 622 "tftp $loadaddr $bootfile;" \ 623 "tftp $fdtaddr $fdtfile;" \ 624 "bootm $loadaddr - $fdtaddr" 625 626 #define CONFIG_RAMBOOTCOMMAND \ 627 "setenv rootdev /dev/ram;" \ 628 "run setbootargs;" \ 629 "tftp $ramdiskaddr $ramdiskfile;" \ 630 "tftp $loadaddr $bootfile;" \ 631 "tftp $fdtaddr $fdtfile;" \ 632 "bootm $loadaddr $ramdiskaddr $fdtaddr" 633 634 #undef MK_STR 635 #undef XMK_STR 636 637 #endif /* __CONFIG_H */ 638