1 /* 2 * (C) Copyright 2001 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 /* ------------------------------------------------------------------------- */ 25 26 /* 27 * board/config.h - configuration options, board specific 28 */ 29 30 #ifndef __CONFIG_H 31 #define __CONFIG_H 32 33 /* 34 * High Level Configuration Options 35 * (easy to change) 36 */ 37 38 #define CONFIG_MPC824X 1 39 /* #define CONFIG_MPC8240 1 */ 40 #define CONFIG_MPC8245 1 41 #define CONFIG_EXALION 1 42 43 #if defined (CONFIG_MPC8240) 44 /* #warning ---------- eXalion with MPC8240 --------------- */ 45 #elif defined (CONFIG_MPC8245) 46 /* #warning ++++++++++ eXalion with MPC8245 +++++++++++++++ */ 47 #elif defined (CONFIG_MPC8245) && defined (CONFIG_MPC8245) 48 #error #### Both types of MPC824x defined (CONFIG_8240 and CONFIG_8245) 49 #else 50 #error #### Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240) 51 #endif 52 /* older kernels need clock in MHz newer in Hz */ 53 /* #define CONFIG_CLOCKS_IN_MHZ 1 */ /* clocks passsed to Linux in MHz */ 54 #undef CONFIG_CLOCKS_IN_MHZ 55 56 #define CONFIG_BOOTDELAY 10 57 58 59 /*#define CONFIG_DRAM_SPEED 66 */ /* MHz */ 60 61 /* 62 * BOOTP options 63 */ 64 #define CONFIG_BOOTP_BOOTFILESIZE 65 #define CONFIG_BOOTP_BOOTPATH 66 #define CONFIG_BOOTP_GATEWAY 67 #define CONFIG_BOOTP_HOSTNAME 68 69 70 /* 71 * Command line configuration. 72 */ 73 #include <config_cmd_default.h> 74 75 #define CONFIG_CMD_FLASH 76 #define CONFIG_CMD_SDRAM 77 #define CONFIG_CMD_I2C 78 #define CONFIG_CMD_IDE 79 #define CONFIG_CMD_FAT 80 #define CONFIG_CMD_SAVEENV 81 #define CONFIG_CMD_PCI 82 83 84 /*----------------------------------------------------------------------- 85 * Miscellaneous configurable options 86 */ 87 #define CONFIG_SYS_LONGHELP 1 /* undef to save memory */ 88 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 89 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 90 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 91 #define CONFIG_SYS_MAXARGS 8 /* max number of command args */ 92 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 93 #define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */ 94 95 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 96 97 #define CONFIG_MISC_INIT_R 1 98 99 /*----------------------------------------------------------------------- 100 * Start addresses for the final memory configuration 101 * (Set up by the startup code) 102 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 103 */ 104 #define CONFIG_SYS_SDRAM_BASE 0x00000000 105 #define CONFIG_SYS_MAX_RAM_SIZE 0x10000000 /* 1 GBytes - initdram() will */ 106 /* return real value. */ 107 108 #define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 109 110 #undef CONFIG_SYS_RAMBOOT 111 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 112 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE 113 114 /*----------------------------------------------------------------------- 115 * Definitions for initial stack pointer and data area 116 */ 117 #define CONFIG_SYS_INIT_DATA_SIZE 128 118 119 #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 120 #define CONFIG_SYS_INIT_RAM_END 0x1000 121 #define CONFIG_SYS_INIT_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_INIT_DATA_SIZE) 122 123 #define CONFIG_SYS_GBL_DATA_SIZE 256 /* size in bytes reserved for initial data */ 124 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 125 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 126 127 128 #if defined (CONFIG_MPC8240) 129 #define CONFIG_SYS_FLASH_BASE 0xFFE00000 130 #define CONFIG_SYS_FLASH_SIZE (2 * 1024 * 1024) /* onboard 2MByte flash */ 131 #elif defined (CONFIG_MPC8245) 132 #define CONFIG_SYS_FLASH_BASE 0xFFC00000 133 #define CONFIG_SYS_FLASH_SIZE (4 * 1024 * 1024) /* onboard 4MByte flash */ 134 #else 135 #error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240) 136 #endif 137 138 #define CONFIG_ENV_IS_IN_FLASH 1 139 #define CONFIG_ENV_SECT_SIZE 0x20000 /* Size of one Flash sector */ 140 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE /* Use one Flash sector for enviroment */ 141 #define CONFIG_ENV_ADDR 0xFFFC0000 142 #define CONFIG_ENV_OFFSET 0 /* starting right at the beginning */ 143 144 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ 145 146 #define CONFIG_SYS_ALT_MEMTEST 1 /* use real memory test */ 147 #define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */ 148 #define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */ 149 150 #define CONFIG_SYS_EUMB_ADDR 0xFC000000 151 152 /* #define CONFIG_SYS_ISA_MEM 0xFD000000 */ 153 #define CONFIG_SYS_ISA_IO 0xFE000000 154 155 /*----------------------------------------------------------------------- 156 * FLASH organization 157 */ 158 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */ 159 #define CONFIG_SYS_MAX_FLASH_SECT 64 /* Max number of sectors per flash */ 160 161 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ 162 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ 163 164 #define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE 165 #define FLASH_BASE1_PRELIM 0 166 167 168 /*----------------------------------------------------------------------- 169 * FLASH and environment organization 170 */ 171 172 #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ 173 #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ 174 #define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ 175 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 176 #define CONFIG_SYS_FLASH_INCREMENT 0 /* there is only one bank */ 177 #define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware protection */ 178 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ 179 180 181 /*----------------------------------------------------------------------- 182 * PCI stuff 183 */ 184 #define CONFIG_PCI 1 /* include pci support */ 185 #undef CONFIG_PCI_PNP 186 187 #define CONFIG_NET_MULTI 1 /* Multi ethernet cards support */ 188 189 #define CONFIG_EEPRO100 1 190 191 #define PCI_ENET0_MEMADDR 0x80000000 /* Intel 82559ER */ 192 #define PCI_ENET0_IOADDR 0x80000000 193 #define PCI_ENET1_MEMADDR 0x81000000 /* Intel 82559ER */ 194 #define PCI_ENET1_IOADDR 0x81000000 195 #define PCI_ENET2_MEMADDR 0x82000000 /* Broadcom BCM569xx */ 196 #define PCI_ENET2_IOADDR 0x82000000 197 #define PCI_ENET3_MEMADDR 0x83000000 /* Broadcom BCM56xx */ 198 #define PCI_ENET3_IOADDR 0x83000000 199 200 /*----------------------------------------------------------------------- 201 * NS16550 Configuration 202 */ 203 #define CONFIG_SYS_NS16550 1 204 #define CONFIG_SYS_NS16550_SERIAL 1 205 206 #define CONFIG_CONS_INDEX 1 207 #define CONFIG_BAUDRATE 38400 208 209 #define CONFIG_SYS_NS16550_REG_SIZE 1 210 211 #if (CONFIG_CONS_INDEX == 1) 212 #define CONFIG_SYS_NS16550_CLK 1843200 /* COM1 only ! */ 213 #else 214 #define CONFIG_SYS_NS16550_CLK ({ extern ulong get_bus_freq (ulong); get_bus_freq (0); }) 215 #endif 216 217 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_ISA_IO + 0x3F8) 218 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_EUMB_ADDR + 0x4500) 219 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_EUMB_ADDR + 0x4600) 220 221 /*----------------------------------------------------------------------- 222 * select i2c support configuration 223 * 224 * Supported configurations are {none, software, hardware} drivers. 225 * If the software driver is chosen, there are some additional 226 * configuration items that the driver uses to drive the port pins. 227 */ 228 #define CONFIG_HARD_I2C 1 /* To enable I2C support */ 229 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 230 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 231 #define CONFIG_SYS_I2C_SLAVE 0x7F 232 233 /*----------------------------------------------------------------------- 234 * Low Level Configuration Settings 235 * (address mappings, register initial values, etc.) 236 * You should know what you are doing if you make changes here. 237 */ 238 #define CONFIG_SYS_HZ 1000 239 240 #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ 241 #define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 2 /* for MPC8240 only */ 242 243 /*#define CONFIG_133MHZ_DRAM 1 */ /* For 133 MHZ DRAM only !!!!!!!!!!! */ 244 245 #if defined (CONFIG_MPC8245) 246 /* Bit-field values for PMCR2. */ 247 #if defined (CONFIG_133MHZ_DRAM) 248 #define CONFIG_SYS_DLL_EXTEND 0x80 /* use DLL extended range - 133MHz only */ 249 #define CONFIG_SYS_PCI_HOLD_DEL 0x20 /* delay and hold timing - 133MHz only */ 250 #endif 251 252 /* Bit-field values for MIOCR1. */ 253 #if !defined (CONFIG_133MHZ_DRAM) 254 #define CONFIG_SYS_DLL_MAX_DELAY 0x04 /* longer DLL delay line - 66MHz only */ 255 #endif 256 /* Bit-field values for MIOCR2. */ 257 #define CONFIG_SYS_SDRAM_DSCD 0x20 /* SDRAM data in sample clock delay */ 258 /* - note bottom 3 bits MUST be 0 */ 259 #endif 260 261 /* Bit-field values for MCCR1. */ 262 #define CONFIG_SYS_ROMNAL 7 /*rom/flash next access time */ 263 #define CONFIG_SYS_ROMFAL 11 /*rom/flash access time */ 264 265 /* Bit-field values for MCCR2. */ 266 #define CONFIG_SYS_TSWAIT 0x5 /* Transaction Start Wait States timer */ 267 #if defined (CONFIG_133MHZ_DRAM) 268 #define CONFIG_SYS_REFINT 1300 /* no of clock cycles between CBR */ 269 #else /* refresh cycles */ 270 #define CONFIG_SYS_REFINT 750 271 #endif 272 273 /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. */ 274 #if defined (CONFIG_133MHZ_DRAM) 275 #define CONFIG_SYS_BSTOPRE 1023 276 #else 277 #define CONFIG_SYS_BSTOPRE 250 278 #endif 279 280 /* Bit-field values for MCCR3. */ 281 /* the following are for SDRAM only */ 282 283 #if defined (CONFIG_133MHZ_DRAM) 284 #define CONFIG_SYS_REFREC 9 /* Refresh to activate interval */ 285 #else 286 #define CONFIG_SYS_REFREC 5 /* Refresh to activate interval */ 287 #endif 288 #if defined (CONFIG_MPC8240) 289 #define CONFIG_SYS_RDLAT 2 /* data latency from read command */ 290 #endif 291 292 /* Bit-field values for MCCR4. */ 293 #if defined (CONFIG_133MHZ_DRAM) 294 #define CONFIG_SYS_PRETOACT 3 /* Precharge to activate interval */ 295 #define CONFIG_SYS_ACTTOPRE 7 /* Activate to Precharge interval */ 296 #define CONFIG_SYS_ACTORW 5 /* Activate to R/W */ 297 #define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */ 298 #else 299 #if 0 300 #define CONFIG_SYS_PRETOACT 2 /* Precharge to activate interval */ 301 #define CONFIG_SYS_ACTTOPRE 3 /* Activate to Precharge interval */ 302 #define CONFIG_SYS_ACTORW 3 /* Activate to R/W */ 303 #define CONFIG_SYS_SDMODE_CAS_LAT 2 /* SDMODE CAS latency */ 304 #endif 305 #define CONFIG_SYS_PRETOACT 2 /* Precharge to activate interval */ 306 #define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */ 307 #define CONFIG_SYS_ACTORW 3 /* Activate to R/W */ 308 #define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */ 309 #endif 310 #define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */ 311 #define CONFIG_SYS_SDMODE_BURSTLEN 2 /* SDMODE Burst length 2=4, 3=8 */ 312 #define CONFIG_SYS_REGDIMM 0 313 #if defined (CONFIG_MPC8240) 314 #define CONFIG_SYS_REGISTERD_TYPE_BUFFER 0 315 #elif defined (CONFIG_MPC8245) 316 #define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1 317 #define CONFIG_SYS_EXTROM 0 318 #else 319 #error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240) 320 #endif 321 322 323 /*----------------------------------------------------------------------- 324 memory bank settings 325 * only bits 20-29 are actually used from these vales to set the 326 * start/end address the upper two bits will be 0, and the lower 20 327 * bits will be set to 0x00000 for a start address, or 0xfffff for an 328 * end address 329 */ 330 #define CONFIG_SYS_BANK0_START 0x00000000 331 #define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1) 332 #define CONFIG_SYS_BANK0_ENABLE 1 333 #define CONFIG_SYS_BANK1_START 0x3ff00000 334 #define CONFIG_SYS_BANK1_END 0x3fffffff 335 #define CONFIG_SYS_BANK1_ENABLE 0 336 #define CONFIG_SYS_BANK2_START 0x3ff00000 337 #define CONFIG_SYS_BANK2_END 0x3fffffff 338 #define CONFIG_SYS_BANK2_ENABLE 0 339 #define CONFIG_SYS_BANK3_START 0x3ff00000 340 #define CONFIG_SYS_BANK3_END 0x3fffffff 341 #define CONFIG_SYS_BANK3_ENABLE 0 342 #define CONFIG_SYS_BANK4_START 0x00000000 343 #define CONFIG_SYS_BANK4_END 0x00000000 344 #define CONFIG_SYS_BANK4_ENABLE 0 345 #define CONFIG_SYS_BANK5_START 0x00000000 346 #define CONFIG_SYS_BANK5_END 0x00000000 347 #define CONFIG_SYS_BANK5_ENABLE 0 348 #define CONFIG_SYS_BANK6_START 0x00000000 349 #define CONFIG_SYS_BANK6_END 0x00000000 350 #define CONFIG_SYS_BANK6_ENABLE 0 351 #define CONFIG_SYS_BANK7_START 0x00000000 352 #define CONFIG_SYS_BANK7_END 0x00000000 353 #define CONFIG_SYS_BANK7_ENABLE 0 354 355 /*----------------------------------------------------------------------- 356 * Memory bank enable bitmask, specifying which of the banks defined above 357 are actually present. MSB is for bank #7, LSB is for bank #0. 358 */ 359 #define CONFIG_SYS_BANK_ENABLE 0x01 360 361 #if defined (CONFIG_MPC8240) 362 #define CONFIG_SYS_ODCR 0xDF /* configures line driver impedances, */ 363 /* see 8240 book for bit definitions */ 364 #elif defined (CONFIG_MPC8245) 365 #if defined (CONFIG_133MHZ_DRAM) 366 #define CONFIG_SYS_ODCR 0xFE /* configures line driver impedances - 133MHz */ 367 #else 368 #define CONFIG_SYS_ODCR 0xDE /* configures line driver impedances - 66MHz */ 369 #endif 370 #else 371 #error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240) 372 #endif 373 374 #define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 retains the */ 375 /* currently accessed page in memory */ 376 /* see 8240 book for details */ 377 378 /*----------------------------------------------------------------------- 379 * Block Address Translation (BAT) register settings. 380 */ 381 /* SDRAM 0 - 256MB */ 382 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 383 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 384 385 /* stack in DCACHE @ 1GB (no backing mem) */ 386 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) 387 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 388 389 /* PCI memory */ 390 #define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) 391 #define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) 392 393 /* Flash, config addrs, etc */ 394 #define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) 395 #define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 396 397 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 398 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 399 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 400 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 401 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 402 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 403 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 404 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 405 406 407 /*----------------------------------------------------------------------- 408 * Cache Configuration 409 */ 410 #define CONFIG_SYS_CACHELINE_SIZE 32 411 #if defined(CONFIG_CMD_KGDB) 412 # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ 413 #endif 414 415 416 /*----------------------------------------------------------------------- 417 * Internal Definitions 418 * 419 * Boot Flags 420 */ 421 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 422 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 423 424 425 /* values according to the manual */ 426 #define CONFIG_DRAM_50MHZ 1 427 #define CONFIG_SDRAM_50MHZ 428 429 #undef NR_8259_INTS 430 #define NR_8259_INTS 1 431 432 /*----------------------------------------------------------------------- 433 * IDE/ATA stuff 434 */ 435 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 2 IDE busses */ 436 #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 2 drives per IDE bus */ 437 438 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_ISA_IO /* base address */ 439 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */ 440 #define CONFIG_SYS_ATA_IDE1_OFFSET 0x0170 /* ide1 offset */ 441 #define CONFIG_SYS_ATA_DATA_OFFSET 0 /* data reg offset */ 442 #define CONFIG_SYS_ATA_REG_OFFSET 0 /* reg offset */ 443 #define CONFIG_SYS_ATA_ALT_OFFSET 0x200 /* alternate register offset */ 444 445 #define CONFIG_ATAPI 446 447 #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ 448 #undef CONFIG_IDE_LED /* no led for ide supported */ 449 #undef CONFIG_IDE_RESET /* reset for ide supported... */ 450 #undef CONFIG_IDE_RESET_ROUTINE /* with a special reset function */ 451 452 /*----------------------------------------------------------------------- 453 * DISK Partition support 454 */ 455 #define CONFIG_DOS_PARTITION 456 457 /*----------------------------------------------------------------------- 458 * For booting Linux, the board info and command line data 459 * have to be in the first 8 MB of memory, since this is 460 * the maximum mapped by the Linux kernel during initialization. 461 */ 462 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 463 464 #endif /* __CONFIG_H */ 465