1/*
2 * (C) Copyright 2000-2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * This file contains all the macros and symbols which define
26 * a PowerPC assembly language environment.
27 */
28#ifndef	__PPC_ASM_TMPL__
29#define __PPC_ASM_TMPL__
30
31/***************************************************************************
32 *
33 * These definitions simplify the ugly declarations necessary for GOT
34 * definitions.
35 *
36 * Stolen from prepboot/bootldr.h, (C) 1998 Gabriel Paubert, paubert@iram.es
37 *
38 * Uses r12 to access the GOT
39 */
40
41#define START_GOT			\
42	.section	".got2","aw";	\
43.LCTOC1 = .+32768
44
45#define END_GOT				\
46	.text
47
48#define GET_GOT				\
49	bl	1f		;	\
50	.text	2		;	\
510:	.long	.LCTOC1-1f	;	\
52	.text			;	\
531:	mflr	r12		;	\
54	lwz	r0,0b-1b(r12)	;	\
55	add	r12,r0,r12	;
56
57#define GOT_ENTRY(NAME)		.L_ ## NAME = . - .LCTOC1 ; .long NAME
58
59#define GOT(NAME)		.L_ ## NAME (r12)
60
61
62/***************************************************************************
63 * Register names
64 */
65#define	r0	0
66#define	r1	1
67#define	r2	2
68#define	r3	3
69#define	r4	4
70#define	r5	5
71#define	r6	6
72#define	r7	7
73#define	r8	8
74#define	r9	9
75#define	r10	10
76#define	r11	11
77#define	r12	12
78#define	r13	13
79#define	r14	14
80#define	r15	15
81#define	r16	16
82#define	r17	17
83#define	r18	18
84#define	r19	19
85#define	r20	20
86#define	r21	21
87#define	r22	22
88#define	r23	23
89#define	r24	24
90#define	r25	25
91#define	r26	26
92#define	r27	27
93#define	r28	28
94#define	r29	29
95#define	r30	30
96#define	r31	31
97
98
99#if defined(CONFIG_8xx) || defined(CONFIG_MPC824X)
100
101/* Some special registers */
102
103#define ICR	148	/* Interrupt Cause Register (37-44) */
104#define DER	149
105#define COUNTA	150	/* Breakpoint Counter	    (37-44) */
106#define COUNTB	151	/* Breakpoint Counter	    (37-44) */
107#define LCTRL1	156	/* Load/Store Support	    (37-40) */
108#define LCTRL2	157	/* Load/Store Support	    (37-41) */
109#define ICTRL	158
110
111#endif	/* CONFIG_8xx, CONFIG_MPC824X */
112
113
114#if  defined(CONFIG_5xx)
115/* Some special purpose registers */
116#define DER	149		/* Debug Enable Register		*/
117#define COUNTA	150		/* Breakpoint Counter			*/
118#define COUNTB	151		/* Breakpoint Counter			*/
119#define LCTRL1	156		/* Load/Store Support			*/
120#define LCTRL2	157		/* Load/Store Support			*/
121#define ICTRL	158		/* I-Bus Support Control Register	*/
122#define EID	81
123#endif	/* CONFIG_5xx */
124
125#if defined(CONFIG_8xx)
126
127/* Registers in the processor's internal memory map that we use.
128*/
129#define SYPCR	0x00000004
130#define BR0	0x00000100
131#define OR0	0x00000104
132#define BR1	0x00000108
133#define OR1	0x0000010c
134#define BR2	0x00000110
135#define OR2	0x00000114
136#define BR3	0x00000118
137#define OR3	0x0000011c
138#define BR4	0x00000120
139#define OR4	0x00000124
140
141#define MAR	0x00000164
142#define MCR	0x00000168
143#define MAMR	0x00000170
144#define MBMR	0x00000174
145#define MSTAT	0x00000178
146#define MPTPR	0x0000017a
147#define MDR	0x0000017c
148
149#define TBSCR	0x00000200
150#define TBREFF0	0x00000204
151
152#define PLPRCR	0x00000284
153
154#elif defined(CONFIG_8260)
155
156#define HID2		1011
157
158#define HID0_IFEM	(1<<7)
159
160#define HID0_ICE_BITPOS	16
161#define HID0_DCE_BITPOS	17
162
163#define IM_REGBASE	0x10000
164#define IM_SYPCR	(IM_REGBASE+0x0004)
165#define IM_SWSR		(IM_REGBASE+0x000e)
166#define IM_BR0		(IM_REGBASE+0x0100)
167#define IM_OR0		(IM_REGBASE+0x0104)
168#define IM_BR1		(IM_REGBASE+0x0108)
169#define IM_OR1		(IM_REGBASE+0x010c)
170#define IM_BR2		(IM_REGBASE+0x0110)
171#define IM_OR2		(IM_REGBASE+0x0114)
172#define IM_MPTPR	(IM_REGBASE+0x0184)
173#define IM_PSDMR	(IM_REGBASE+0x0190)
174#define IM_PSRT		(IM_REGBASE+0x019c)
175#define IM_IMMR		(IM_REGBASE+0x01a8)
176#define IM_SCCR		(IM_REGBASE+0x0c80)
177
178#elif defined(CONFIG_MPC5xxx) || defined(CONFIG_MPC8220)
179
180#define HID0_ICE_BITPOS	16
181#define HID0_DCE_BITPOS	17
182
183#endif
184
185#define curptr r2
186
187#define SYNC \
188	sync; \
189	isync
190
191/*
192 * Macros for storing registers into and loading registers from
193 * exception frames.
194 */
195#define SAVE_GPR(n, base)	stw	n,GPR0+4*(n)(base)
196#define SAVE_2GPRS(n, base)	SAVE_GPR(n, base); SAVE_GPR(n+1, base)
197#define SAVE_4GPRS(n, base)	SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
198#define SAVE_8GPRS(n, base)	SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
199#define SAVE_10GPRS(n, base)	SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
200#define REST_GPR(n, base)	lwz	n,GPR0+4*(n)(base)
201#define REST_2GPRS(n, base)	REST_GPR(n, base); REST_GPR(n+1, base)
202#define REST_4GPRS(n, base)	REST_2GPRS(n, base); REST_2GPRS(n+2, base)
203#define REST_8GPRS(n, base)	REST_4GPRS(n, base); REST_4GPRS(n+4, base)
204#define REST_10GPRS(n, base)	REST_8GPRS(n, base); REST_2GPRS(n+8, base)
205
206/*
207 * GCC sometimes accesses words at negative offsets from the stack
208 * pointer, although the SysV ABI says it shouldn't.  To cope with
209 * this, we leave this much untouched space on the stack on exception
210 * entry.
211 */
212#define STACK_UNDERHEAD	64
213
214/*
215 * Exception entry code.  This code runs with address translation
216 * turned off, i.e. using physical addresses.
217 * We assume sprg3 has the physical address of the current
218 * task's thread_struct.
219 */
220#define EXCEPTION_PROLOG(reg1, reg2)	\
221	mtspr	SPRG0,r20;	\
222	mtspr	SPRG1,r21;	\
223	mfcr	r20;		\
224	subi	r21,r1,INT_FRAME_SIZE+STACK_UNDERHEAD;	/* alloc exc. frame */\
225	stw	r20,_CCR(r21);		/* save registers */ \
226	stw	r22,GPR22(r21);	\
227	stw	r23,GPR23(r21);	\
228	mfspr	r20,SPRG0;	\
229	stw	r20,GPR20(r21);	\
230	mfspr	r22,SPRG1;	\
231	stw	r22,GPR21(r21);	\
232	mflr	r20;		\
233	stw	r20,_LINK(r21);	\
234	mfctr	r22;		\
235	stw	r22,_CTR(r21);	\
236	mfspr	r20,XER;	\
237	stw	r20,_XER(r21);	\
238	mfspr	r20, DAR_DEAR;	\
239	stw	r20,_DAR(r21);	\
240	mfspr	r22,reg1;	\
241	mfspr	r23,reg2;	\
242	stw	r0,GPR0(r21);	\
243	stw	r1,GPR1(r21);	\
244	stw	r2,GPR2(r21);	\
245	stw	r1,0(r21);	\
246	mr	r1,r21;			/* set new kernel sp */	\
247	SAVE_4GPRS(3, r21);
248/*
249 * Note: code which follows this uses cr0.eq (set if from kernel),
250 * r21, r22 (SRR0), and r23 (SRR1).
251 */
252
253/*
254 * Exception vectors.
255 *
256 * The data words for `hdlr' and `int_return' are initialized with
257 * OFFSET values only; they must be relocated first before they can
258 * be used!
259 */
260#define COPY_EE(d, s)		rlwimi d,s,0,16,16
261#define NOCOPY(d, s)
262#define EXC_XFER_TEMPLATE(label, hdlr, msr, copyee)	\
263	bl	1f;					\
2641:	mflr    r20;					\
265	lwz	r20,(.L_ ## label)-1b+8(r20);		\
266	mtlr	r20;					\
267	li	r20,msr;				\
268	copyee(r20,r23);				\
269	rlwimi	r20,r23,0,25,25;			\
270	blrl;						\
271.L_ ## label :						\
272	.long	hdlr - _start + _START_OFFSET;		\
273	.long	int_return - _start + _START_OFFSET;	\
274	.long	transfer_to_handler - _start + _START_OFFSET
275
276#define STD_EXCEPTION(n, label, hdlr)				\
277	. = n;							\
278label:								\
279	EXCEPTION_PROLOG(SRR0, SRR1);				\
280	addi	r3,r1,STACK_FRAME_OVERHEAD;			\
281	EXC_XFER_TEMPLATE(label, hdlr, MSR_KERNEL, NOCOPY)	\
282
283#define CRIT_EXCEPTION(n, label, hdlr)				\
284	. = n;							\
285label:								\
286	EXCEPTION_PROLOG(CSRR0, CSRR1);				\
287	addi	r3,r1,STACK_FRAME_OVERHEAD;			\
288	EXC_XFER_TEMPLATE(label, hdlr,				\
289	MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE), NOCOPY)		\
290
291#define MCK_EXCEPTION(n, label, hdlr)				\
292	. = n;							\
293label:								\
294	EXCEPTION_PROLOG(MCSRR0, MCSRR1);			\
295	addi	r3,r1,STACK_FRAME_OVERHEAD;			\
296	EXC_XFER_TEMPLATE(label, hdlr,				\
297	MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE), NOCOPY)		\
298
299#endif	/* __PPC_ASM_TMPL__ */
300