1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 *  armboot - Startup Code for ARM926EJS CPU-core
4 *
5 *  Copyright (c) 2003  Texas Instruments
6 *
7 *  ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
8 *
9 *  Copyright (c) 2001	Marius Groger <mag@sysgo.de>
10 *  Copyright (c) 2002	Alex Zupke <azu@sysgo.de>
11 *  Copyright (c) 2002	Gary Jennejohn <garyj@denx.de>
12 *  Copyright (c) 2003	Richard Woodruff <r-woodruff2@ti.com>
13 *  Copyright (c) 2003	Kshitij <kshitij@ti.com>
14 *  Copyright (c) 2010	Albert Aribaud <albert.u.boot@aribaud.net>
15 *
16 * Change to support call back into iMX28 bootrom
17 * Copyright (c) 2011 Marek Vasut <marek.vasut@gmail.com>
18 * on behalf of DENX Software Engineering GmbH
19 */
20
21#include <asm-offsets.h>
22#include <config.h>
23#include <common.h>
24
25/*
26 *************************************************************************
27 *
28 * Startup Code (reset vector)
29 *
30 * do important init only if we don't start from memory!
31 * setup Memory and board specific bits prior to relocation.
32 * relocate armboot to ram
33 * setup stack
34 *
35 *************************************************************************
36 */
37
38	.globl	reset
39reset:
40	/*
41	 * If the CPU is configured in "Wait JTAG connection mode", the stack
42	 * pointer is not configured and is zero. This will cause crash when
43	 * trying to push data onto stack right below here. Load the SP and make
44	 * it point to the end of OCRAM if the SP is zero.
45	 */
46	cmp	sp, #0x00000000
47	ldreq	sp, =CONFIG_SYS_INIT_SP_ADDR
48
49	/*
50	 * Store all registers on old stack pointer, this will allow us later to
51	 * return to the BootROM and let the BootROM load U-Boot into RAM.
52	 *
53	 * WARNING: Register r0 and r1 are used by the BootROM to pass data
54	 *          to the called code. Register r0 will contain arbitrary
55	 *          data that are set in the BootStream. In case this code
56	 *          was started with CALL instruction, register r1 will contain
57	 *          pointer to the return value this function can then set.
58	 *          The code below MUST NOT CHANGE register r0 and r1 !
59	 */
60	push	{r0-r12,r14}
61
62	/* Save control register c1 */
63	mrc	p15, 0, r2, c1, c0, 0
64	push	{r2}
65
66	/* Set the cpu to SVC32 mode and store old CPSR register content. */
67	mrs	r2, cpsr
68	push	{r2}
69	bic	r2, r2, #0x1f
70	orr	r2, r2, #0xd3
71	msr	cpsr, r2
72
73	bl	board_init_ll
74
75	/* Restore BootROM's CPU mode (especially FIQ). */
76	pop	{r2}
77	msr	cpsr,r2
78
79	/*
80	 * Restore c1 register. Especially set exception vector location
81	 * back to BootROM space which is required by bootrom for USB boot.
82	 */
83	pop	{r2}
84	mcr	p15, 0, r2, c1, c0, 0
85
86	pop	{r0-r12,r14}
87
88	/*
89	 * In case this code was started by the CALL instruction, the register
90	 * r0 is examined by the BootROM after this code returns. The value in
91	 * r0 must be set to 0 to indicate successful return.
92	 */
93	mov r0, #0
94
95	bx	lr
96