1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * fsl_mcdmafec.h -- Multi-channel DMA Fast Ethernet Controller definitions
4  *
5  * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
6  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7  */
8 
9 #ifndef fsl_mcdmafec_h
10 #define fsl_mcdmafec_h
11 
12 /* Re-use of the definitions */
13 #include <asm/fec.h>
14 
15 typedef struct fecdma {
16 	u32 rsvd0;		/* 0x000 */
17 	u32 eir;		/* 0x004 */
18 	u32 eimr;		/* 0x008 */
19 	u32 rsvd1[6];		/* 0x00C - 0x023 */
20 	u32 ecr;		/* 0x024 */
21 	u32 rsvd2[6];		/* 0x028 - 0x03F */
22 	u32 mmfr;		/* 0x040 */
23 	u32 mscr;		/* 0x044 */
24 	u32 rsvd3[7];		/* 0x048 - 0x063 */
25 	u32 mibc;		/* 0x064 */
26 	u32 rsvd4[7];		/* 0x068 - 0x083 */
27 	u32 rcr;		/* 0x084 */
28 	u32 rhr;		/* 0x088 */
29 	u32 rsvd5[14];		/* 0x08C - 0x0C3 */
30 	u32 tcr;		/* 0x0C4 */
31 	u32 rsvd6[7];		/* 0x0C8 - 0x0E3 */
32 	u32 palr;		/* 0x0E4 */
33 	u32 paur;		/* 0x0E8 */
34 	u32 opd;		/* 0x0EC */
35 	u32 rsvd7[10];		/* 0x0F0 - 0x117 */
36 	u32 iaur;		/* 0x118 */
37 	u32 ialr;		/* 0x11C */
38 	u32 gaur;		/* 0x120 */
39 	u32 galr;		/* 0x124 */
40 	u32 rsvd8[7];		/* 0x128 - 0x143 */
41 	u32 tfwr;		/* 0x144 */
42 	u32 rsvd9[14];		/* 0x148 - 0x17F */
43 	u32 fmc;		/* 0x180 */
44 	u32 rfdr;		/* 0x184 */
45 	u32 rfsr;		/* 0x188 */
46 	u32 rfcr;		/* 0x18C */
47 	u32 rlrfp;		/* 0x190 */
48 	u32 rlwfp;		/* 0x194 */
49 	u32 rfar;		/* 0x198 */
50 	u32 rfrp;		/* 0x19C */
51 	u32 rfwp;		/* 0x1A0 */
52 	u32 tfdr;		/* 0x1A4 */
53 	u32 tfsr;		/* 0x1A8 */
54 	u32 tfcr;		/* 0x1AC */
55 	u32 tlrfp;		/* 0x1B0 */
56 	u32 tlwfp;		/* 0x1B4 */
57 	u32 tfar;		/* 0x1B8 */
58 	u32 tfrp;		/* 0x1BC */
59 	u32 tfwp;		/* 0x1C0 */
60 	u32 frst;		/* 0x1C4 */
61 	u32 ctcwr;		/* 0x1C8 */
62 } fecdma_t;
63 
64 struct fec_info_dma {
65 	int index;
66 	u32 iobase;
67 	u32 pinmux;
68 	u32 miibase;
69 	int phy_addr;
70 	int dup_spd;
71 	char *phy_name;
72 	int phyname_init;
73 	cbd_t *rxbd;		/* Rx BD */
74 	cbd_t *txbd;		/* Tx BD */
75 	uint rxIdx;
76 	uint txIdx;
77 	char *txbuf;
78 	int initialized;
79 	struct fec_info_dma *next;
80 
81 	u16 rxTask;		/* DMA receive Task Number */
82 	u16 txTask;		/* DMA Transmit Task Number */
83 	u16 rxPri;		/* DMA Receive Priority */
84 	u16 txPri;		/* DMA Transmit Priority */
85 	u16 rxInit;		/* DMA Receive Initiator */
86 	u16 txInit;		/* DMA Transmit Initiator */
87 	u16 usedTbdIdx;		/* next transmit BD to clean */
88 	u16 cleanTbdNum;	/* the number of available transmit BDs */
89 };
90 
91 /* Bit definitions and macros for IEVENT */
92 #define FEC_EIR_TXERR		(0x00040000)
93 #define FEC_EIR_RXERR		(0x00020000)
94 #undef FEC_EIR_CLEAR_ALL
95 #define FEC_EIR_CLEAR_ALL	(0xFFFE0000)
96 
97 /* Bit definitions and macros for R_HASH */
98 #define FEC_RHASH_FCE_DC	(0x80000000)
99 #define FEC_RHASH_MULTCAST	(0x40000000)
100 #define FEC_RHASH_HASH(x)	(((x)&0x0000003F)<<24)
101 
102 /* Bit definitions and macros for FEC_TFWR */
103 #undef FEC_TFWR_X_WMRK
104 #undef FEC_TFWR_X_WMRK_64
105 #undef FEC_TFWR_X_WMRK_128
106 #undef FEC_TFWR_X_WMRK_192
107 
108 #define FEC_TFWR_X_WMRK(x)	((x)&0x0F)
109 #define FEC_TFWR_X_WMRK_64	(0x00)
110 #define FEC_TFWR_X_WMRK_128	(0x01)
111 #define FEC_TFWR_X_WMRK_192	(0x02)
112 #define FEC_TFWR_X_WMRK_256	(0x03)
113 #define FEC_TFWR_X_WMRK_320	(0x04)
114 #define FEC_TFWR_X_WMRK_384	(0x05)
115 #define FEC_TFWR_X_WMRK_448	(0x06)
116 #define FEC_TFWR_X_WMRK_512	(0x07)
117 #define FEC_TFWR_X_WMRK_576	(0x08)
118 #define FEC_TFWR_X_WMRK_640	(0x09)
119 #define FEC_TFWR_X_WMRK_704	(0x0A)
120 #define FEC_TFWR_X_WMRK_768	(0x0B)
121 #define FEC_TFWR_X_WMRK_832	(0x0C)
122 #define FEC_TFWR_X_WMRK_896	(0x0D)
123 #define FEC_TFWR_X_WMRK_960	(0x0E)
124 #define FEC_TFWR_X_WMRK_1024	(0x0F)
125 
126 /* FIFO definitions */
127 /* Bit definitions and macros for FSTAT */
128 #define FIFO_STAT_IP		(0x80000000)
129 #define FIFO_STAT_FRAME(x)	(((x)&0x0000000F)<<24)
130 #define FIFO_STAT_FAE		(0x00800000)
131 #define FIFO_STAT_RXW		(0x00400000)
132 #define FIFO_STAT_UF		(0x00200000)
133 #define FIFO_STAT_OF		(0x00100000)
134 #define FIFO_STAT_FR		(0x00080000)
135 #define FIFO_STAT_FULL		(0x00040000)
136 #define FIFO_STAT_ALARM		(0x00020000)
137 #define FIFO_STAT_EMPTY		(0x00010000)
138 
139 /* Bit definitions and macros for FCTRL */
140 #define FIFO_CTRL_WCTL		(0x40000000)
141 #define FIFO_CTRL_WFR		(0x20000000)
142 #define FIFO_CTRL_FRAME		(0x08000000)
143 #define FIFO_CTRL_GR(x)		(((x)&0x00000007)<<24)
144 #define FIFO_CTRL_IPMASK	(0x00800000)
145 #define FIFO_CTRL_FAEMASK	(0x00400000)
146 #define FIFO_CTRL_RXWMASK	(0x00200000)
147 #define FIFO_CTRL_UFMASK	(0x00100000)
148 #define FIFO_CTRL_OFMASK	(0x00080000)
149 
150 #endif				/* fsl_mcdmafec_h */
151