1//===-- X86.td - Target definition file for the Intel X86 --*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This is a target description file for the Intel i386 architecture, referred
11// to here as the "X86" architecture.
12//
13//===----------------------------------------------------------------------===//
14
15// Get the target-independent interfaces which we are implementing...
16//
17include "llvm/Target/Target.td"
18
19//===----------------------------------------------------------------------===//
20// X86 Subtarget state
21//
22
23def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true",
24                                  "64-bit mode (x86_64)">;
25def Mode32Bit : SubtargetFeature<"32bit-mode", "In32BitMode", "true",
26                                  "32-bit mode (80386)">;
27def Mode16Bit : SubtargetFeature<"16bit-mode", "In16BitMode", "true",
28                                  "16-bit mode (i8086)">;
29
30//===----------------------------------------------------------------------===//
31// X86 Subtarget features
32//===----------------------------------------------------------------------===//
33
34def FeatureX87     : SubtargetFeature<"x87","HasX87", "true",
35                                      "Enable X87 float instructions">;
36
37def FeatureNOPL    : SubtargetFeature<"nopl", "HasNOPL", "true",
38                                      "Enable NOPL instruction">;
39
40def FeatureCMOV    : SubtargetFeature<"cmov","HasCMov", "true",
41                                      "Enable conditional move instructions">;
42
43def FeaturePOPCNT   : SubtargetFeature<"popcnt", "HasPOPCNT", "true",
44                                       "Support POPCNT instruction">;
45
46def FeatureFXSR    : SubtargetFeature<"fxsr", "HasFXSR", "true",
47                                      "Support fxsave/fxrestore instructions">;
48
49def FeatureXSAVE   : SubtargetFeature<"xsave", "HasXSAVE", "true",
50                                       "Support xsave instructions">;
51
52def FeatureXSAVEOPT: SubtargetFeature<"xsaveopt", "HasXSAVEOPT", "true",
53                                       "Support xsaveopt instructions">;
54
55def FeatureXSAVEC  : SubtargetFeature<"xsavec", "HasXSAVEC", "true",
56                                       "Support xsavec instructions">;
57
58def FeatureXSAVES  : SubtargetFeature<"xsaves", "HasXSAVES", "true",
59                                       "Support xsaves instructions">;
60
61def FeatureSSE1    : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
62                                      "Enable SSE instructions",
63                                      // SSE codegen depends on cmovs, and all
64                                      // SSE1+ processors support them.
65                                      [FeatureCMOV]>;
66def FeatureSSE2    : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
67                                      "Enable SSE2 instructions",
68                                      [FeatureSSE1]>;
69def FeatureSSE3    : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
70                                      "Enable SSE3 instructions",
71                                      [FeatureSSE2]>;
72def FeatureSSSE3   : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
73                                      "Enable SSSE3 instructions",
74                                      [FeatureSSE3]>;
75def FeatureSSE41   : SubtargetFeature<"sse4.1", "X86SSELevel", "SSE41",
76                                      "Enable SSE 4.1 instructions",
77                                      [FeatureSSSE3]>;
78def FeatureSSE42   : SubtargetFeature<"sse4.2", "X86SSELevel", "SSE42",
79                                      "Enable SSE 4.2 instructions",
80                                      [FeatureSSE41]>;
81// The MMX subtarget feature is separate from the rest of the SSE features
82// because it's important (for odd compatibility reasons) to be able to
83// turn it off explicitly while allowing SSE+ to be on.
84def FeatureMMX     : SubtargetFeature<"mmx","X863DNowLevel", "MMX",
85                                      "Enable MMX instructions">;
86def Feature3DNow   : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
87                                      "Enable 3DNow! instructions",
88                                      [FeatureMMX]>;
89def Feature3DNowA  : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
90                                      "Enable 3DNow! Athlon instructions",
91                                      [Feature3DNow]>;
92// All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
93// feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
94// without disabling 64-bit mode.
95def Feature64Bit   : SubtargetFeature<"64bit", "HasX86_64", "true",
96                                      "Support 64-bit instructions",
97                                      [FeatureCMOV]>;
98def FeatureCMPXCHG16B : SubtargetFeature<"cx16", "HasCmpxchg16b", "true",
99                                      "64-bit with cmpxchg16b",
100                                      [Feature64Bit]>;
101def FeatureSlowSHLD : SubtargetFeature<"slow-shld", "IsSHLDSlow", "true",
102                                       "SHLD instruction is slow">;
103def FeatureSlowPMULLD : SubtargetFeature<"slow-pmulld", "IsPMULLDSlow", "true",
104                                        "PMULLD instruction is slow">;
105// FIXME: This should not apply to CPUs that do not have SSE.
106def FeatureSlowUAMem16 : SubtargetFeature<"slow-unaligned-mem-16",
107                                "IsUAMem16Slow", "true",
108                                "Slow unaligned 16-byte memory access">;
109def FeatureSlowUAMem32 : SubtargetFeature<"slow-unaligned-mem-32",
110                                "IsUAMem32Slow", "true",
111                                "Slow unaligned 32-byte memory access">;
112def FeatureSSE4A   : SubtargetFeature<"sse4a", "HasSSE4A", "true",
113                                      "Support SSE 4a instructions",
114                                      [FeatureSSE3]>;
115
116def FeatureAVX     : SubtargetFeature<"avx", "X86SSELevel", "AVX",
117                                      "Enable AVX instructions",
118                                      [FeatureSSE42]>;
119def FeatureAVX2    : SubtargetFeature<"avx2", "X86SSELevel", "AVX2",
120                                      "Enable AVX2 instructions",
121                                      [FeatureAVX]>;
122def FeatureFMA     : SubtargetFeature<"fma", "HasFMA", "true",
123                                      "Enable three-operand fused multiple-add",
124                                      [FeatureAVX]>;
125def FeatureF16C    : SubtargetFeature<"f16c", "HasF16C", "true",
126                       "Support 16-bit floating point conversion instructions",
127                       [FeatureAVX]>;
128def FeatureAVX512   : SubtargetFeature<"avx512f", "X86SSELevel", "AVX512F",
129                                      "Enable AVX-512 instructions",
130                                      [FeatureAVX2, FeatureFMA, FeatureF16C]>;
131def FeatureERI      : SubtargetFeature<"avx512er", "HasERI", "true",
132                      "Enable AVX-512 Exponential and Reciprocal Instructions",
133                                      [FeatureAVX512]>;
134def FeatureCDI      : SubtargetFeature<"avx512cd", "HasCDI", "true",
135                      "Enable AVX-512 Conflict Detection Instructions",
136                                      [FeatureAVX512]>;
137def FeatureVPOPCNTDQ : SubtargetFeature<"avx512vpopcntdq", "HasVPOPCNTDQ",
138                       "true", "Enable AVX-512 Population Count Instructions",
139                                      [FeatureAVX512]>;
140def FeaturePFI      : SubtargetFeature<"avx512pf", "HasPFI", "true",
141                      "Enable AVX-512 PreFetch Instructions",
142                                      [FeatureAVX512]>;
143def FeaturePREFETCHWT1  : SubtargetFeature<"prefetchwt1", "HasPREFETCHWT1",
144                                   "true",
145                                   "Prefetch with Intent to Write and T1 Hint">;
146def FeatureDQI     : SubtargetFeature<"avx512dq", "HasDQI", "true",
147                      "Enable AVX-512 Doubleword and Quadword Instructions",
148                                      [FeatureAVX512]>;
149def FeatureBWI     : SubtargetFeature<"avx512bw", "HasBWI", "true",
150                      "Enable AVX-512 Byte and Word Instructions",
151                                      [FeatureAVX512]>;
152def FeatureVLX     : SubtargetFeature<"avx512vl", "HasVLX", "true",
153                      "Enable AVX-512 Vector Length eXtensions",
154                                      [FeatureAVX512]>;
155def FeatureVBMI     : SubtargetFeature<"avx512vbmi", "HasVBMI", "true",
156                      "Enable AVX-512 Vector Byte Manipulation Instructions",
157                                      [FeatureBWI]>;
158def FeatureVBMI2    : SubtargetFeature<"avx512vbmi2", "HasVBMI2", "true",
159                      "Enable AVX-512 further Vector Byte Manipulation Instructions",
160                                      [FeatureBWI]>;
161def FeatureIFMA     : SubtargetFeature<"avx512ifma", "HasIFMA", "true",
162                      "Enable AVX-512 Integer Fused Multiple-Add",
163                                      [FeatureAVX512]>;
164def FeaturePKU   : SubtargetFeature<"pku", "HasPKU", "true",
165                      "Enable protection keys">;
166def FeatureVNNI    : SubtargetFeature<"avx512vnni", "HasVNNI", "true",
167                          "Enable AVX-512 Vector Neural Network Instructions",
168                                      [FeatureAVX512]>;
169def FeatureBITALG  : SubtargetFeature<"avx512bitalg", "HasBITALG", "true",
170                       "Enable AVX-512 Bit Algorithms",
171                        [FeatureBWI]>;
172def FeaturePCLMUL  : SubtargetFeature<"pclmul", "HasPCLMUL", "true",
173                         "Enable packed carry-less multiplication instructions",
174                               [FeatureSSE2]>;
175def FeatureGFNI    : SubtargetFeature<"gfni", "HasGFNI", "true",
176                         "Enable Galois Field Arithmetic Instructions",
177                               [FeatureSSE2]>;
178def FeatureVPCLMULQDQ : SubtargetFeature<"vpclmulqdq", "HasVPCLMULQDQ", "true",
179                                         "Enable vpclmulqdq instructions",
180                                         [FeatureAVX, FeaturePCLMUL]>;
181def FeatureFMA4    : SubtargetFeature<"fma4", "HasFMA4", "true",
182                                      "Enable four-operand fused multiple-add",
183                                      [FeatureAVX, FeatureSSE4A]>;
184def FeatureXOP     : SubtargetFeature<"xop", "HasXOP", "true",
185                                      "Enable XOP instructions",
186                                      [FeatureFMA4]>;
187def FeatureSSEUnalignedMem : SubtargetFeature<"sse-unaligned-mem",
188                                          "HasSSEUnalignedMem", "true",
189                      "Allow unaligned memory operands with SSE instructions">;
190def FeatureAES     : SubtargetFeature<"aes", "HasAES", "true",
191                                      "Enable AES instructions",
192                                      [FeatureSSE2]>;
193def FeatureVAES    : SubtargetFeature<"vaes", "HasVAES", "true",
194                       "Promote selected AES instructions to AVX512/AVX registers",
195                        [FeatureAVX, FeatureAES]>;
196def FeatureTBM     : SubtargetFeature<"tbm", "HasTBM", "true",
197                                      "Enable TBM instructions">;
198def FeatureLWP     : SubtargetFeature<"lwp", "HasLWP", "true",
199                                      "Enable LWP instructions">;
200def FeatureMOVBE   : SubtargetFeature<"movbe", "HasMOVBE", "true",
201                                      "Support MOVBE instruction">;
202def FeatureRDRAND  : SubtargetFeature<"rdrnd", "HasRDRAND", "true",
203                                      "Support RDRAND instruction">;
204def FeatureFSGSBase : SubtargetFeature<"fsgsbase", "HasFSGSBase", "true",
205                                       "Support FS/GS Base instructions">;
206def FeatureLZCNT   : SubtargetFeature<"lzcnt", "HasLZCNT", "true",
207                                      "Support LZCNT instruction">;
208def FeatureBMI     : SubtargetFeature<"bmi", "HasBMI", "true",
209                                      "Support BMI instructions">;
210def FeatureBMI2    : SubtargetFeature<"bmi2", "HasBMI2", "true",
211                                      "Support BMI2 instructions">;
212def FeatureRTM     : SubtargetFeature<"rtm", "HasRTM", "true",
213                                      "Support RTM instructions">;
214def FeatureADX     : SubtargetFeature<"adx", "HasADX", "true",
215                                      "Support ADX instructions">;
216def FeatureSHA     : SubtargetFeature<"sha", "HasSHA", "true",
217                                      "Enable SHA instructions",
218                                      [FeatureSSE2]>;
219def FeatureSHSTK   : SubtargetFeature<"shstk", "HasSHSTK", "true",
220                       "Support CET Shadow-Stack instructions">;
221def FeaturePRFCHW  : SubtargetFeature<"prfchw", "HasPRFCHW", "true",
222                                      "Support PRFCHW instructions">;
223def FeatureRDSEED  : SubtargetFeature<"rdseed", "HasRDSEED", "true",
224                                      "Support RDSEED instruction">;
225def FeatureLAHFSAHF : SubtargetFeature<"sahf", "HasLAHFSAHF", "true",
226                                       "Support LAHF and SAHF instructions">;
227def FeatureMWAITX  : SubtargetFeature<"mwaitx", "HasMWAITX", "true",
228                                      "Enable MONITORX/MWAITX timer functionality">;
229def FeatureCLZERO  : SubtargetFeature<"clzero", "HasCLZERO", "true",
230                                      "Enable Cache Line Zero">;
231def FeatureCLDEMOTE  : SubtargetFeature<"cldemote", "HasCLDEMOTE", "true",
232                                      "Enable Cache Demote">;
233def FeaturePTWRITE  : SubtargetFeature<"ptwrite", "HasPTWRITE", "true",
234                                      "Support ptwrite instruction">;
235def FeatureMPX     : SubtargetFeature<"mpx", "HasMPX", "true",
236                                      "Support MPX instructions">;
237def FeatureLEAForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true",
238                                     "Use LEA for adjusting the stack pointer">;
239def FeatureSlowDivide32 : SubtargetFeature<"idivl-to-divb",
240                                     "HasSlowDivide32", "true",
241                                     "Use 8-bit divide for positive values less than 256">;
242def FeatureSlowDivide64 : SubtargetFeature<"idivq-to-divl",
243                                     "HasSlowDivide64", "true",
244                                     "Use 32-bit divide for positive values less than 2^32">;
245def FeaturePadShortFunctions : SubtargetFeature<"pad-short-functions",
246                                     "PadShortFunctions", "true",
247                                     "Pad short functions">;
248def FeatureINVPCID : SubtargetFeature<"invpcid", "HasINVPCID", "true",
249                                      "Invalidate Process-Context Identifier">;
250def FeatureSGX     : SubtargetFeature<"sgx", "HasSGX", "true",
251                                      "Enable Software Guard Extensions">;
252def FeatureCLFLUSHOPT : SubtargetFeature<"clflushopt", "HasCLFLUSHOPT", "true",
253                                      "Flush A Cache Line Optimized">;
254def FeatureCLWB    : SubtargetFeature<"clwb", "HasCLWB", "true",
255                                      "Cache Line Write Back">;
256def FeatureWBNOINVD    : SubtargetFeature<"wbnoinvd", "HasWBNOINVD", "true",
257                                      "Write Back No Invalidate">;
258def FeatureRDPID : SubtargetFeature<"rdpid", "HasRDPID", "true",
259                                    "Support RDPID instructions">;
260def FeatureWAITPKG  : SubtargetFeature<"waitpkg", "HasWAITPKG", "true",
261                                      "Wait and pause enhancements">;
262// On some processors, instructions that implicitly take two memory operands are
263// slow. In practice, this means that CALL, PUSH, and POP with memory operands
264// should be avoided in favor of a MOV + register CALL/PUSH/POP.
265def FeatureSlowTwoMemOps : SubtargetFeature<"slow-two-mem-ops",
266                                     "SlowTwoMemOps", "true",
267                                     "Two memory operand instructions are slow">;
268def FeatureLEAUsesAG : SubtargetFeature<"lea-uses-ag", "LEAUsesAG", "true",
269                                   "LEA instruction needs inputs at AG stage">;
270def FeatureSlowLEA : SubtargetFeature<"slow-lea", "SlowLEA", "true",
271                                   "LEA instruction with certain arguments is slow">;
272def FeatureSlow3OpsLEA : SubtargetFeature<"slow-3ops-lea", "Slow3OpsLEA", "true",
273                                   "LEA instruction with 3 ops or certain registers is slow">;
274def FeatureSlowIncDec : SubtargetFeature<"slow-incdec", "SlowIncDec", "true",
275                                   "INC and DEC instructions are slower than ADD and SUB">;
276def FeatureSoftFloat
277    : SubtargetFeature<"soft-float", "UseSoftFloat", "true",
278                       "Use software floating point features.">;
279def FeaturePOPCNTFalseDeps : SubtargetFeature<"false-deps-popcnt",
280                                     "HasPOPCNTFalseDeps", "true",
281                                     "POPCNT has a false dependency on dest register">;
282def FeatureLZCNTFalseDeps : SubtargetFeature<"false-deps-lzcnt-tzcnt",
283                                     "HasLZCNTFalseDeps", "true",
284                                     "LZCNT/TZCNT have a false dependency on dest register">;
285def FeaturePCONFIG : SubtargetFeature<"pconfig", "HasPCONFIG", "true",
286                                      "platform configuration instruction">;
287// On recent X86 (port bound) processors, its preferable to combine to a single shuffle
288// using a variable mask over multiple fixed shuffles.
289def FeatureFastVariableShuffle
290    : SubtargetFeature<"fast-variable-shuffle",
291                       "HasFastVariableShuffle",
292                       "true", "Shuffles with variable masks are fast">;
293// On some X86 processors, there is no performance hazard to writing only the
294// lower parts of a YMM or ZMM register without clearing the upper part.
295def FeatureFastPartialYMMorZMMWrite
296    : SubtargetFeature<"fast-partial-ymm-or-zmm-write",
297                       "HasFastPartialYMMorZMMWrite",
298                       "true", "Partial writes to YMM/ZMM registers are fast">;
299// FeatureFastScalarFSQRT should be enabled if scalar FSQRT has shorter latency
300// than the corresponding NR code. FeatureFastVectorFSQRT should be enabled if
301// vector FSQRT has higher throughput than the corresponding NR code.
302// The idea is that throughput bound code is likely to be vectorized, so for
303// vectorized code we should care about the throughput of SQRT operations.
304// But if the code is scalar that probably means that the code has some kind of
305// dependency and we should care more about reducing the latency.
306def FeatureFastScalarFSQRT
307    : SubtargetFeature<"fast-scalar-fsqrt", "HasFastScalarFSQRT",
308                       "true", "Scalar SQRT is fast (disable Newton-Raphson)">;
309def FeatureFastVectorFSQRT
310    : SubtargetFeature<"fast-vector-fsqrt", "HasFastVectorFSQRT",
311                       "true", "Vector SQRT is fast (disable Newton-Raphson)">;
312// If lzcnt has equivalent latency/throughput to most simple integer ops, it can
313// be used to replace test/set sequences.
314def FeatureFastLZCNT
315    : SubtargetFeature<
316          "fast-lzcnt", "HasFastLZCNT", "true",
317          "LZCNT instructions are as fast as most simple integer ops">;
318// If the target can efficiently decode NOPs upto 11-bytes in length.
319def FeatureFast11ByteNOP
320    : SubtargetFeature<
321          "fast-11bytenop", "HasFast11ByteNOP", "true",
322          "Target can quickly decode up to 11 byte NOPs">;
323// If the target can efficiently decode NOPs upto 15-bytes in length.
324def FeatureFast15ByteNOP
325    : SubtargetFeature<
326          "fast-15bytenop", "HasFast15ByteNOP", "true",
327          "Target can quickly decode up to 15 byte NOPs">;
328// Sandy Bridge and newer processors can use SHLD with the same source on both
329// inputs to implement rotate to avoid the partial flag update of the normal
330// rotate instructions.
331def FeatureFastSHLDRotate
332    : SubtargetFeature<
333          "fast-shld-rotate", "HasFastSHLDRotate", "true",
334          "SHLD can be used as a faster rotate">;
335
336// Ivy Bridge and newer processors have enhanced REP MOVSB and STOSB (aka
337// "string operations"). See "REP String Enhancement" in the Intel Software
338// Development Manual. This feature essentially means that REP MOVSB will copy
339// using the largest available size instead of copying bytes one by one, making
340// it at least as fast as REPMOVS{W,D,Q}.
341def FeatureERMSB
342    : SubtargetFeature<
343          "ermsb", "HasERMSB", "true",
344          "REP MOVS/STOS are fast">;
345
346// Sandy Bridge and newer processors have many instructions that can be
347// fused with conditional branches and pass through the CPU as a single
348// operation.
349def FeatureMacroFusion
350    : SubtargetFeature<"macrofusion", "HasMacroFusion", "true",
351                 "Various instructions can be fused with conditional branches">;
352
353// Gather is available since Haswell (AVX2 set). So technically, we can
354// generate Gathers on all AVX2 processors. But the overhead on HSW is high.
355// Skylake Client processor has faster Gathers than HSW and performance is
356// similar to Skylake Server (AVX-512).
357def FeatureHasFastGather
358    : SubtargetFeature<"fast-gather", "HasFastGather", "true",
359                       "Indicates if gather is reasonably fast.">;
360
361def FeaturePrefer256Bit
362    : SubtargetFeature<"prefer-256-bit", "Prefer256Bit", "true",
363                       "Prefer 256-bit AVX instructions">;
364
365// Enable mitigation of some aspects of speculative execution related
366// vulnerabilities by removing speculatable indirect branches. This disables
367// jump-table formation, rewrites explicit `indirectbr` instructions into
368// `switch` instructions, and uses a special construct called a "retpoline" to
369// prevent speculation of the remaining indirect branches (indirect calls and
370// tail calls).
371def FeatureRetpoline
372    : SubtargetFeature<"retpoline", "UseRetpoline", "true",
373                       "Remove speculation of indirect branches from the "
374                       "generated code, either by avoiding them entirely or "
375                       "lowering them with a speculation blocking construct.">;
376
377// Rely on external thunks for the emitted retpoline calls. This allows users
378// to provide their own custom thunk definitions in highly specialized
379// environments such as a kernel that does boot-time hot patching.
380def FeatureRetpolineExternalThunk
381    : SubtargetFeature<
382          "retpoline-external-thunk", "UseRetpolineExternalThunk", "true",
383          "Enable retpoline, but with an externally provided thunk.",
384          [FeatureRetpoline]>;
385
386// Direct Move instructions.
387def FeatureMOVDIRI  : SubtargetFeature<"movdiri", "HasMOVDIRI", "true",
388                                       "Support movdiri instruction">;
389def FeatureMOVDIR64B : SubtargetFeature<"movdir64b", "HasMOVDIR64B", "true",
390                                        "Support movdir64b instruction">;
391
392//===----------------------------------------------------------------------===//
393// Register File Description
394//===----------------------------------------------------------------------===//
395
396include "X86RegisterInfo.td"
397include "X86RegisterBanks.td"
398
399//===----------------------------------------------------------------------===//
400// Instruction Descriptions
401//===----------------------------------------------------------------------===//
402
403include "X86Schedule.td"
404include "X86InstrInfo.td"
405include "X86SchedPredicates.td"
406
407def X86InstrInfo : InstrInfo;
408
409//===----------------------------------------------------------------------===//
410// X86 processors supported.
411//===----------------------------------------------------------------------===//
412
413include "X86ScheduleAtom.td"
414include "X86SchedSandyBridge.td"
415include "X86SchedHaswell.td"
416include "X86SchedBroadwell.td"
417include "X86ScheduleSLM.td"
418include "X86ScheduleZnver1.td"
419include "X86ScheduleBtVer2.td"
420include "X86SchedSkylakeClient.td"
421include "X86SchedSkylakeServer.td"
422
423def ProcIntelAtom : SubtargetFeature<"atom", "X86ProcFamily", "IntelAtom",
424                    "Intel Atom processors">;
425def ProcIntelSLM  : SubtargetFeature<"slm", "X86ProcFamily", "IntelSLM",
426                    "Intel Silvermont processors">;
427def ProcIntelGLM  : SubtargetFeature<"glm", "X86ProcFamily", "IntelGLM",
428                    "Intel Goldmont processors">;
429def ProcIntelGLP  : SubtargetFeature<"glp", "X86ProcFamily", "IntelGLP",
430                    "Intel Goldmont Plus processors">;
431def ProcIntelTRM  : SubtargetFeature<"tremont", "X86ProcFamily", "IntelTRM",
432                    "Intel Tremont processors">;
433def ProcIntelHSW  : SubtargetFeature<"haswell", "X86ProcFamily",
434                    "IntelHaswell", "Intel Haswell processors">;
435def ProcIntelBDW  : SubtargetFeature<"broadwell", "X86ProcFamily",
436                    "IntelBroadwell", "Intel Broadwell processors">;
437def ProcIntelSKL  : SubtargetFeature<"skylake", "X86ProcFamily",
438                    "IntelSkylake", "Intel Skylake processors">;
439def ProcIntelKNL  : SubtargetFeature<"knl", "X86ProcFamily",
440                    "IntelKNL", "Intel Knights Landing processors">;
441def ProcIntelSKX  : SubtargetFeature<"skx", "X86ProcFamily",
442                    "IntelSKX", "Intel Skylake Server processors">;
443def ProcIntelCNL  : SubtargetFeature<"cannonlake", "X86ProcFamily",
444                    "IntelCannonlake", "Intel Cannonlake processors">;
445def ProcIntelICL  : SubtargetFeature<"icelake-client", "X86ProcFamily",
446                    "IntelIcelakeClient", "Intel Icelake processors">;
447def ProcIntelICX  : SubtargetFeature<"icelake-server", "X86ProcFamily",
448                    "IntelIcelakeServer", "Intel Icelake Server processors">;
449
450class Proc<string Name, list<SubtargetFeature> Features>
451 : ProcessorModel<Name, GenericModel, Features>;
452
453def : Proc<"generic",         [FeatureX87, FeatureSlowUAMem16]>;
454def : Proc<"i386",            [FeatureX87, FeatureSlowUAMem16]>;
455def : Proc<"i486",            [FeatureX87, FeatureSlowUAMem16]>;
456def : Proc<"i586",            [FeatureX87, FeatureSlowUAMem16]>;
457def : Proc<"pentium",         [FeatureX87, FeatureSlowUAMem16]>;
458def : Proc<"pentium-mmx",     [FeatureX87, FeatureSlowUAMem16, FeatureMMX]>;
459
460def : Proc<"i686", [FeatureX87, FeatureSlowUAMem16, FeatureCMOV]>;
461def : Proc<"pentiumpro", [FeatureX87, FeatureSlowUAMem16, FeatureCMOV,
462                          FeatureNOPL]>;
463
464def : Proc<"pentium2",        [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
465                               FeatureCMOV, FeatureFXSR, FeatureNOPL]>;
466
467foreach P = ["pentium3", "pentium3m"] in {
468  def : Proc<P, [FeatureX87, FeatureSlowUAMem16, FeatureMMX, FeatureSSE1,
469                 FeatureFXSR, FeatureNOPL]>;
470}
471
472// Enable the PostRAScheduler for SSE2 and SSE3 class cpus.
473// The intent is to enable it for pentium4 which is the current default
474// processor in a vanilla 32-bit clang compilation when no specific
475// architecture is specified.  This generally gives a nice performance
476// increase on silvermont, with largely neutral behavior on other
477// contemporary large core processors.
478// pentium-m, pentium4m, prescott and nocona are included as a preventative
479// measure to avoid performance surprises, in case clang's default cpu
480// changes slightly.
481
482def : ProcessorModel<"pentium-m", GenericPostRAModel,
483                     [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
484                      FeatureSSE2, FeatureFXSR, FeatureNOPL]>;
485
486foreach P = ["pentium4", "pentium4m"] in {
487  def : ProcessorModel<P, GenericPostRAModel,
488                       [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
489                        FeatureSSE2, FeatureFXSR, FeatureNOPL]>;
490}
491
492// Intel Quark.
493def : Proc<"lakemont",        []>;
494
495// Intel Core Duo.
496def : ProcessorModel<"yonah", SandyBridgeModel,
497                     [FeatureX87, FeatureSlowUAMem16, FeatureMMX, FeatureSSE3,
498                      FeatureFXSR, FeatureNOPL]>;
499
500// NetBurst.
501def : ProcessorModel<"prescott", GenericPostRAModel,
502                     [FeatureX87, FeatureSlowUAMem16, FeatureMMX, FeatureSSE3,
503                      FeatureFXSR, FeatureNOPL]>;
504def : ProcessorModel<"nocona", GenericPostRAModel, [
505  FeatureX87,
506  FeatureSlowUAMem16,
507  FeatureMMX,
508  FeatureSSE3,
509  FeatureFXSR,
510  FeatureNOPL,
511  FeatureCMPXCHG16B
512]>;
513
514// Intel Core 2 Solo/Duo.
515def : ProcessorModel<"core2", SandyBridgeModel, [
516  FeatureX87,
517  FeatureSlowUAMem16,
518  FeatureMMX,
519  FeatureSSSE3,
520  FeatureFXSR,
521  FeatureNOPL,
522  FeatureCMPXCHG16B,
523  FeatureLAHFSAHF,
524  FeatureMacroFusion
525]>;
526def : ProcessorModel<"penryn", SandyBridgeModel, [
527  FeatureX87,
528  FeatureSlowUAMem16,
529  FeatureMMX,
530  FeatureSSE41,
531  FeatureFXSR,
532  FeatureNOPL,
533  FeatureCMPXCHG16B,
534  FeatureLAHFSAHF,
535  FeatureMacroFusion
536]>;
537
538// Atom CPUs.
539class BonnellProc<string Name> : ProcessorModel<Name, AtomModel, [
540  ProcIntelAtom,
541  FeatureX87,
542  FeatureSlowUAMem16,
543  FeatureMMX,
544  FeatureSSSE3,
545  FeatureFXSR,
546  FeatureNOPL,
547  FeatureCMPXCHG16B,
548  FeatureMOVBE,
549  FeatureLEAForSP,
550  FeatureSlowDivide32,
551  FeatureSlowDivide64,
552  FeatureSlowTwoMemOps,
553  FeatureLEAUsesAG,
554  FeaturePadShortFunctions,
555  FeatureLAHFSAHF
556]>;
557def : BonnellProc<"bonnell">;
558def : BonnellProc<"atom">; // Pin the generic name to the baseline.
559
560class SilvermontProc<string Name> : ProcessorModel<Name, SLMModel, [
561  ProcIntelSLM,
562  FeatureX87,
563  FeatureMMX,
564  FeatureSSE42,
565  FeatureFXSR,
566  FeatureNOPL,
567  FeatureCMPXCHG16B,
568  FeatureMOVBE,
569  FeaturePOPCNT,
570  FeaturePCLMUL,
571  FeatureAES,
572  FeatureSlowDivide64,
573  FeatureSlowTwoMemOps,
574  FeaturePRFCHW,
575  FeatureSlowLEA,
576  FeatureSlowIncDec,
577  FeatureSlowPMULLD,
578  FeatureRDRAND,
579  FeatureLAHFSAHF,
580  FeaturePOPCNTFalseDeps
581]>;
582def : SilvermontProc<"silvermont">;
583def : SilvermontProc<"slm">; // Legacy alias.
584
585class ProcessorFeatures<list<SubtargetFeature> Inherited,
586                        list<SubtargetFeature> NewFeatures> {
587  list<SubtargetFeature> Value = !listconcat(Inherited, NewFeatures);
588}
589
590class ProcModel<string Name, SchedMachineModel Model,
591                list<SubtargetFeature> ProcFeatures,
592                list<SubtargetFeature> OtherFeatures> :
593  ProcessorModel<Name, Model, !listconcat(ProcFeatures, OtherFeatures)>;
594
595def GLMFeatures : ProcessorFeatures<[], [
596  FeatureX87,
597  FeatureMMX,
598  FeatureSSE42,
599  FeatureFXSR,
600  FeatureNOPL,
601  FeatureCMPXCHG16B,
602  FeatureMOVBE,
603  FeaturePOPCNT,
604  FeaturePCLMUL,
605  FeatureAES,
606  FeaturePRFCHW,
607  FeatureSlowTwoMemOps,
608  FeatureSlowLEA,
609  FeatureSlowIncDec,
610  FeatureLAHFSAHF,
611  FeatureMPX,
612  FeatureSHA,
613  FeatureRDRAND,
614  FeatureRDSEED,
615  FeatureXSAVE,
616  FeatureXSAVEOPT,
617  FeatureXSAVEC,
618  FeatureXSAVES,
619  FeatureCLFLUSHOPT,
620  FeatureFSGSBase
621]>;
622
623class GoldmontProc<string Name> : ProcModel<Name, SLMModel,
624      GLMFeatures.Value, [
625  ProcIntelGLM,
626  FeaturePOPCNTFalseDeps
627]>;
628def : GoldmontProc<"goldmont">;
629
630def GLPFeatures : ProcessorFeatures<GLMFeatures.Value, [
631  FeaturePTWRITE,
632  FeatureRDPID,
633  FeatureSGX
634]>;
635
636class GoldmontPlusProc<string Name> : ProcModel<Name, SLMModel,
637      GLPFeatures.Value, [
638  ProcIntelGLP
639]>;
640def : GoldmontPlusProc<"goldmont-plus">;
641
642class TremontProc<string Name> : ProcModel<Name, SLMModel,
643      GLPFeatures.Value, [
644  ProcIntelTRM,
645  FeatureCLDEMOTE,
646  FeatureGFNI,
647  FeatureMOVDIRI,
648  FeatureMOVDIR64B,
649  FeatureWAITPKG
650]>;
651def : TremontProc<"tremont">;
652
653// "Arrandale" along with corei3 and corei5
654class NehalemProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
655  FeatureX87,
656  FeatureMMX,
657  FeatureSSE42,
658  FeatureFXSR,
659  FeatureNOPL,
660  FeatureCMPXCHG16B,
661  FeaturePOPCNT,
662  FeatureLAHFSAHF,
663  FeatureMacroFusion
664]>;
665def : NehalemProc<"nehalem">;
666def : NehalemProc<"corei7">;
667
668// Westmere is a similar machine to nehalem with some additional features.
669// Westmere is the corei3/i5/i7 path from nehalem to sandybridge
670class WestmereProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
671  FeatureX87,
672  FeatureMMX,
673  FeatureSSE42,
674  FeatureFXSR,
675  FeatureNOPL,
676  FeatureCMPXCHG16B,
677  FeaturePOPCNT,
678  FeatureAES,
679  FeaturePCLMUL,
680  FeatureLAHFSAHF,
681  FeatureMacroFusion
682]>;
683def : WestmereProc<"westmere">;
684
685// SSE is not listed here since llvm treats AVX as a reimplementation of SSE,
686// rather than a superset.
687def SNBFeatures : ProcessorFeatures<[], [
688  FeatureX87,
689  FeatureMMX,
690  FeatureAVX,
691  FeatureFXSR,
692  FeatureNOPL,
693  FeatureCMPXCHG16B,
694  FeaturePOPCNT,
695  FeatureAES,
696  FeatureSlowDivide64,
697  FeaturePCLMUL,
698  FeatureXSAVE,
699  FeatureXSAVEOPT,
700  FeatureLAHFSAHF,
701  FeatureSlow3OpsLEA,
702  FeatureFastScalarFSQRT,
703  FeatureFastSHLDRotate,
704  FeatureSlowIncDec,
705  FeatureMacroFusion
706]>;
707
708class SandyBridgeProc<string Name> : ProcModel<Name, SandyBridgeModel,
709                                               SNBFeatures.Value, [
710  FeatureSlowUAMem32,
711  FeaturePOPCNTFalseDeps
712]>;
713def : SandyBridgeProc<"sandybridge">;
714def : SandyBridgeProc<"corei7-avx">; // Legacy alias.
715
716def IVBFeatures : ProcessorFeatures<SNBFeatures.Value, [
717  FeatureRDRAND,
718  FeatureF16C,
719  FeatureFSGSBase
720]>;
721
722class IvyBridgeProc<string Name> : ProcModel<Name, SandyBridgeModel,
723                                             IVBFeatures.Value, [
724  FeatureSlowUAMem32,
725  FeaturePOPCNTFalseDeps
726]>;
727def : IvyBridgeProc<"ivybridge">;
728def : IvyBridgeProc<"core-avx-i">; // Legacy alias.
729
730def HSWFeatures : ProcessorFeatures<IVBFeatures.Value, [
731  FeatureAVX2,
732  FeatureBMI,
733  FeatureBMI2,
734  FeatureERMSB,
735  FeatureFMA,
736  FeatureINVPCID,
737  FeatureLZCNT,
738  FeatureMOVBE,
739  FeatureFastVariableShuffle
740]>;
741
742class HaswellProc<string Name> : ProcModel<Name, HaswellModel,
743                                           HSWFeatures.Value, [
744  ProcIntelHSW,
745  FeaturePOPCNTFalseDeps,
746  FeatureLZCNTFalseDeps
747]>;
748def : HaswellProc<"haswell">;
749def : HaswellProc<"core-avx2">; // Legacy alias.
750
751def BDWFeatures : ProcessorFeatures<HSWFeatures.Value, [
752  FeatureADX,
753  FeatureRDSEED,
754  FeaturePRFCHW
755]>;
756class BroadwellProc<string Name> : ProcModel<Name, BroadwellModel,
757                                             BDWFeatures.Value, [
758  ProcIntelBDW,
759  FeaturePOPCNTFalseDeps,
760  FeatureLZCNTFalseDeps
761]>;
762def : BroadwellProc<"broadwell">;
763
764def SKLFeatures : ProcessorFeatures<BDWFeatures.Value, [
765  FeatureMPX,
766  FeatureRTM,
767  FeatureXSAVEC,
768  FeatureXSAVES,
769  FeatureCLFLUSHOPT,
770  FeatureFastVectorFSQRT
771]>;
772
773class SkylakeClientProc<string Name> : ProcModel<Name, SkylakeClientModel,
774                                                 SKLFeatures.Value, [
775  ProcIntelSKL,
776  FeatureHasFastGather,
777  FeaturePOPCNTFalseDeps,
778  FeatureSGX
779]>;
780def : SkylakeClientProc<"skylake">;
781
782def KNLFeatures : ProcessorFeatures<IVBFeatures.Value, [
783  FeatureAVX512,
784  FeatureERI,
785  FeatureCDI,
786  FeaturePFI,
787  FeaturePREFETCHWT1,
788  FeatureADX,
789  FeatureRDSEED,
790  FeatureMOVBE,
791  FeatureLZCNT,
792  FeatureBMI,
793  FeatureBMI2,
794  FeatureFMA,
795  FeaturePRFCHW
796]>;
797
798// FIXME: define KNL model
799class KnightsLandingProc<string Name> : ProcModel<Name, HaswellModel,
800                                                  KNLFeatures.Value, [
801  ProcIntelKNL,
802  FeatureSlowTwoMemOps,
803  FeatureFastPartialYMMorZMMWrite,
804  FeatureHasFastGather
805]>;
806def : KnightsLandingProc<"knl">;
807
808class KnightsMillProc<string Name> : ProcModel<Name, HaswellModel,
809                                               KNLFeatures.Value, [
810  ProcIntelKNL,
811  FeatureSlowTwoMemOps,
812  FeatureFastPartialYMMorZMMWrite,
813  FeatureHasFastGather,
814  FeatureVPOPCNTDQ
815]>;
816def : KnightsMillProc<"knm">; // TODO Add AVX5124FMAPS/AVX5124VNNIW features
817
818def SKXFeatures : ProcessorFeatures<SKLFeatures.Value, [
819  FeatureAVX512,
820  FeatureCDI,
821  FeatureDQI,
822  FeatureBWI,
823  FeatureVLX,
824  FeaturePKU,
825  FeatureCLWB
826]>;
827
828class SkylakeServerProc<string Name> : ProcModel<Name, SkylakeServerModel,
829                                                 SKXFeatures.Value, [
830  ProcIntelSKX,
831  FeatureHasFastGather,
832  FeaturePOPCNTFalseDeps
833]>;
834def : SkylakeServerProc<"skylake-avx512">;
835def : SkylakeServerProc<"skx">; // Legacy alias.
836
837def CNLFeatures : ProcessorFeatures<SKLFeatures.Value, [
838  FeatureAVX512,
839  FeatureCDI,
840  FeatureDQI,
841  FeatureBWI,
842  FeatureVLX,
843  FeaturePKU,
844  FeatureVBMI,
845  FeatureIFMA,
846  FeatureSHA,
847  FeatureSGX
848]>;
849
850class CannonlakeProc<string Name> : ProcModel<Name, SkylakeServerModel,
851                                              CNLFeatures.Value, [
852  ProcIntelCNL,
853  FeatureHasFastGather
854]>;
855def : CannonlakeProc<"cannonlake">;
856
857def ICLFeatures : ProcessorFeatures<CNLFeatures.Value, [
858  FeatureBITALG,
859  FeatureVAES,
860  FeatureVBMI2,
861  FeatureVNNI,
862  FeatureVPCLMULQDQ,
863  FeatureVPOPCNTDQ,
864  FeatureGFNI,
865  FeatureCLWB,
866  FeatureRDPID
867]>;
868
869class IcelakeClientProc<string Name> : ProcModel<Name, SkylakeServerModel,
870                                                 ICLFeatures.Value, [
871  ProcIntelICL,
872  FeatureHasFastGather
873]>;
874def : IcelakeClientProc<"icelake-client">;
875
876class IcelakeServerProc<string Name> : ProcModel<Name, SkylakeServerModel,
877                                                 ICLFeatures.Value, [
878  ProcIntelICX,
879  FeaturePCONFIG,
880  FeatureWBNOINVD,
881  FeatureHasFastGather
882]>;
883def : IcelakeServerProc<"icelake-server">;
884
885// AMD CPUs.
886
887def : Proc<"k6",              [FeatureX87, FeatureSlowUAMem16, FeatureMMX]>;
888def : Proc<"k6-2",            [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>;
889def : Proc<"k6-3",            [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>;
890
891foreach P = ["athlon", "athlon-tbird"] in {
892  def : Proc<P, [FeatureX87, FeatureSlowUAMem16, Feature3DNowA,
893                 FeatureNOPL, FeatureSlowSHLD]>;
894}
895
896foreach P = ["athlon-4", "athlon-xp", "athlon-mp"] in {
897  def : Proc<P, [FeatureX87, FeatureSlowUAMem16, FeatureSSE1,
898                 Feature3DNowA, FeatureFXSR, FeatureNOPL, FeatureSlowSHLD]>;
899}
900
901foreach P = ["k8", "opteron", "athlon64", "athlon-fx"] in {
902  def : Proc<P, [FeatureX87, FeatureSlowUAMem16, FeatureSSE2, Feature3DNowA,
903                 FeatureFXSR, FeatureNOPL, Feature64Bit, FeatureSlowSHLD]>;
904}
905
906foreach P = ["k8-sse3", "opteron-sse3", "athlon64-sse3"] in {
907  def : Proc<P, [FeatureX87, FeatureSlowUAMem16, FeatureSSE3, Feature3DNowA,
908                 FeatureFXSR, FeatureNOPL, FeatureCMPXCHG16B, FeatureSlowSHLD]>;
909}
910
911foreach P = ["amdfam10", "barcelona"] in {
912  def : Proc<P, [FeatureX87, FeatureSSE4A, Feature3DNowA, FeatureFXSR,
913                 FeatureNOPL, FeatureCMPXCHG16B, FeatureLZCNT, FeaturePOPCNT,
914                 FeatureSlowSHLD, FeatureLAHFSAHF]>;
915}
916
917// Bobcat
918def : Proc<"btver1", [
919  FeatureX87,
920  FeatureMMX,
921  FeatureSSSE3,
922  FeatureSSE4A,
923  FeatureFXSR,
924  FeatureNOPL,
925  FeatureCMPXCHG16B,
926  FeaturePRFCHW,
927  FeatureLZCNT,
928  FeaturePOPCNT,
929  FeatureSlowSHLD,
930  FeatureLAHFSAHF,
931  FeatureFast15ByteNOP
932]>;
933
934// Jaguar
935def : ProcessorModel<"btver2", BtVer2Model, [
936  FeatureX87,
937  FeatureMMX,
938  FeatureAVX,
939  FeatureFXSR,
940  FeatureNOPL,
941  FeatureSSE4A,
942  FeatureCMPXCHG16B,
943  FeaturePRFCHW,
944  FeatureAES,
945  FeaturePCLMUL,
946  FeatureBMI,
947  FeatureF16C,
948  FeatureMOVBE,
949  FeatureLZCNT,
950  FeatureFastLZCNT,
951  FeaturePOPCNT,
952  FeatureXSAVE,
953  FeatureXSAVEOPT,
954  FeatureSlowSHLD,
955  FeatureLAHFSAHF,
956  FeatureFast15ByteNOP,
957  FeatureFastPartialYMMorZMMWrite
958]>;
959
960// Bulldozer
961def : Proc<"bdver1", [
962  FeatureX87,
963  FeatureXOP,
964  FeatureFMA4,
965  FeatureCMPXCHG16B,
966  FeatureAES,
967  FeaturePRFCHW,
968  FeaturePCLMUL,
969  FeatureMMX,
970  FeatureAVX,
971  FeatureFXSR,
972  FeatureNOPL,
973  FeatureSSE4A,
974  FeatureLZCNT,
975  FeaturePOPCNT,
976  FeatureXSAVE,
977  FeatureLWP,
978  FeatureSlowSHLD,
979  FeatureLAHFSAHF,
980  FeatureFast11ByteNOP,
981  FeatureMacroFusion
982]>;
983// Piledriver
984def : Proc<"bdver2", [
985  FeatureX87,
986  FeatureXOP,
987  FeatureFMA4,
988  FeatureCMPXCHG16B,
989  FeatureAES,
990  FeaturePRFCHW,
991  FeaturePCLMUL,
992  FeatureMMX,
993  FeatureAVX,
994  FeatureFXSR,
995  FeatureNOPL,
996  FeatureSSE4A,
997  FeatureF16C,
998  FeatureLZCNT,
999  FeaturePOPCNT,
1000  FeatureXSAVE,
1001  FeatureBMI,
1002  FeatureTBM,
1003  FeatureLWP,
1004  FeatureFMA,
1005  FeatureSlowSHLD,
1006  FeatureLAHFSAHF,
1007  FeatureFast11ByteNOP,
1008  FeatureMacroFusion
1009]>;
1010
1011// Steamroller
1012def : Proc<"bdver3", [
1013  FeatureX87,
1014  FeatureXOP,
1015  FeatureFMA4,
1016  FeatureCMPXCHG16B,
1017  FeatureAES,
1018  FeaturePRFCHW,
1019  FeaturePCLMUL,
1020  FeatureMMX,
1021  FeatureAVX,
1022  FeatureFXSR,
1023  FeatureNOPL,
1024  FeatureSSE4A,
1025  FeatureF16C,
1026  FeatureLZCNT,
1027  FeaturePOPCNT,
1028  FeatureXSAVE,
1029  FeatureBMI,
1030  FeatureTBM,
1031  FeatureLWP,
1032  FeatureFMA,
1033  FeatureXSAVEOPT,
1034  FeatureSlowSHLD,
1035  FeatureFSGSBase,
1036  FeatureLAHFSAHF,
1037  FeatureFast11ByteNOP,
1038  FeatureMacroFusion
1039]>;
1040
1041// Excavator
1042def : Proc<"bdver4", [
1043  FeatureX87,
1044  FeatureMMX,
1045  FeatureAVX2,
1046  FeatureFXSR,
1047  FeatureNOPL,
1048  FeatureXOP,
1049  FeatureFMA4,
1050  FeatureCMPXCHG16B,
1051  FeatureAES,
1052  FeaturePRFCHW,
1053  FeaturePCLMUL,
1054  FeatureF16C,
1055  FeatureLZCNT,
1056  FeaturePOPCNT,
1057  FeatureXSAVE,
1058  FeatureBMI,
1059  FeatureBMI2,
1060  FeatureTBM,
1061  FeatureLWP,
1062  FeatureFMA,
1063  FeatureXSAVEOPT,
1064  FeatureSlowSHLD,
1065  FeatureFSGSBase,
1066  FeatureLAHFSAHF,
1067  FeatureFast11ByteNOP,
1068  FeatureMWAITX,
1069  FeatureMacroFusion
1070]>;
1071
1072// Znver1
1073def: ProcessorModel<"znver1", Znver1Model, [
1074  FeatureADX,
1075  FeatureAES,
1076  FeatureAVX2,
1077  FeatureBMI,
1078  FeatureBMI2,
1079  FeatureCLFLUSHOPT,
1080  FeatureCLZERO,
1081  FeatureCMPXCHG16B,
1082  FeatureF16C,
1083  FeatureFMA,
1084  FeatureFSGSBase,
1085  FeatureFXSR,
1086  FeatureNOPL,
1087  FeatureFastLZCNT,
1088  FeatureLAHFSAHF,
1089  FeatureLZCNT,
1090  FeatureFast15ByteNOP,
1091  FeatureMacroFusion,
1092  FeatureMMX,
1093  FeatureMOVBE,
1094  FeatureMWAITX,
1095  FeaturePCLMUL,
1096  FeaturePOPCNT,
1097  FeaturePRFCHW,
1098  FeatureRDRAND,
1099  FeatureRDSEED,
1100  FeatureSHA,
1101  FeatureSSE4A,
1102  FeatureSlowSHLD,
1103  FeatureX87,
1104  FeatureXSAVE,
1105  FeatureXSAVEC,
1106  FeatureXSAVEOPT,
1107  FeatureXSAVES]>;
1108
1109def : Proc<"geode",           [FeatureX87, FeatureSlowUAMem16, Feature3DNowA]>;
1110
1111def : Proc<"winchip-c6",      [FeatureX87, FeatureSlowUAMem16, FeatureMMX]>;
1112def : Proc<"winchip2",        [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>;
1113def : Proc<"c3",              [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>;
1114def : Proc<"c3-2",            [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
1115                               FeatureSSE1, FeatureFXSR]>;
1116
1117// We also provide a generic 64-bit specific x86 processor model which tries to
1118// be good for modern chips without enabling instruction set encodings past the
1119// basic SSE2 and 64-bit ones. It disables slow things from any mainstream and
1120// modern 64-bit x86 chip, and enables features that are generally beneficial.
1121//
1122// We currently use the Sandy Bridge model as the default scheduling model as
1123// we use it across Nehalem, Westmere, Sandy Bridge, and Ivy Bridge which
1124// covers a huge swath of x86 processors. If there are specific scheduling
1125// knobs which need to be tuned differently for AMD chips, we might consider
1126// forming a common base for them.
1127def : ProcessorModel<"x86-64", SandyBridgeModel, [
1128  FeatureX87,
1129  FeatureMMX,
1130  FeatureSSE2,
1131  FeatureFXSR,
1132  FeatureNOPL,
1133  Feature64Bit,
1134  FeatureSlow3OpsLEA,
1135  FeatureSlowIncDec,
1136  FeatureMacroFusion
1137]>;
1138
1139//===----------------------------------------------------------------------===//
1140// Calling Conventions
1141//===----------------------------------------------------------------------===//
1142
1143include "X86CallingConv.td"
1144
1145
1146//===----------------------------------------------------------------------===//
1147// Assembly Parser
1148//===----------------------------------------------------------------------===//
1149
1150def ATTAsmParserVariant : AsmParserVariant {
1151  int Variant = 0;
1152
1153  // Variant name.
1154  string Name = "att";
1155
1156  // Discard comments in assembly strings.
1157  string CommentDelimiter = "#";
1158
1159  // Recognize hard coded registers.
1160  string RegisterPrefix = "%";
1161}
1162
1163def IntelAsmParserVariant : AsmParserVariant {
1164  int Variant = 1;
1165
1166  // Variant name.
1167  string Name = "intel";
1168
1169  // Discard comments in assembly strings.
1170  string CommentDelimiter = ";";
1171
1172  // Recognize hard coded registers.
1173  string RegisterPrefix = "";
1174}
1175
1176//===----------------------------------------------------------------------===//
1177// Assembly Printers
1178//===----------------------------------------------------------------------===//
1179
1180// The X86 target supports two different syntaxes for emitting machine code.
1181// This is controlled by the -x86-asm-syntax={att|intel}
1182def ATTAsmWriter : AsmWriter {
1183  string AsmWriterClassName  = "ATTInstPrinter";
1184  int Variant = 0;
1185}
1186def IntelAsmWriter : AsmWriter {
1187  string AsmWriterClassName  = "IntelInstPrinter";
1188  int Variant = 1;
1189}
1190
1191def X86 : Target {
1192  // Information about the instructions...
1193  let InstructionSet = X86InstrInfo;
1194  let AssemblyParserVariants = [ATTAsmParserVariant, IntelAsmParserVariant];
1195  let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];
1196  let AllowRegisterRenaming = 1;
1197}
1198
1199//===----------------------------------------------------------------------===//
1200// Pfm Counters
1201//===----------------------------------------------------------------------===//
1202
1203include "X86PfmCounters.td"
1204