1
2 /*
3 * QEMU OldWorld PowerMac (currently ~G3 Beige) hardware System Emulator
4 *
5 * Copyright (c) 2004-2007 Fabrice Bellard
6 * Copyright (c) 2007 Jocelyn Mayer
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 */
26
27 #include "qemu/osdep.h"
28 #include "qemu-common.h"
29 #include "qemu/datadir.h"
30 #include "qemu/units.h"
31 #include "qapi/error.h"
32 #include "hw/ppc/ppc.h"
33 #include "hw/qdev-properties.h"
34 #include "mac.h"
35 #include "hw/input/adb.h"
36 #include "sysemu/sysemu.h"
37 #include "net/net.h"
38 #include "hw/isa/isa.h"
39 #include "hw/pci/pci.h"
40 #include "hw/pci/pci_host.h"
41 #include "hw/boards.h"
42 #include "hw/nvram/fw_cfg.h"
43 #include "hw/char/escc.h"
44 #include "hw/misc/macio/macio.h"
45 #include "hw/loader.h"
46 #include "hw/fw-path-provider.h"
47 #include "elf.h"
48 #include "qemu/error-report.h"
49 #include "sysemu/kvm.h"
50 #include "sysemu/reset.h"
51 #include "kvm_ppc.h"
52 #include "exec/address-spaces.h"
53
54 #define MAX_IDE_BUS 2
55 #define CFG_ADDR 0xf0000510
56 #define TBFREQ 16600000UL
57 #define CLOCKFREQ 266000000UL
58 #define BUSFREQ 66000000UL
59
60 #define NDRV_VGA_FILENAME "qemu_vga.ndrv"
61
62 #define GRACKLE_BASE 0xfec00000
63 #define PROM_BASE 0xffc00000
64 #define PROM_SIZE (4 * MiB)
65
66 /* FreeBSD headers define this */
67 #ifdef round_page
68 #undef round_page
69 #endif
70
fw_cfg_boot_set(void * opaque,const char * boot_device,Error ** errp)71 static void fw_cfg_boot_set(void *opaque, const char *boot_device,
72 Error **errp)
73 {
74 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
75 }
76
translate_kernel_address(void * opaque,uint64_t addr)77 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
78 {
79 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
80 }
81
ppc_heathrow_reset(void * opaque)82 static void ppc_heathrow_reset(void *opaque)
83 {
84 PowerPCCPU *cpu = opaque;
85
86 cpu_reset(CPU(cpu));
87 }
88
ppc_heathrow_init(MachineState * machine)89 static void ppc_heathrow_init(MachineState *machine)
90 {
91 ram_addr_t ram_size = machine->ram_size;
92 const char *bios_name = machine->firmware ?: PROM_FILENAME;
93 const char *boot_device = machine->boot_order;
94 PowerPCCPU *cpu = NULL;
95 CPUPPCState *env = NULL;
96 char *filename;
97 int i;
98 MemoryRegion *bios = g_new(MemoryRegion, 1);
99 uint32_t kernel_base, initrd_base, cmdline_base = 0;
100 int32_t kernel_size, initrd_size;
101 PCIBus *pci_bus;
102 PCIDevice *macio;
103 MACIOIDEState *macio_ide;
104 ESCCState *escc;
105 SysBusDevice *s;
106 DeviceState *dev, *pic_dev, *grackle_dev;
107 BusState *adb_bus;
108 uint64_t bios_addr;
109 int bios_size;
110 unsigned int smp_cpus = machine->smp.cpus;
111 uint16_t ppc_boot_device;
112 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
113 void *fw_cfg;
114 uint64_t tbfreq;
115
116 /* init CPUs */
117 for (i = 0; i < smp_cpus; i++) {
118 cpu = POWERPC_CPU(cpu_create(machine->cpu_type));
119 env = &cpu->env;
120
121 /* Set time-base frequency to 16.6 Mhz */
122 cpu_ppc_tb_init(env, TBFREQ);
123 qemu_register_reset(ppc_heathrow_reset, cpu);
124 }
125
126 /* allocate RAM */
127 if (ram_size > 2047 * MiB) {
128 error_report("Too much memory for this machine: %" PRId64 " MB, "
129 "maximum 2047 MB", ram_size / MiB);
130 exit(1);
131 }
132
133 memory_region_add_subregion(get_system_memory(), 0, machine->ram);
134
135 /* allocate and load firmware ROM */
136 memory_region_init_rom(bios, NULL, "ppc_heathrow.bios", PROM_SIZE,
137 &error_fatal);
138 memory_region_add_subregion(get_system_memory(), PROM_BASE, bios);
139
140 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
141 if (filename) {
142 /* Load OpenBIOS (ELF) */
143 bios_size = load_elf(filename, NULL, NULL, NULL, NULL, &bios_addr,
144 NULL, NULL, 1, PPC_ELF_MACHINE, 0, 0);
145 /* Unfortunately, load_elf sign-extends reading elf32 */
146 bios_addr = (uint32_t)bios_addr;
147
148 if (bios_size <= 0) {
149 /* or if could not load ELF try loading a binary ROM image */
150 bios_size = load_image_targphys(filename, PROM_BASE, PROM_SIZE);
151 bios_addr = PROM_BASE;
152 }
153 g_free(filename);
154 } else {
155 bios_size = -1;
156 }
157 if (bios_size < 0 || bios_addr - PROM_BASE + bios_size > PROM_SIZE) {
158 error_report("could not load PowerPC bios '%s'", bios_name);
159 exit(1);
160 }
161
162 if (machine->kernel_filename) {
163 int bswap_needed;
164
165 #ifdef BSWAP_NEEDED
166 bswap_needed = 1;
167 #else
168 bswap_needed = 0;
169 #endif
170 kernel_base = KERNEL_LOAD_ADDR;
171 kernel_size = load_elf(machine->kernel_filename, NULL,
172 translate_kernel_address, NULL, NULL, NULL,
173 NULL, NULL, 1, PPC_ELF_MACHINE, 0, 0);
174 if (kernel_size < 0)
175 kernel_size = load_aout(machine->kernel_filename, kernel_base,
176 ram_size - kernel_base, bswap_needed,
177 TARGET_PAGE_SIZE);
178 if (kernel_size < 0)
179 kernel_size = load_image_targphys(machine->kernel_filename,
180 kernel_base,
181 ram_size - kernel_base);
182 if (kernel_size < 0) {
183 error_report("could not load kernel '%s'",
184 machine->kernel_filename);
185 exit(1);
186 }
187 /* load initrd */
188 if (machine->initrd_filename) {
189 initrd_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size +
190 KERNEL_GAP);
191 initrd_size = load_image_targphys(machine->initrd_filename,
192 initrd_base,
193 ram_size - initrd_base);
194 if (initrd_size < 0) {
195 error_report("could not load initial ram disk '%s'",
196 machine->initrd_filename);
197 exit(1);
198 }
199 cmdline_base = TARGET_PAGE_ALIGN(initrd_base + initrd_size);
200 } else {
201 initrd_base = 0;
202 initrd_size = 0;
203 cmdline_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + KERNEL_GAP);
204 }
205 ppc_boot_device = 'm';
206 } else {
207 kernel_base = 0;
208 kernel_size = 0;
209 initrd_base = 0;
210 initrd_size = 0;
211 ppc_boot_device = '\0';
212 for (i = 0; boot_device[i] != '\0'; i++) {
213 /* TOFIX: for now, the second IDE channel is not properly
214 * used by OHW. The Mac floppy disk are not emulated.
215 * For now, OHW cannot boot from the network.
216 */
217 #if 0
218 if (boot_device[i] >= 'a' && boot_device[i] <= 'f') {
219 ppc_boot_device = boot_device[i];
220 break;
221 }
222 #else
223 if (boot_device[i] >= 'c' && boot_device[i] <= 'd') {
224 ppc_boot_device = boot_device[i];
225 break;
226 }
227 #endif
228 }
229 if (ppc_boot_device == '\0') {
230 error_report("No valid boot device for G3 Beige machine");
231 exit(1);
232 }
233 }
234
235 /* Timebase Frequency */
236 if (kvm_enabled()) {
237 tbfreq = kvmppc_get_tbfreq();
238 } else {
239 tbfreq = TBFREQ;
240 }
241
242 /* Grackle PCI host bridge */
243 grackle_dev = qdev_new(TYPE_GRACKLE_PCI_HOST_BRIDGE);
244 qdev_prop_set_uint32(grackle_dev, "ofw-addr", 0x80000000);
245 s = SYS_BUS_DEVICE(grackle_dev);
246 sysbus_realize_and_unref(s, &error_fatal);
247
248 sysbus_mmio_map(s, 0, GRACKLE_BASE);
249 sysbus_mmio_map(s, 1, GRACKLE_BASE + 0x200000);
250 /* PCI hole */
251 memory_region_add_subregion(get_system_memory(), 0x80000000ULL,
252 sysbus_mmio_get_region(s, 2));
253 /* Register 2 MB of ISA IO space */
254 memory_region_add_subregion(get_system_memory(), 0xfe000000,
255 sysbus_mmio_get_region(s, 3));
256
257 pci_bus = PCI_HOST_BRIDGE(grackle_dev)->bus;
258
259 /* MacIO */
260 macio = pci_new(PCI_DEVFN(16, 0), TYPE_OLDWORLD_MACIO);
261 dev = DEVICE(macio);
262 qdev_prop_set_uint64(dev, "frequency", tbfreq);
263
264 escc = ESCC(object_resolve_path_component(OBJECT(macio), "escc"));
265 qdev_prop_set_chr(DEVICE(escc), "chrA", serial_hd(0));
266 qdev_prop_set_chr(DEVICE(escc), "chrB", serial_hd(1));
267
268 pci_realize_and_unref(macio, pci_bus, &error_fatal);
269
270 pic_dev = DEVICE(object_resolve_path_component(OBJECT(macio), "pic"));
271 for (i = 0; i < 4; i++) {
272 qdev_connect_gpio_out(grackle_dev, i,
273 qdev_get_gpio_in(pic_dev, 0x15 + i));
274 }
275
276 /* Connect the heathrow PIC outputs to the 6xx bus */
277 for (i = 0; i < smp_cpus; i++) {
278 switch (PPC_INPUT(env)) {
279 case PPC_FLAGS_INPUT_6xx:
280 /* XXX: we register only 1 output pin for heathrow PIC */
281 qdev_connect_gpio_out(pic_dev, 0,
282 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]);
283 break;
284 default:
285 error_report("Bus model not supported on OldWorld Mac machine");
286 exit(1);
287 }
288 }
289
290 pci_vga_init(pci_bus);
291
292 for (i = 0; i < nb_nics; i++) {
293 pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL);
294 }
295
296 /* MacIO IDE */
297 ide_drive_get(hd, ARRAY_SIZE(hd));
298 macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio),
299 "ide[0]"));
300 macio_ide_init_drives(macio_ide, hd);
301
302 macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio),
303 "ide[1]"));
304 macio_ide_init_drives(macio_ide, &hd[MAX_IDE_DEVS]);
305
306 /* MacIO CUDA/ADB */
307 dev = DEVICE(object_resolve_path_component(OBJECT(macio), "cuda"));
308 adb_bus = qdev_get_child_bus(dev, "adb.0");
309 dev = qdev_new(TYPE_ADB_KEYBOARD);
310 qdev_realize_and_unref(dev, adb_bus, &error_fatal);
311 dev = qdev_new(TYPE_ADB_MOUSE);
312 qdev_realize_and_unref(dev, adb_bus, &error_fatal);
313
314 if (machine_usb(machine)) {
315 pci_create_simple(pci_bus, -1, "pci-ohci");
316 }
317
318 if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8)
319 graphic_depth = 15;
320
321 /* No PCI init: the BIOS will do it */
322
323 dev = qdev_new(TYPE_FW_CFG_MEM);
324 fw_cfg = FW_CFG(dev);
325 qdev_prop_set_uint32(dev, "data_width", 1);
326 qdev_prop_set_bit(dev, "dma_enabled", false);
327 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG,
328 OBJECT(fw_cfg));
329 s = SYS_BUS_DEVICE(dev);
330 sysbus_realize_and_unref(s, &error_fatal);
331 sysbus_mmio_map(s, 0, CFG_ADDR);
332 sysbus_mmio_map(s, 1, CFG_ADDR + 2);
333
334 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
335 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)machine->smp.max_cpus);
336 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
337 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_HEATHROW);
338 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base);
339 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
340 if (machine->kernel_cmdline) {
341 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base);
342 pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE,
343 machine->kernel_cmdline);
344 } else {
345 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
346 }
347 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base);
348 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
349 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device);
350
351 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width);
352 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height);
353 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth);
354
355 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled());
356 if (kvm_enabled()) {
357 uint8_t *hypercall;
358
359 hypercall = g_malloc(16);
360 kvmppc_get_hypercall(env, hypercall, 16);
361 fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16);
362 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid());
363 }
364 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, tbfreq);
365 /* Mac OS X requires a "known good" clock-frequency value; pass it one. */
366 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_CLOCKFREQ, CLOCKFREQ);
367 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_BUSFREQ, BUSFREQ);
368
369 /* MacOS NDRV VGA driver */
370 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, NDRV_VGA_FILENAME);
371 if (filename) {
372 gchar *ndrv_file;
373 gsize ndrv_size;
374
375 if (g_file_get_contents(filename, &ndrv_file, &ndrv_size, NULL)) {
376 fw_cfg_add_file(fw_cfg, "ndrv/qemu_vga.ndrv", ndrv_file, ndrv_size);
377 }
378 g_free(filename);
379 }
380
381 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
382 }
383
384 /*
385 * Implementation of an interface to adjust firmware path
386 * for the bootindex property handling.
387 */
heathrow_fw_dev_path(FWPathProvider * p,BusState * bus,DeviceState * dev)388 static char *heathrow_fw_dev_path(FWPathProvider *p, BusState *bus,
389 DeviceState *dev)
390 {
391 PCIDevice *pci;
392 MACIOIDEState *macio_ide;
393
394 if (!strcmp(object_get_typename(OBJECT(dev)), "macio-oldworld")) {
395 pci = PCI_DEVICE(dev);
396 return g_strdup_printf("mac-io@%x", PCI_SLOT(pci->devfn));
397 }
398
399 if (!strcmp(object_get_typename(OBJECT(dev)), "macio-ide")) {
400 macio_ide = MACIO_IDE(dev);
401 return g_strdup_printf("ata-3@%x", macio_ide->addr);
402 }
403
404 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-hd")) {
405 return g_strdup("disk");
406 }
407
408 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-cd")) {
409 return g_strdup("cdrom");
410 }
411
412 if (!strcmp(object_get_typename(OBJECT(dev)), "virtio-blk-device")) {
413 return g_strdup("disk");
414 }
415
416 return NULL;
417 }
418
heathrow_kvm_type(MachineState * machine,const char * arg)419 static int heathrow_kvm_type(MachineState *machine, const char *arg)
420 {
421 /* Always force PR KVM */
422 return 2;
423 }
424
heathrow_class_init(ObjectClass * oc,void * data)425 static void heathrow_class_init(ObjectClass *oc, void *data)
426 {
427 MachineClass *mc = MACHINE_CLASS(oc);
428 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc);
429
430 mc->desc = "Heathrow based PowerMAC";
431 mc->init = ppc_heathrow_init;
432 mc->block_default_type = IF_IDE;
433 mc->max_cpus = MAX_CPUS;
434 #ifndef TARGET_PPC64
435 mc->is_default = true;
436 #endif
437 /* TOFIX "cad" when Mac floppy is implemented */
438 mc->default_boot_order = "cd";
439 mc->kvm_type = heathrow_kvm_type;
440 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("750_v3.1");
441 mc->default_display = "std";
442 mc->ignore_boot_device_suffixes = true;
443 mc->default_ram_id = "ppc_heathrow.ram";
444 fwc->get_dev_path = heathrow_fw_dev_path;
445 }
446
447 static const TypeInfo ppc_heathrow_machine_info = {
448 .name = MACHINE_TYPE_NAME("g3beige"),
449 .parent = TYPE_MACHINE,
450 .class_init = heathrow_class_init,
451 .interfaces = (InterfaceInfo[]) {
452 { TYPE_FW_PATH_PROVIDER },
453 { }
454 },
455 };
456
ppc_heathrow_register_types(void)457 static void ppc_heathrow_register_types(void)
458 {
459 type_register_static(&ppc_heathrow_machine_info);
460 }
461
462 type_init(ppc_heathrow_register_types);
463