1 /*
2 * QEMU RISC-V Spike Board
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017-2018 SiFive, Inc.
6 *
7 * This provides a RISC-V Board with the following devices:
8 *
9 * 0) HTIF Console and Poweroff
10 * 1) CLINT (Timer and IPI)
11 * 2) PLIC (Platform Level Interrupt Controller)
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms and conditions of the GNU General Public License,
15 * version 2 or later, as published by the Free Software Foundation.
16 *
17 * This program is distributed in the hope it will be useful, but WITHOUT
18 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
19 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
20 * more details.
21 *
22 * You should have received a copy of the GNU General Public License along with
23 * this program. If not, see <http://www.gnu.org/licenses/>.
24 */
25
26 #include "qemu/osdep.h"
27 #include "qemu/log.h"
28 #include "qemu/error-report.h"
29 #include "qapi/error.h"
30 #include "hw/boards.h"
31 #include "hw/loader.h"
32 #include "hw/sysbus.h"
33 #include "target/riscv/cpu.h"
34 #include "hw/riscv/riscv_hart.h"
35 #include "hw/riscv/spike.h"
36 #include "hw/riscv/boot.h"
37 #include "hw/riscv/numa.h"
38 #include "hw/char/riscv_htif.h"
39 #include "hw/intc/sifive_clint.h"
40 #include "chardev/char.h"
41 #include "sysemu/arch_init.h"
42 #include "sysemu/device_tree.h"
43 #include "sysemu/sysemu.h"
44
45 static const MemMapEntry spike_memmap[] = {
46 [SPIKE_MROM] = { 0x1000, 0xf000 },
47 [SPIKE_CLINT] = { 0x2000000, 0x10000 },
48 [SPIKE_DRAM] = { 0x80000000, 0x0 },
49 };
50
create_fdt(SpikeState * s,const MemMapEntry * memmap,uint64_t mem_size,const char * cmdline,bool is_32_bit)51 static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
52 uint64_t mem_size, const char *cmdline, bool is_32_bit)
53 {
54 void *fdt;
55 uint64_t addr, size;
56 unsigned long clint_addr;
57 int cpu, socket;
58 MachineState *mc = MACHINE(s);
59 uint32_t *clint_cells;
60 uint32_t cpu_phandle, intc_phandle, phandle = 1;
61 char *name, *mem_name, *clint_name, *clust_name;
62 char *core_name, *cpu_name, *intc_name;
63
64 fdt = s->fdt = create_device_tree(&s->fdt_size);
65 if (!fdt) {
66 error_report("create_device_tree() failed");
67 exit(1);
68 }
69
70 qemu_fdt_setprop_string(fdt, "/", "model", "ucbbar,spike-bare,qemu");
71 qemu_fdt_setprop_string(fdt, "/", "compatible", "ucbbar,spike-bare-dev");
72 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
73 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
74
75 qemu_fdt_add_subnode(fdt, "/htif");
76 qemu_fdt_setprop_string(fdt, "/htif", "compatible", "ucb,htif0");
77
78 qemu_fdt_add_subnode(fdt, "/soc");
79 qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
80 qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus");
81 qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
82 qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
83
84 qemu_fdt_add_subnode(fdt, "/cpus");
85 qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
86 SIFIVE_CLINT_TIMEBASE_FREQ);
87 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
88 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
89 qemu_fdt_add_subnode(fdt, "/cpus/cpu-map");
90
91 for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) {
92 clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket);
93 qemu_fdt_add_subnode(fdt, clust_name);
94
95 clint_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4);
96
97 for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) {
98 cpu_phandle = phandle++;
99
100 cpu_name = g_strdup_printf("/cpus/cpu@%d",
101 s->soc[socket].hartid_base + cpu);
102 qemu_fdt_add_subnode(fdt, cpu_name);
103 if (is_32_bit) {
104 qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv32");
105 } else {
106 qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv48");
107 }
108 name = riscv_isa_string(&s->soc[socket].harts[cpu]);
109 qemu_fdt_setprop_string(fdt, cpu_name, "riscv,isa", name);
110 g_free(name);
111 qemu_fdt_setprop_string(fdt, cpu_name, "compatible", "riscv");
112 qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay");
113 qemu_fdt_setprop_cell(fdt, cpu_name, "reg",
114 s->soc[socket].hartid_base + cpu);
115 qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu");
116 riscv_socket_fdt_write_id(mc, fdt, cpu_name, socket);
117 qemu_fdt_setprop_cell(fdt, cpu_name, "phandle", cpu_phandle);
118
119 intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name);
120 qemu_fdt_add_subnode(fdt, intc_name);
121 intc_phandle = phandle++;
122 qemu_fdt_setprop_cell(fdt, intc_name, "phandle", intc_phandle);
123 qemu_fdt_setprop_string(fdt, intc_name, "compatible",
124 "riscv,cpu-intc");
125 qemu_fdt_setprop(fdt, intc_name, "interrupt-controller", NULL, 0);
126 qemu_fdt_setprop_cell(fdt, intc_name, "#interrupt-cells", 1);
127
128 clint_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
129 clint_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
130 clint_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
131 clint_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
132
133 core_name = g_strdup_printf("%s/core%d", clust_name, cpu);
134 qemu_fdt_add_subnode(fdt, core_name);
135 qemu_fdt_setprop_cell(fdt, core_name, "cpu", cpu_phandle);
136
137 g_free(core_name);
138 g_free(intc_name);
139 g_free(cpu_name);
140 }
141
142 addr = memmap[SPIKE_DRAM].base + riscv_socket_mem_offset(mc, socket);
143 size = riscv_socket_mem_size(mc, socket);
144 mem_name = g_strdup_printf("/memory@%lx", (long)addr);
145 qemu_fdt_add_subnode(fdt, mem_name);
146 qemu_fdt_setprop_cells(fdt, mem_name, "reg",
147 addr >> 32, addr, size >> 32, size);
148 qemu_fdt_setprop_string(fdt, mem_name, "device_type", "memory");
149 riscv_socket_fdt_write_id(mc, fdt, mem_name, socket);
150 g_free(mem_name);
151
152 clint_addr = memmap[SPIKE_CLINT].base +
153 (memmap[SPIKE_CLINT].size * socket);
154 clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr);
155 qemu_fdt_add_subnode(fdt, clint_name);
156 qemu_fdt_setprop_string(fdt, clint_name, "compatible", "riscv,clint0");
157 qemu_fdt_setprop_cells(fdt, clint_name, "reg",
158 0x0, clint_addr, 0x0, memmap[SPIKE_CLINT].size);
159 qemu_fdt_setprop(fdt, clint_name, "interrupts-extended",
160 clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
161 riscv_socket_fdt_write_id(mc, fdt, clint_name, socket);
162
163 g_free(clint_name);
164 g_free(clint_cells);
165 g_free(clust_name);
166 }
167
168 riscv_socket_fdt_write_distance_matrix(mc, fdt);
169
170 if (cmdline) {
171 qemu_fdt_add_subnode(fdt, "/chosen");
172 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
173 }
174 }
175
spike_board_init(MachineState * machine)176 static void spike_board_init(MachineState *machine)
177 {
178 const MemMapEntry *memmap = spike_memmap;
179 SpikeState *s = SPIKE_MACHINE(machine);
180 MemoryRegion *system_memory = get_system_memory();
181 MemoryRegion *main_mem = g_new(MemoryRegion, 1);
182 MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
183 target_ulong firmware_end_addr, kernel_start_addr;
184 uint32_t fdt_load_addr;
185 uint64_t kernel_entry;
186 char *soc_name;
187 int i, base_hartid, hart_count;
188
189 /* Check socket count limit */
190 if (SPIKE_SOCKETS_MAX < riscv_socket_count(machine)) {
191 error_report("number of sockets/nodes should be less than %d",
192 SPIKE_SOCKETS_MAX);
193 exit(1);
194 }
195
196 /* Initialize sockets */
197 for (i = 0; i < riscv_socket_count(machine); i++) {
198 if (!riscv_socket_check_hartids(machine, i)) {
199 error_report("discontinuous hartids in socket%d", i);
200 exit(1);
201 }
202
203 base_hartid = riscv_socket_first_hartid(machine, i);
204 if (base_hartid < 0) {
205 error_report("can't find hartid base for socket%d", i);
206 exit(1);
207 }
208
209 hart_count = riscv_socket_hart_count(machine, i);
210 if (hart_count < 0) {
211 error_report("can't find hart count for socket%d", i);
212 exit(1);
213 }
214
215 soc_name = g_strdup_printf("soc%d", i);
216 object_initialize_child(OBJECT(machine), soc_name, &s->soc[i],
217 TYPE_RISCV_HART_ARRAY);
218 g_free(soc_name);
219 object_property_set_str(OBJECT(&s->soc[i]), "cpu-type",
220 machine->cpu_type, &error_abort);
221 object_property_set_int(OBJECT(&s->soc[i]), "hartid-base",
222 base_hartid, &error_abort);
223 object_property_set_int(OBJECT(&s->soc[i]), "num-harts",
224 hart_count, &error_abort);
225 sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_abort);
226
227 /* Core Local Interruptor (timer and IPI) for each socket */
228 sifive_clint_create(
229 memmap[SPIKE_CLINT].base + i * memmap[SPIKE_CLINT].size,
230 memmap[SPIKE_CLINT].size, base_hartid, hart_count,
231 SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
232 SIFIVE_CLINT_TIMEBASE_FREQ, false);
233 }
234
235 /* register system main memory (actual RAM) */
236 memory_region_init_ram(main_mem, NULL, "riscv.spike.ram",
237 machine->ram_size, &error_fatal);
238 memory_region_add_subregion(system_memory, memmap[SPIKE_DRAM].base,
239 main_mem);
240
241 /* create device tree */
242 create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
243 riscv_is_32bit(&s->soc[0]));
244
245 /* boot rom */
246 memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom",
247 memmap[SPIKE_MROM].size, &error_fatal);
248 memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base,
249 mask_rom);
250
251 /*
252 * Not like other RISC-V machines that use plain binary bios images,
253 * keeping ELF files here was intentional because BIN files don't work
254 * for the Spike machine as HTIF emulation depends on ELF parsing.
255 */
256 if (riscv_is_32bit(&s->soc[0])) {
257 firmware_end_addr = riscv_find_and_load_firmware(machine,
258 "opensbi-riscv32-generic-fw_dynamic.elf",
259 memmap[SPIKE_DRAM].base,
260 htif_symbol_callback);
261 } else {
262 firmware_end_addr = riscv_find_and_load_firmware(machine,
263 "opensbi-riscv64-generic-fw_dynamic.elf",
264 memmap[SPIKE_DRAM].base,
265 htif_symbol_callback);
266 }
267
268 if (machine->kernel_filename) {
269 kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0],
270 firmware_end_addr);
271
272 kernel_entry = riscv_load_kernel(machine->kernel_filename,
273 kernel_start_addr,
274 htif_symbol_callback);
275
276 if (machine->initrd_filename) {
277 hwaddr start;
278 hwaddr end = riscv_load_initrd(machine->initrd_filename,
279 machine->ram_size, kernel_entry,
280 &start);
281 qemu_fdt_setprop_cell(s->fdt, "/chosen",
282 "linux,initrd-start", start);
283 qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
284 end);
285 }
286 } else {
287 /*
288 * If dynamic firmware is used, it doesn't know where is the next mode
289 * if kernel argument is not set.
290 */
291 kernel_entry = 0;
292 }
293
294 /* Compute the fdt load address in dram */
295 fdt_load_addr = riscv_load_fdt(memmap[SPIKE_DRAM].base,
296 machine->ram_size, s->fdt);
297 /* load the reset vector */
298 riscv_setup_rom_reset_vec(machine, &s->soc[0], memmap[SPIKE_DRAM].base,
299 memmap[SPIKE_MROM].base,
300 memmap[SPIKE_MROM].size, kernel_entry,
301 fdt_load_addr, s->fdt);
302
303 /* initialize HTIF using symbols found in load_kernel */
304 htif_mm_init(system_memory, mask_rom,
305 &s->soc[0].harts[0].env, serial_hd(0));
306 }
307
spike_machine_instance_init(Object * obj)308 static void spike_machine_instance_init(Object *obj)
309 {
310 }
311
spike_machine_class_init(ObjectClass * oc,void * data)312 static void spike_machine_class_init(ObjectClass *oc, void *data)
313 {
314 MachineClass *mc = MACHINE_CLASS(oc);
315
316 mc->desc = "RISC-V Spike board";
317 mc->init = spike_board_init;
318 mc->max_cpus = SPIKE_CPUS_MAX;
319 mc->is_default = true;
320 mc->default_cpu_type = TYPE_RISCV_CPU_BASE;
321 mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids;
322 mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
323 mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
324 mc->numa_mem_supported = true;
325 }
326
327 static const TypeInfo spike_machine_typeinfo = {
328 .name = MACHINE_TYPE_NAME("spike"),
329 .parent = TYPE_MACHINE,
330 .class_init = spike_machine_class_init,
331 .instance_init = spike_machine_instance_init,
332 .instance_size = sizeof(SpikeState),
333 };
334
spike_machine_init_register_types(void)335 static void spike_machine_init_register_types(void)
336 {
337 type_register_static(&spike_machine_typeinfo);
338 }
339
340 type_init(spike_machine_init_register_types)
341