1//------------------------------------------------------------------------------
2//
3// Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
4// Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
5//
6// SPDX-License-Identifier: BSD-2-Clause-Patent
7//
8//------------------------------------------------------------------------------
9
10
11    INCLUDE AsmMacroExport.inc
12    PRESERVE8
13
14DC_ON           EQU     ( 0x1:SHL:2 )
15IC_ON           EQU     ( 0x1:SHL:12 )
16CTRL_M_BIT      EQU     (1 << 0)
17CTRL_C_BIT      EQU     (1 << 2)
18CTRL_B_BIT      EQU     (1 << 7)
19CTRL_I_BIT      EQU     (1 << 12)
20
21
22 RVCT_ASM_EXPORT ArmInvalidateDataCacheEntryByMVA
23  mcr     p15, 0, r0, c7, c6, 1   ; invalidate single data cache line
24  bx      lr
25
26 RVCT_ASM_EXPORT ArmCleanDataCacheEntryByMVA
27  mcr     p15, 0, r0, c7, c10, 1  ; clean single data cache line
28  bx      lr
29
30
31 RVCT_ASM_EXPORT ArmInvalidateInstructionCacheEntryToPoUByMVA
32  mcr     p15, 0, r0, c7, c5, 1   ; invalidate single instruction cache line to PoU
33  mcr     p15, 0, r0, c7, c5, 7   ; invalidate branch predictor
34  bx      lr
35
36
37 RVCT_ASM_EXPORT ArmCleanDataCacheEntryToPoUByMVA
38  mcr     p15, 0, r0, c7, c11, 1  ; clean single data cache line to PoU
39  bx      lr
40
41
42 RVCT_ASM_EXPORT ArmCleanInvalidateDataCacheEntryByMVA
43  mcr     p15, 0, r0, c7, c14, 1  ; clean and invalidate single data cache line
44  bx      lr
45
46
47 RVCT_ASM_EXPORT ArmInvalidateDataCacheEntryBySetWay
48  mcr     p15, 0, r0, c7, c6, 2        ; Invalidate this line
49  bx      lr
50
51
52 RVCT_ASM_EXPORT ArmCleanInvalidateDataCacheEntryBySetWay
53  mcr     p15, 0, r0, c7, c14, 2       ; Clean and Invalidate this line
54  bx      lr
55
56
57 RVCT_ASM_EXPORT ArmCleanDataCacheEntryBySetWay
58  mcr     p15, 0, r0, c7, c10, 2       ; Clean this line
59  bx      lr
60
61
62 RVCT_ASM_EXPORT ArmInvalidateInstructionCache
63  mcr     p15,0,R0,c7,c5,0      ;Invalidate entire instruction cache
64  isb
65  bx      LR
66
67 RVCT_ASM_EXPORT ArmEnableMmu
68  mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
69  orr     R0,R0,#1              ; Set SCTLR.M bit : Enable MMU
70  mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)
71  dsb
72  isb
73  bx      LR
74
75 RVCT_ASM_EXPORT ArmDisableMmu
76  mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
77  bic     R0,R0,#1              ; Clear SCTLR.M bit : Disable MMU
78  mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)
79
80  mcr     p15,0,R0,c8,c7,0      ; TLBIALL : Invalidate unified TLB
81  mcr     p15,0,R0,c7,c5,6      ; BPIALL  : Invalidate entire branch predictor array
82  dsb
83  isb
84  bx      LR
85
86 RVCT_ASM_EXPORT ArmDisableCachesAndMmu
87  mrc   p15, 0, r0, c1, c0, 0           ; Get control register
88  bic   r0, r0, #CTRL_M_BIT             ; Disable MMU
89  bic   r0, r0, #CTRL_C_BIT             ; Disable D Cache
90  bic   r0, r0, #CTRL_I_BIT             ; Disable I Cache
91  mcr   p15, 0, r0, c1, c0, 0           ; Write control register
92  dsb
93  isb
94  bx      LR
95
96 RVCT_ASM_EXPORT ArmMmuEnabled
97  mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
98  and     R0,R0,#1
99  bx      LR
100
101 RVCT_ASM_EXPORT ArmEnableDataCache
102  ldr     R1,=DC_ON             ; Specify SCTLR.C bit : (Data) Cache enable bit
103  mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
104  orr     R0,R0,R1              ; Set SCTLR.C bit : Data and unified caches enabled
105  mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)
106  dsb
107  isb
108  bx      LR
109
110 RVCT_ASM_EXPORT ArmDisableDataCache
111  ldr     R1,=DC_ON             ; Specify SCTLR.C bit : (Data) Cache enable bit
112  mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
113  bic     R0,R0,R1              ; Clear SCTLR.C bit : Data and unified caches disabled
114  mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)
115  dsb
116  isb
117  bx      LR
118
119 RVCT_ASM_EXPORT ArmEnableInstructionCache
120  ldr     R1,=IC_ON             ; Specify SCTLR.I bit : Instruction cache enable bit
121  mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
122  orr     R0,R0,R1              ; Set SCTLR.I bit : Instruction caches enabled
123  mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)
124  dsb
125  isb
126  bx      LR
127
128 RVCT_ASM_EXPORT ArmDisableInstructionCache
129  ldr     R1,=IC_ON             ; Specify SCTLR.I bit : Instruction cache enable bit
130  mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
131  BIC     R0,R0,R1              ; Clear SCTLR.I bit : Instruction caches disabled
132  mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)
133  isb
134  bx      LR
135
136 RVCT_ASM_EXPORT ArmEnableSWPInstruction
137  mrc     p15, 0, r0, c1, c0, 0
138  orr     r0, r0, #0x00000400
139  mcr     p15, 0, r0, c1, c0, 0
140  isb
141  bx      LR
142
143 RVCT_ASM_EXPORT ArmEnableBranchPrediction
144  mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
145  orr     r0, r0, #0x00000800   ;
146  mcr     p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
147  dsb
148  isb
149  bx      LR
150
151 RVCT_ASM_EXPORT ArmDisableBranchPrediction
152  mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
153  bic     r0, r0, #0x00000800   ;
154  mcr     p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
155  dsb
156  isb
157  bx      LR
158
159 RVCT_ASM_EXPORT ArmSetLowVectors
160  mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
161  bic     r0, r0, #0x00002000   ; clear V bit
162  mcr     p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
163  isb
164  bx      LR
165
166 RVCT_ASM_EXPORT ArmSetHighVectors
167  mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
168  orr     r0, r0, #0x00002000   ; Set V bit
169  mcr     p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
170  isb
171  bx      LR
172
173 RVCT_ASM_EXPORT ArmV7AllDataCachesOperation
174  stmfd SP!,{r4-r12, LR}
175  mov   R1, R0                ; Save Function call in R1
176  mrc   p15, 1, R6, c0, c0, 1 ; Read CLIDR
177  ands  R3, R6, #&7000000     ; Mask out all but Level of Coherency (LoC)
178  mov   R3, R3, LSR #23       ; Cache level value (naturally aligned)
179  beq   Finished
180  mov   R10, #0
181
182Loop1
183  add   R2, R10, R10, LSR #1    ; Work out 3xcachelevel
184  mov   R12, R6, LSR R2         ; bottom 3 bits are the Cache type for this level
185  and   R12, R12, #7            ; get those 3 bits alone
186  cmp   R12, #2
187  blt   Skip                    ; no cache or only instruction cache at this level
188  mcr   p15, 2, R10, c0, c0, 0  ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
189  isb                           ; isb to sync the change to the CacheSizeID reg
190  mrc   p15, 1, R12, c0, c0, 0  ; reads current Cache Size ID register (CCSIDR)
191  and   R2, R12, #&7            ; extract the line length field
192  add   R2, R2, #4              ; add 4 for the line length offset (log2 16 bytes)
193  ldr   R4, =0x3FF
194  ands  R4, R4, R12, LSR #3     ; R4 is the max number on the way size (right aligned)
195  clz   R5, R4                  ; R5 is the bit position of the way size increment
196  ldr   R7, =0x00007FFF
197  ands  R7, R7, R12, LSR #13    ; R7 is the max number of the index size (right aligned)
198
199Loop2
200  mov   R9, R4                  ; R9 working copy of the max way size (right aligned)
201
202Loop3
203  orr   R0, R10, R9, LSL R5     ; factor in the way number and cache number into R11
204  orr   R0, R0, R7, LSL R2      ; factor in the index number
205
206  blx   R1
207
208  subs  R9, R9, #1              ; decrement the way number
209  bge   Loop3
210  subs  R7, R7, #1              ; decrement the index
211  bge   Loop2
212Skip
213  add   R10, R10, #2            ; increment the cache number
214  cmp   R3, R10
215  bgt   Loop1
216
217Finished
218  dsb
219  ldmfd SP!, {r4-r12, lr}
220  bx    LR
221
222 RVCT_ASM_EXPORT ArmDataMemoryBarrier
223  dmb
224  bx      LR
225
226 RVCT_ASM_EXPORT ArmDataSynchronizationBarrier
227  dsb
228  bx      LR
229
230 RVCT_ASM_EXPORT ArmInstructionSynchronizationBarrier
231  isb
232  bx      LR
233
234 RVCT_ASM_EXPORT ArmReadVBar
235  // Set the Address of the Vector Table in the VBAR register
236  mrc     p15, 0, r0, c12, c0, 0
237  bx      lr
238
239 RVCT_ASM_EXPORT ArmWriteVBar
240  // Set the Address of the Vector Table in the VBAR register
241  mcr     p15, 0, r0, c12, c0, 0
242  // Ensure the SCTLR.V bit is clear
243  mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
244  bic     r0, r0, #0x00002000   ; clear V bit
245  mcr     p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
246  isb
247  bx      lr
248
249 RVCT_ASM_EXPORT ArmEnableVFP
250  // Read CPACR (Coprocessor Access Control Register)
251  mrc     p15, 0, r0, c1, c0, 2
252  // Enable VPF access (Full Access to CP10, CP11) (V* instructions)
253  orr     r0, r0, #0x00f00000
254  // Write back CPACR (Coprocessor Access Control Register)
255  mcr     p15, 0, r0, c1, c0, 2
256  isb
257  // Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.
258  mov     r0, #0x40000000
259  mcr     p10,#0x7,r0,c8,c0,#0
260  bx      lr
261
262 RVCT_ASM_EXPORT ArmCallWFI
263  wfi
264  bx      lr
265
266//Note: Return 0 in Uniprocessor implementation
267 RVCT_ASM_EXPORT ArmReadCbar
268  mrc     p15, 4, r0, c15, c0, 0  //Read Configuration Base Address Register
269  bx      lr
270
271 RVCT_ASM_EXPORT ArmReadMpidr
272  mrc     p15, 0, r0, c0, c0, 5     ; read MPIDR
273  bx      lr
274
275 RVCT_ASM_EXPORT ArmReadTpidrurw
276  mrc     p15, 0, r0, c13, c0, 2    ; read TPIDRURW
277  bx      lr
278
279 RVCT_ASM_EXPORT ArmWriteTpidrurw
280  mcr     p15, 0, r0, c13, c0, 2   ; write TPIDRURW
281  bx      lr
282
283 RVCT_ASM_EXPORT ArmIsArchTimerImplemented
284  mrc    p15, 0, r0, c0, c1, 1     ; Read ID_PFR1
285  and    r0, r0, #0x000F0000
286  bx     lr
287
288 RVCT_ASM_EXPORT ArmReadIdPfr1
289  mrc    p15, 0, r0, c0, c1, 1     ; Read ID_PFR1 Register
290  bx     lr
291
292 END
293