1 /****************************************************************************** 2 * include/public/trace.h 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a copy 5 * of this software and associated documentation files (the "Software"), to 6 * deal in the Software without restriction, including without limitation the 7 * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or 8 * sell copies of the Software, and to permit persons to whom the Software is 9 * furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 17 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 20 * DEALINGS IN THE SOFTWARE. 21 * 22 * Mark Williamson, (C) 2004 Intel Research Cambridge 23 * Copyright (C) 2005 Bin Ren 24 */ 25 26 #ifndef __XEN_PUBLIC_TRACE_H__ 27 #define __XEN_PUBLIC_TRACE_H__ 28 29 FILE_LICENCE ( MIT ); 30 31 #define TRACE_EXTRA_MAX 7 32 #define TRACE_EXTRA_SHIFT 28 33 34 /* Trace classes */ 35 #define TRC_CLS_SHIFT 16 36 #define TRC_GEN 0x0001f000 /* General trace */ 37 #define TRC_SCHED 0x0002f000 /* Xen Scheduler trace */ 38 #define TRC_DOM0OP 0x0004f000 /* Xen DOM0 operation trace */ 39 #define TRC_HVM 0x0008f000 /* Xen HVM trace */ 40 #define TRC_MEM 0x0010f000 /* Xen memory trace */ 41 #define TRC_PV 0x0020f000 /* Xen PV traces */ 42 #define TRC_SHADOW 0x0040f000 /* Xen shadow tracing */ 43 #define TRC_HW 0x0080f000 /* Xen hardware-related traces */ 44 #define TRC_GUEST 0x0800f000 /* Guest-generated traces */ 45 #define TRC_ALL 0x0ffff000 46 #define TRC_HD_TO_EVENT(x) ((x)&0x0fffffff) 47 #define TRC_HD_CYCLE_FLAG (1UL<<31) 48 #define TRC_HD_INCLUDES_CYCLE_COUNT(x) ( !!( (x) & TRC_HD_CYCLE_FLAG ) ) 49 #define TRC_HD_EXTRA(x) (((x)>>TRACE_EXTRA_SHIFT)&TRACE_EXTRA_MAX) 50 51 /* Trace subclasses */ 52 #define TRC_SUBCLS_SHIFT 12 53 54 /* trace subclasses for SVM */ 55 #define TRC_HVM_ENTRYEXIT 0x00081000 /* VMENTRY and #VMEXIT */ 56 #define TRC_HVM_HANDLER 0x00082000 /* various HVM handlers */ 57 #define TRC_HVM_EMUL 0x00084000 /* emulated devices */ 58 59 #define TRC_SCHED_MIN 0x00021000 /* Just runstate changes */ 60 #define TRC_SCHED_CLASS 0x00022000 /* Scheduler-specific */ 61 #define TRC_SCHED_VERBOSE 0x00028000 /* More inclusive scheduling */ 62 63 /* 64 * The highest 3 bits of the last 12 bits of TRC_SCHED_CLASS above are 65 * reserved for encoding what scheduler produced the information. The 66 * actual event is encoded in the last 9 bits. 67 * 68 * This means we have 8 scheduling IDs available (which means at most 8 69 * schedulers generating events) and, in each scheduler, up to 512 70 * different events. 71 */ 72 #define TRC_SCHED_ID_BITS 3 73 #define TRC_SCHED_ID_SHIFT (TRC_SUBCLS_SHIFT - TRC_SCHED_ID_BITS) 74 #define TRC_SCHED_ID_MASK (((1UL<<TRC_SCHED_ID_BITS) - 1) << TRC_SCHED_ID_SHIFT) 75 #define TRC_SCHED_EVT_MASK (~(TRC_SCHED_ID_MASK)) 76 77 /* Per-scheduler IDs, to identify scheduler specific events */ 78 #define TRC_SCHED_CSCHED 0 79 #define TRC_SCHED_CSCHED2 1 80 #define TRC_SCHED_SEDF 2 81 #define TRC_SCHED_ARINC653 3 82 83 /* Per-scheduler tracing */ 84 #define TRC_SCHED_CLASS_EVT(_c, _e) \ 85 ( ( TRC_SCHED_CLASS | \ 86 ((TRC_SCHED_##_c << TRC_SCHED_ID_SHIFT) & TRC_SCHED_ID_MASK) ) + \ 87 (_e & TRC_SCHED_EVT_MASK) ) 88 89 /* Trace classes for Hardware */ 90 #define TRC_HW_PM 0x00801000 /* Power management traces */ 91 #define TRC_HW_IRQ 0x00802000 /* Traces relating to the handling of IRQs */ 92 93 /* Trace events per class */ 94 #define TRC_LOST_RECORDS (TRC_GEN + 1) 95 #define TRC_TRACE_WRAP_BUFFER (TRC_GEN + 2) 96 #define TRC_TRACE_CPU_CHANGE (TRC_GEN + 3) 97 98 #define TRC_SCHED_RUNSTATE_CHANGE (TRC_SCHED_MIN + 1) 99 #define TRC_SCHED_CONTINUE_RUNNING (TRC_SCHED_MIN + 2) 100 #define TRC_SCHED_DOM_ADD (TRC_SCHED_VERBOSE + 1) 101 #define TRC_SCHED_DOM_REM (TRC_SCHED_VERBOSE + 2) 102 #define TRC_SCHED_SLEEP (TRC_SCHED_VERBOSE + 3) 103 #define TRC_SCHED_WAKE (TRC_SCHED_VERBOSE + 4) 104 #define TRC_SCHED_YIELD (TRC_SCHED_VERBOSE + 5) 105 #define TRC_SCHED_BLOCK (TRC_SCHED_VERBOSE + 6) 106 #define TRC_SCHED_SHUTDOWN (TRC_SCHED_VERBOSE + 7) 107 #define TRC_SCHED_CTL (TRC_SCHED_VERBOSE + 8) 108 #define TRC_SCHED_ADJDOM (TRC_SCHED_VERBOSE + 9) 109 #define TRC_SCHED_SWITCH (TRC_SCHED_VERBOSE + 10) 110 #define TRC_SCHED_S_TIMER_FN (TRC_SCHED_VERBOSE + 11) 111 #define TRC_SCHED_T_TIMER_FN (TRC_SCHED_VERBOSE + 12) 112 #define TRC_SCHED_DOM_TIMER_FN (TRC_SCHED_VERBOSE + 13) 113 #define TRC_SCHED_SWITCH_INFPREV (TRC_SCHED_VERBOSE + 14) 114 #define TRC_SCHED_SWITCH_INFNEXT (TRC_SCHED_VERBOSE + 15) 115 #define TRC_SCHED_SHUTDOWN_CODE (TRC_SCHED_VERBOSE + 16) 116 117 #define TRC_MEM_PAGE_GRANT_MAP (TRC_MEM + 1) 118 #define TRC_MEM_PAGE_GRANT_UNMAP (TRC_MEM + 2) 119 #define TRC_MEM_PAGE_GRANT_TRANSFER (TRC_MEM + 3) 120 #define TRC_MEM_SET_P2M_ENTRY (TRC_MEM + 4) 121 #define TRC_MEM_DECREASE_RESERVATION (TRC_MEM + 5) 122 #define TRC_MEM_POD_POPULATE (TRC_MEM + 16) 123 #define TRC_MEM_POD_ZERO_RECLAIM (TRC_MEM + 17) 124 #define TRC_MEM_POD_SUPERPAGE_SPLINTER (TRC_MEM + 18) 125 126 #define TRC_PV_ENTRY 0x00201000 /* Hypervisor entry points for PV guests. */ 127 #define TRC_PV_SUBCALL 0x00202000 /* Sub-call in a multicall hypercall */ 128 129 #define TRC_PV_HYPERCALL (TRC_PV_ENTRY + 1) 130 #define TRC_PV_TRAP (TRC_PV_ENTRY + 3) 131 #define TRC_PV_PAGE_FAULT (TRC_PV_ENTRY + 4) 132 #define TRC_PV_FORCED_INVALID_OP (TRC_PV_ENTRY + 5) 133 #define TRC_PV_EMULATE_PRIVOP (TRC_PV_ENTRY + 6) 134 #define TRC_PV_EMULATE_4GB (TRC_PV_ENTRY + 7) 135 #define TRC_PV_MATH_STATE_RESTORE (TRC_PV_ENTRY + 8) 136 #define TRC_PV_PAGING_FIXUP (TRC_PV_ENTRY + 9) 137 #define TRC_PV_GDT_LDT_MAPPING_FAULT (TRC_PV_ENTRY + 10) 138 #define TRC_PV_PTWR_EMULATION (TRC_PV_ENTRY + 11) 139 #define TRC_PV_PTWR_EMULATION_PAE (TRC_PV_ENTRY + 12) 140 #define TRC_PV_HYPERCALL_V2 (TRC_PV_ENTRY + 13) 141 #define TRC_PV_HYPERCALL_SUBCALL (TRC_PV_SUBCALL + 14) 142 143 /* 144 * TRC_PV_HYPERCALL_V2 format 145 * 146 * Only some of the hypercall argument are recorded. Bit fields A0 to 147 * A5 in the first extra word are set if the argument is present and 148 * the arguments themselves are packed sequentially in the following 149 * words. 150 * 151 * The TRC_64_FLAG bit is not set for these events (even if there are 152 * 64-bit arguments in the record). 153 * 154 * Word 155 * 0 bit 31 30|29 28|27 26|25 24|23 22|21 20|19 ... 0 156 * A5 |A4 |A3 |A2 |A1 |A0 |Hypercall op 157 * 1 First 32 bit (or low word of first 64 bit) arg in record 158 * 2 Second 32 bit (or high word of first 64 bit) arg in record 159 * ... 160 * 161 * A0-A5 bitfield values: 162 * 163 * 00b Argument not present 164 * 01b 32-bit argument present 165 * 10b 64-bit argument present 166 * 11b Reserved 167 */ 168 #define TRC_PV_HYPERCALL_V2_ARG_32(i) (0x1 << (20 + 2*(i))) 169 #define TRC_PV_HYPERCALL_V2_ARG_64(i) (0x2 << (20 + 2*(i))) 170 #define TRC_PV_HYPERCALL_V2_ARG_MASK (0xfff00000) 171 172 #define TRC_SHADOW_NOT_SHADOW (TRC_SHADOW + 1) 173 #define TRC_SHADOW_FAST_PROPAGATE (TRC_SHADOW + 2) 174 #define TRC_SHADOW_FAST_MMIO (TRC_SHADOW + 3) 175 #define TRC_SHADOW_FALSE_FAST_PATH (TRC_SHADOW + 4) 176 #define TRC_SHADOW_MMIO (TRC_SHADOW + 5) 177 #define TRC_SHADOW_FIXUP (TRC_SHADOW + 6) 178 #define TRC_SHADOW_DOMF_DYING (TRC_SHADOW + 7) 179 #define TRC_SHADOW_EMULATE (TRC_SHADOW + 8) 180 #define TRC_SHADOW_EMULATE_UNSHADOW_USER (TRC_SHADOW + 9) 181 #define TRC_SHADOW_EMULATE_UNSHADOW_EVTINJ (TRC_SHADOW + 10) 182 #define TRC_SHADOW_EMULATE_UNSHADOW_UNHANDLED (TRC_SHADOW + 11) 183 #define TRC_SHADOW_WRMAP_BF (TRC_SHADOW + 12) 184 #define TRC_SHADOW_PREALLOC_UNPIN (TRC_SHADOW + 13) 185 #define TRC_SHADOW_RESYNC_FULL (TRC_SHADOW + 14) 186 #define TRC_SHADOW_RESYNC_ONLY (TRC_SHADOW + 15) 187 188 /* trace events per subclass */ 189 #define TRC_HVM_NESTEDFLAG (0x400) 190 #define TRC_HVM_VMENTRY (TRC_HVM_ENTRYEXIT + 0x01) 191 #define TRC_HVM_VMEXIT (TRC_HVM_ENTRYEXIT + 0x02) 192 #define TRC_HVM_VMEXIT64 (TRC_HVM_ENTRYEXIT + TRC_64_FLAG + 0x02) 193 #define TRC_HVM_PF_XEN (TRC_HVM_HANDLER + 0x01) 194 #define TRC_HVM_PF_XEN64 (TRC_HVM_HANDLER + TRC_64_FLAG + 0x01) 195 #define TRC_HVM_PF_INJECT (TRC_HVM_HANDLER + 0x02) 196 #define TRC_HVM_PF_INJECT64 (TRC_HVM_HANDLER + TRC_64_FLAG + 0x02) 197 #define TRC_HVM_INJ_EXC (TRC_HVM_HANDLER + 0x03) 198 #define TRC_HVM_INJ_VIRQ (TRC_HVM_HANDLER + 0x04) 199 #define TRC_HVM_REINJ_VIRQ (TRC_HVM_HANDLER + 0x05) 200 #define TRC_HVM_IO_READ (TRC_HVM_HANDLER + 0x06) 201 #define TRC_HVM_IO_WRITE (TRC_HVM_HANDLER + 0x07) 202 #define TRC_HVM_CR_READ (TRC_HVM_HANDLER + 0x08) 203 #define TRC_HVM_CR_READ64 (TRC_HVM_HANDLER + TRC_64_FLAG + 0x08) 204 #define TRC_HVM_CR_WRITE (TRC_HVM_HANDLER + 0x09) 205 #define TRC_HVM_CR_WRITE64 (TRC_HVM_HANDLER + TRC_64_FLAG + 0x09) 206 #define TRC_HVM_DR_READ (TRC_HVM_HANDLER + 0x0A) 207 #define TRC_HVM_DR_WRITE (TRC_HVM_HANDLER + 0x0B) 208 #define TRC_HVM_MSR_READ (TRC_HVM_HANDLER + 0x0C) 209 #define TRC_HVM_MSR_WRITE (TRC_HVM_HANDLER + 0x0D) 210 #define TRC_HVM_CPUID (TRC_HVM_HANDLER + 0x0E) 211 #define TRC_HVM_INTR (TRC_HVM_HANDLER + 0x0F) 212 #define TRC_HVM_NMI (TRC_HVM_HANDLER + 0x10) 213 #define TRC_HVM_SMI (TRC_HVM_HANDLER + 0x11) 214 #define TRC_HVM_VMMCALL (TRC_HVM_HANDLER + 0x12) 215 #define TRC_HVM_HLT (TRC_HVM_HANDLER + 0x13) 216 #define TRC_HVM_INVLPG (TRC_HVM_HANDLER + 0x14) 217 #define TRC_HVM_INVLPG64 (TRC_HVM_HANDLER + TRC_64_FLAG + 0x14) 218 #define TRC_HVM_MCE (TRC_HVM_HANDLER + 0x15) 219 #define TRC_HVM_IOPORT_READ (TRC_HVM_HANDLER + 0x16) 220 #define TRC_HVM_IOMEM_READ (TRC_HVM_HANDLER + 0x17) 221 #define TRC_HVM_CLTS (TRC_HVM_HANDLER + 0x18) 222 #define TRC_HVM_LMSW (TRC_HVM_HANDLER + 0x19) 223 #define TRC_HVM_LMSW64 (TRC_HVM_HANDLER + TRC_64_FLAG + 0x19) 224 #define TRC_HVM_RDTSC (TRC_HVM_HANDLER + 0x1a) 225 #define TRC_HVM_INTR_WINDOW (TRC_HVM_HANDLER + 0x20) 226 #define TRC_HVM_NPF (TRC_HVM_HANDLER + 0x21) 227 #define TRC_HVM_REALMODE_EMULATE (TRC_HVM_HANDLER + 0x22) 228 #define TRC_HVM_TRAP (TRC_HVM_HANDLER + 0x23) 229 #define TRC_HVM_TRAP_DEBUG (TRC_HVM_HANDLER + 0x24) 230 #define TRC_HVM_VLAPIC (TRC_HVM_HANDLER + 0x25) 231 232 #define TRC_HVM_IOPORT_WRITE (TRC_HVM_HANDLER + 0x216) 233 #define TRC_HVM_IOMEM_WRITE (TRC_HVM_HANDLER + 0x217) 234 235 /* Trace events for emulated devices */ 236 #define TRC_HVM_EMUL_HPET_START_TIMER (TRC_HVM_EMUL + 0x1) 237 #define TRC_HVM_EMUL_PIT_START_TIMER (TRC_HVM_EMUL + 0x2) 238 #define TRC_HVM_EMUL_RTC_START_TIMER (TRC_HVM_EMUL + 0x3) 239 #define TRC_HVM_EMUL_LAPIC_START_TIMER (TRC_HVM_EMUL + 0x4) 240 #define TRC_HVM_EMUL_HPET_STOP_TIMER (TRC_HVM_EMUL + 0x5) 241 #define TRC_HVM_EMUL_PIT_STOP_TIMER (TRC_HVM_EMUL + 0x6) 242 #define TRC_HVM_EMUL_RTC_STOP_TIMER (TRC_HVM_EMUL + 0x7) 243 #define TRC_HVM_EMUL_LAPIC_STOP_TIMER (TRC_HVM_EMUL + 0x8) 244 #define TRC_HVM_EMUL_PIT_TIMER_CB (TRC_HVM_EMUL + 0x9) 245 #define TRC_HVM_EMUL_LAPIC_TIMER_CB (TRC_HVM_EMUL + 0xA) 246 #define TRC_HVM_EMUL_PIC_INT_OUTPUT (TRC_HVM_EMUL + 0xB) 247 #define TRC_HVM_EMUL_PIC_KICK (TRC_HVM_EMUL + 0xC) 248 #define TRC_HVM_EMUL_PIC_INTACK (TRC_HVM_EMUL + 0xD) 249 #define TRC_HVM_EMUL_PIC_POSEDGE (TRC_HVM_EMUL + 0xE) 250 #define TRC_HVM_EMUL_PIC_NEGEDGE (TRC_HVM_EMUL + 0xF) 251 #define TRC_HVM_EMUL_PIC_PEND_IRQ_CALL (TRC_HVM_EMUL + 0x10) 252 #define TRC_HVM_EMUL_LAPIC_PIC_INTR (TRC_HVM_EMUL + 0x11) 253 254 /* trace events for per class */ 255 #define TRC_PM_FREQ_CHANGE (TRC_HW_PM + 0x01) 256 #define TRC_PM_IDLE_ENTRY (TRC_HW_PM + 0x02) 257 #define TRC_PM_IDLE_EXIT (TRC_HW_PM + 0x03) 258 259 /* Trace events for IRQs */ 260 #define TRC_HW_IRQ_MOVE_CLEANUP_DELAY (TRC_HW_IRQ + 0x1) 261 #define TRC_HW_IRQ_MOVE_CLEANUP (TRC_HW_IRQ + 0x2) 262 #define TRC_HW_IRQ_BIND_VECTOR (TRC_HW_IRQ + 0x3) 263 #define TRC_HW_IRQ_CLEAR_VECTOR (TRC_HW_IRQ + 0x4) 264 #define TRC_HW_IRQ_MOVE_FINISH (TRC_HW_IRQ + 0x5) 265 #define TRC_HW_IRQ_ASSIGN_VECTOR (TRC_HW_IRQ + 0x6) 266 #define TRC_HW_IRQ_UNMAPPED_VECTOR (TRC_HW_IRQ + 0x7) 267 #define TRC_HW_IRQ_HANDLED (TRC_HW_IRQ + 0x8) 268 269 /* 270 * Event Flags 271 * 272 * Some events (e.g, TRC_PV_TRAP and TRC_HVM_IOMEM_READ) have multiple 273 * record formats. These event flags distinguish between the 274 * different formats. 275 */ 276 #define TRC_64_FLAG 0x100 /* Addresses are 64 bits (instead of 32 bits) */ 277 278 /* This structure represents a single trace buffer record. */ 279 struct t_rec { 280 uint32_t event:28; 281 uint32_t extra_u32:3; /* # entries in trailing extra_u32[] array */ 282 uint32_t cycles_included:1; /* u.cycles or u.no_cycles? */ 283 union { 284 struct { 285 uint32_t cycles_lo, cycles_hi; /* cycle counter timestamp */ 286 uint32_t extra_u32[7]; /* event data items */ 287 } cycles; 288 struct { 289 uint32_t extra_u32[7]; /* event data items */ 290 } nocycles; 291 } u; 292 }; 293 294 /* 295 * This structure contains the metadata for a single trace buffer. The head 296 * field, indexes into an array of struct t_rec's. 297 */ 298 struct t_buf { 299 /* Assume the data buffer size is X. X is generally not a power of 2. 300 * CONS and PROD are incremented modulo (2*X): 301 * 0 <= cons < 2*X 302 * 0 <= prod < 2*X 303 * This is done because addition modulo X breaks at 2^32 when X is not a 304 * power of 2: 305 * (((2^32 - 1) % X) + 1) % X != (2^32) % X 306 */ 307 uint32_t cons; /* Offset of next item to be consumed by control tools. */ 308 uint32_t prod; /* Offset of next item to be produced by Xen. */ 309 /* Records follow immediately after the meta-data header. */ 310 }; 311 312 /* Structure used to pass MFNs to the trace buffers back to trace consumers. 313 * Offset is an offset into the mapped structure where the mfn list will be held. 314 * MFNs will be at ((unsigned long *)(t_info))+(t_info->cpu_offset[cpu]). 315 */ 316 struct t_info { 317 uint16_t tbuf_size; /* Size in pages of each trace buffer */ 318 uint16_t mfn_offset[]; /* Offset within t_info structure of the page list per cpu */ 319 /* MFN lists immediately after the header */ 320 }; 321 322 #endif /* __XEN_PUBLIC_TRACE_H__ */ 323 324 /* 325 * Local variables: 326 * mode: C 327 * c-file-style: "BSD" 328 * c-basic-offset: 4 329 * tab-width: 4 330 * indent-tabs-mode: nil 331 * End: 332 */ 333