1Virtual Accelerator Switchboard (VAS)
2=====================================
3
4VAS is present in P9 or later processors. In P9, each chip has one
5instance of VAS. Each instance of VAS is represented as a "platform
6device" i.e as a node in root of the device tree: ::
7
8  /vas@<vas_addr>
9
10with unique VAS address which also represents the Hypervisor window
11context address for the instance of VAS.
12
13Each VAS node contains: ::
14
15  compatible: "ibm,power9-vas", "ibm,vas"
16
17  ibm,chip-id: Chip-id of the chip containing this instance of VAS.
18
19  ibm,vas-id: unique identifier for each instance of VAS in the system.
20
21  reg: contains 8 64-bit fields.
22
23        Fields [0] and [1] represent the Hypervisor window context BAR
24        (start and length). Fields [2] and [3] represent the OS/User
25        window context BAR (start and length). Fields [4] and [5]
26        contain the start and length of paste power bus address region
27        for this chip. Fields [6] and [7] represent the bit field (start
28        bit and number of bits) where the window id of the window should
29        be encoded when computing the paste address for the window.
30