1.. _skiboot-5.10.5: 2 3============== 4skiboot-5.10.5 5============== 6 7skiboot 5.10.5 was released on Tuesday April 24th, 2018. It replaces 8:ref:`skiboot-5.10.4` as the current stable release in the 5.10.x series. 9 10It is recommended that 5.10.5 be used instead of any previous 5.10.x version 11due to the bug fixes and debugging enhancements in it. 12 13Over :ref:`skiboot-5.10.4`, we have four bug fixes: 14 15- npu2/hw-procedures: fence bricks on GPU reset 16 17 The NPU workbook defines a way of fencing a brick and 18 getting the brick out of fence state. We do have an implementation 19 of bringing the brick out of fenced/quiesced state. We do 20 the latter in our procedures, but to support run time reset 21 we need to do the former. 22 23 The fencing ensures that access to memory behind the links 24 will not lead to HMI's, but instead SUE's will be populated 25 in cache (in the case of speculation). The expectation is then 26 that prior to and after reset, the operating system components 27 will flush the cache for the region of memory behind the GPU. 28 29 This patch does the following: 30 31 1. Implements a npu2_dev_fence_brick() function to set/clear 32 fence state 33 2. Clear FIR bits prior to clearing the fence status 34 3. Clear's the fence status 35 4. We take the powerbus out of CQ fence much later now, 36 in credits_check() which is the last hardware procedure 37 called after link training. 38 39- hdata/spira: parse vpd to add part-number and serial-number to xscom@ node 40 41 Expected by FWTS and associates our processor with the part/serial 42 number, which is obviously a good thing for one's own sanity. 43- hw/imc: Check for pause_microcode_at_boot() return status 44 45 pause_microcode_at_boot() loops through all the chip's ucode 46 control block and pause the ucode if it is in the running state. 47 But it does not fail if any of the chip's ucode is not initialised. 48 49 Add code to return a failure if ucode is not initialized in any 50 of the chip. Since pause_microcode_at_boot() is called just before 51 attaching the IMC device nodes in imc_init(), add code to check for 52 the function return. 53- core/cpufeatures: Fix setting DARN and SCV HWCAP feature bits 54 55 DARN and SCV has been assigned AT_HWCAP2 (32-63) bits: :: 56 57 #define PPC_FEATURE2_DARN 0x00200000 /* darn random number insn */ 58 #define PPC_FEATURE2_SCV 0x00100000 /* scv syscall */ 59 60 A cpufeatures-aware OS will not advertise these to userspace without 61 this patch. 62