1.. _skiboot-5.5.0-rc1: 2 3skiboot-5.5.0-rc1 4================= 5 6skiboot-5.5.0-rc1 was released on Tuesday March 28th 2017. It is the first 7release candidate of skiboot 5.5, which will become the new stable release 8of skiboot following the 5.4 release, first released November 11th 2016. 9 10skiboot-5.5.0-rc1 contains all bug fixes as of :ref:`skiboot-5.4.3` 11and :ref:`skiboot-5.1.19` (the currently maintained stable releases). 12 13For how the skiboot stable releases work, see :ref:`stable-rules` for details. 14 15The current plan is to cut the final 5.5.0 by April 8th, with skiboot 5.5.0 16being for all POWER8 and POWER9 platforms in op-build v1.16 (Due April 12th). 17This is a short cycle as this release is mainly targetted towards POWER9 18bringup efforts. 19 20Following skiboot-5.5.0, we will move to a regular six week release cycle, 21similar to op-build, but slightly offset to allow for a short stabilisation 22period. Expected release dates and contents are tracked using GitHub milestone 23and issues: https://github.com/open-power/skiboot/milestones 24 25Over skiboot-5.4, we have the following changes: 26 27New Platforms 28------------- 29- SuperMicro's (SMC) P8DNU: An astbmc based POWER8 platform 30- Add a generic platform to help with bringup of new systems. 31- Four POWER9 based systems (NOTE: All POWER9 systems should be considered 32 for bringup use only at this point): 33 34 - Romulus 35 - Witherspoon (a POWER9 system with NVLink2 attached GPUs) 36 - Zaius (OpenCompute platform, also known as "Barreleye 2") 37 - ZZ (FSP based system) 38 39New features 40------------ 41 42- System reset IPI facility and Mambo implementation 43 Add an opal call :ref:`OPAL_SIGNAL_SYSTEM_RESET` which allows system reset 44 exceptions to be raised on other CPUs and act as an NMI IPI. There 45 is an initial simple Mambo implementation, but allowances are made 46 for a more complex hardware implementation. 47 48 The Mambo implementation is based on the RFC implementation for POWER8 49 hardware (see https://patchwork.ozlabs.org/patch/694794/) which we hope 50 makes it into a future release. 51 52 This implements an in-band NMI equivalent. 53- add CONTRIBUTING.md, ensuring that people new to the project have a one-stop 54 place to find out how to get started. 55- interrupts: Add optional name for OPAL interrupts 56 57 This adds the infrastructure for an interrupt source to provide 58 a name for an interrupt directed toward OPAL. Those names will 59 be put into an "opal-interrupts-names" property which is a 60 standard DT string list corresponding 1:1 with the "opal-interrupts" 61 property. PSI interrupts get names, and this is visible in Linux 62 through /proc/interrupts 63- platform: add OPAL_REBOOT_FULL_IPL reboot type 64 65 There may be circumstances in which a user wants to force a full IPL reboot 66 rather than using fast reboot. Add a new reboot type, OPAL_REBOOT_FULL_IPL, 67 that disables fast reboot. On platforms which don't support fast reboot, 68 this will be equivalent to a normal reboot. 69- phb3: Trick to allow control of the PCIe link width and speed 70 71 This implements a hook inside OPAL that catches 16 and 32 bit writes 72 to the link status register of the PHB. 73 74 It allows you to write a new speed or a new width, and OPAL will then 75 cause the PHB to renegociate. 76 77 Example: 78 79 First read the link status on PHB4: :: 80 81 setpci -s 0004:00:00.0 0x5a.w 82 a103 83 84 It's at x16 Gen3 speed (8GT/s) 85 86 bits 0x0ff0 are the width and 0x000f the speed. The width can be 87 1 to 16 and the speed 1 to 3 (2.5, 5 and 8GT/s) 88 89 Then try to bring it down to 1x Gen1 : :: 90 91 setpci -s 0004:00:00.0 0x5a.w=0xa011 92 93 Observe the result in the PHB: :: 94 95 / # lspci -s 0004:00:00.0 -vv 96 0004:00:00.0 PCI bridge: IBM Device 03dc (prog-if 00 [Normal decode]) 97 .../... 98 LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk- DLActive+ BWMgmt- ABWMgmt+ 99 100 And in the device: :: 101 102 / # lspci -s 0004:01:00.0 -vv 103 .../... 104 LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- 105 106- core/init: Add hdat-map property to OPAL node. 107 108 Exports the HDAT heap to the OS. This allows the OS to view the HDAT heap 109 directly. This allows us to view the HDAT area without having to use 110 getmemproc. 111 112- Add a generic platform: If /bmc in device tree, attempt to init one 113 For the most part, this gets us somewhere on some OpenPOWER systems 114 before there's a platform file for that machine. 115 116 Useful in bringup only, and marked as such with scary looking log 117 messages. 118 119 120Core 121---- 122 123- asm: Don't try to set LPCR:LPES1 on P8 and P9, the bit doesn't exist. 124 125- pci: Add a framework for quirks 126 127 In future we may want to be able to do fixups for specific PCI devices in 128 skiboot, so add a small framework for doing this. 129 130 This is not intended for the same purposes as quirks in the Linux kernel, 131 as the PCI devices that quirks can match for in skiboot are not properly 132 configured. This is intended to enable having a custom path to make 133 changes that don't directly interact with the PCI device, for example 134 adding device tree entries. 135 136- hw/slw: fix possible NULL dereference 137- slw: Print enabled stop states on boot 138- uart: Fix Linux pass-through policy, provide NVRAM override option 139- libc/stdio/vsnprintf.c: add explicit fallthrough, this silences a recent 140 (GCC 7.x) warning 141- init: print the FDT blob size in decimal 142- init: Print some more info before booting linux 143 144 The kernel command line from nvram and the stdout-path are 145 useful to know when debugging console related problems. 146 147- Makefile: Disable stack protector due to gcc problems 148 149 Depending on how it was built, gcc will use the canary from a global 150 (works for us) or from the TLS (doesn't work for us and accesses 151 random stuff instead). 152 153 Fixing that would be tricky. There are talks of adding a gcc option 154 to force use of globals, but in the meantime, disable the stack 155 protector. 156- Stop using 3-operand cmp[l][i] for latest binutils 157 Since a5721ba270, binutils does not support 3-operand cmp[l][i]. 158 This adds (previously optional) parameter L. 159- buddy: Add a simple generic buddy allocator 160- stack: Don't recurse into __stack_chk_fail 161- Makefile: Use -ffixed-r13 162 We use r13 for our own stuff, make sure it's properly fixed 163- Always set ibm,occ-functional-state correctly 164- psi: fix the xive registers initialization on P8, which seems to be fine 165 for real HW but causes a lof of pain under qemu 166- slw: Set PSSCR value for idle states 167- Limit number of "Poller recursion detected" errors to display 168 169 In some error conditions, we could spiral out of control on this 170 and spend all of our time printing the exact same backtrace. 171 172 Limit it to 16 times, because 16 is a nice number. 173- slw: do SLW timer testing while holding xscom lock 174 175 We add some routines that let a caller get the xscom lock once and 176 then do a bunch of xscoms while holding it. 177 In some situations without this, it could take long enough to get 178 the xscom lock that the 1ms timeout would expire and we'd falsely 179 think the SLW timer didn't work when in fact it did. 180- wait_for_resource_loaded: don't needlessly sleep for 5ms 181- run pollers in cpu_process_local_jobs() if running job synchonously 182- fsp: Don't recurse pollers in ibm_fsp_terminate 183- chiptod: More hardening against -1 chip ID 184- interrupts: Rewrite/correct doc for opal_set/get_xive 185- cpu: Don't enable nap mode/PM mode on non-P8 186- platform: Call generic platform probe and init UART there 187- psi: Don't register more interrupts than the HW supports 188- psi: Add DT option to disable LPC interrupts 189 190I2C and TPM 191----------- 192- p8i2c: Use calculated poll_interval when booting OPAL 193 Otherwise we'd default to 2seconds (TIMER_POLL) during boot on 194 chips with a functional i2c interrupt, leading to slow i2c 195 during boot (or hitting timeouts instead). 196- i2c: Add i2c_run_req() to crank the state machine for a request 197- tpm_i2c_nuvoton: work out the polling time using mftb() 198- tpm_i2c_nuvoton: handle errors after reading the tpm fifo 199- tpm_i2c_nuvoton: cleanup variables in tpm_read_fifo() 200- tpm_i2c_nuvoton: handle errors after writting the tpm fifo 201- tpm_i2c_nuvoton: cleanup variables in tpm_write_fifo() 202- tpm_i2c_nuvoton: handle errors after writing sts.commandReady in step 5 203- tpm_i2c_nuvoton: handle errors after writing sts.go 204- tpm_i2c_nuvoton: handle errors after checking the tpm fifo status 205- tpm_i2c_nuvoton: return burst_count in tpm_read_burst_count() 206- tpm_i2c_nuvoton: isolate the code that handles the TPM_TIMEOUT_D timeout 207- tpm_i2c_nuvoton: handle errors after reading sts.commandReady 208- tpm_i2c_nuvoton: add tpm_status_read_byte() 209- tpm_i2c_nuvoton: add tpm_check_status() 210- tpm_i2c_nuvoton: rename defines to shorter names 211- tpm_i2c_interface: decouple rc from being done with i2c request 212- tpm_i2c_interface: set timeout before each request 213- i2c: Add nuvoton quirk, disallowing i2cdetect as it locks TPM 214 215 p8-i2c reset things manually in some error conditions 216- stb: create-container and wrap skiboot in Secure/Trusted Boot container 217 218 We produce **UNSIGNED** skiboot.lid.stb and skiboot.lid.xz.stb as build 219 artifacts. 220 221 These are suitable blobs for flashing onto Trusted Boot enabled op-build 222 builds *WITH* the secure boot jumpers *ON* (i.e. *NOT* in secure mode). 223 It's just enough of the Secure and Trusted Boot container format to 224 make Hostboot behave. 225 226 227PCI 228--- 229- core/pci: Support SRIOV VFs 230 231 Currently, skiboot can't see SRIOV VFs. It introduces some troubles 232 as I can see: The device initialization logic (phb->ops->device_init()) 233 isn't applied to VFs, meaning we have to maintain same and duplicated 234 mechanism in kernel for VFs only. It introduces difficulty to code 235 maintaining and prone to lose sychronization. 236 237 This was motivated by bug reported by Carol: The VF's Max Payload 238 Size (MPS) isn't matched with PF's on Mellanox's adapter even kernel 239 tried to make them same. It's caused by readonly PCIECAP_EXP_DEVCTL 240 register on VFs. The skiboot would be best place to emulate this bits 241 to eliminate the gap as I can see. 242 243 This supports SRIOV VFs. When the PF's SRIOV capability is populated, 244 the number of maximal VFs (struct pci_device) are instanciated, but 245 but not usable yet. In the mean while, PCI config register filter is 246 registered against PCIECAP_SRIOV_CTRL_VFE to capture the event of 247 enabling or disabling VFs. The VFs are initialized, put into the PF's 248 children list (pd->children), populate its PCI capabilities, and 249 register PCI config register filter against PCICAP_EXP_DEVCTL. The 250 filter's handler caches what is written to MPS field and returns 251 the cached value on read, to eliminate the gap mentioned as above. 252 253- core/pci: Avoid hreset after freset 254 255 Commit 5ac71c9 ("pci: Avoid hot resets at boot time") missed to 256 avoid hot reset after fundamental reset for PCIe common slots. 257 258 This fixes it. 259- core/pci: Enforce polling PCIe link in hot-add path 260 261 In surprise hot-add path, the power state isn't changed on hardware. 262 Instead, we set the cached power state (@slot->power_state) and 263 return OPAL_SUCCESS. The upper layer starts the PCI probing immediately 264 when receiving OPAL_SUCCESS. However, the PCIe link behind the PCI 265 slot is likely down. Nothing will be probed from the PCI slot even 266 we do have PCI adpater connected to the slot. 267 268 This fixes the issue by returning OPAL_ASYNC_COMPLETION to force 269 upper layer to poll the PCIe link before probing the PCI devices 270 behind the slot in surprise and managed hot-add paths. 271- hw/phb3: fix error handling in complete reset 272 During a complete reset, when we get a timeout waiting for pending 273 transaction in state PHB3_STATE_CRESET_WAIT_CQ, we mark the PHB as 274 permanently broken. 275 276 Set the state to PHB3_STATE_FENCED so that the kernel can retry the 277 complete reset. 278- phb3: Lock the PHB on set_xive callbacks 279 280p8dnu platform 281-------------- 282- astbmc/p8dnu: Enable PCI slot's power supply on PEX9733 in hot-add path 283- astbmc/p8dnu: Enable PCI slot's power supply on PEX8718 in hot-add path 284- core/pci: Mark broken PDC on slots without surprise hotplug capability 285 286 We has to support surprise hotplug on PCI slots that don't support 287 it on hardware. So we're fully utilizing the PCIe link state change 288 event to detect the events (hot-remove and hot-add). The PDC (Presence 289 Detection Change) event isn't reliable for the purpose. For example, 290 PEX8718 on superMicro's machines. 291 292 This adds another PCI slot property "ibm,slot-broken-pdc" in the 293 device-tree, to indicate the PDC isn't reliable on those (software 294 claimed) surprise pluggable slots. 295- core/pci: Fix PCIe slot's presence 296 297 According to PCIe spec, the presence bit is hardcoded to 1 if PCIe 298 switch downstream port doesn't support slot capability. The register 299 used for the check in pcie_slot_get_presence_state() is wrong. It 300 should be PCIe capability register instead of PCIe slot capability 301 register. Otherwise, we always have present bit on the PCI topology. 302 The issue is found on Supermicro's p8dtu2u machine: :: 303 304 # lspci -t 305 -+-[0022:00]---00.0-[01-08]----00.0-[02-08]--+-01.0-[03]----00.0 306 | \-02.0-[04-08]-- 307 # cat /sys/bus/pci/slots/S002204/adapter 308 1 309 # lspci -vvs 0022:02:02.0 310 # lspci -vvs 0022:02:02.0 311 0022:02:02.0 PCI bridge: PLX Technology, Inc. PEX 8718 16-Lane, \ 312 5-Port PCI Express Gen 3 (8.0 GT/s) Switch (rev ab) (prog-if 00 [Normal decode]) 313 : 314 Capabilities: [68] Express (v2) Downstream Port (Slot+), MSI 00 315 : 316 SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock- 317 Changed: MRL- PresDet- LinkState- 318 319 This fixes the issue by checking the correct register (PCIe capability). 320 Also, the register's value is cached in advance as we did for slot and 321 link capability. 322- core/pci: More reliable way to update PCI slot power state 323 324 The power control bit (SLOT_CTL, offset: PCIe cap + 0x18) isn't 325 reliable enough to reflect the PCI slot's power state. Instead, 326 the power indication bits are more reliable comparatively. This 327 leads to mismatch between the cached power state and PCI slot's 328 presence state, resulting in the hotplug driver in kernel refuses 329 to unplug the devices properly on the request. The issue was 330 found on below NVMe card on "supermicro,p8dtu2u" machine. We don't 331 have this issue on the integrated PLX 8718 switch. :: 332 333 # lspci 334 0022:01:00.0 PCI bridge: PLX Technology, Inc. PEX 9733 33-lane, \ 335 9-port PCI Express Gen 3 (8.0 GT/s) Switch (rev aa) 336 0022:02:01.0 PCI bridge: PLX Technology, Inc. PEX 9733 33-lane, \ 337 9-port PCI Express Gen 3 (8.0 GT/s) Switch (rev aa) 338 0022:02:04.0 PCI bridge: PLX Technology, Inc. PEX 9733 33-lane, \ 339 9-port PCI Express Gen 3 (8.0 GT/s) Switch (rev aa) 340 0022:02:05.0 PCI bridge: PLX Technology, Inc. PEX 9733 33-lane, \ 341 9-port PCI Express Gen 3 (8.0 GT/s) Switch (rev aa) 342 0022:02:06.0 PCI bridge: PLX Technology, Inc. PEX 9733 33-lane, \ 343 9-port PCI Express Gen 3 (8.0 GT/s) Switch (rev aa) 344 0022:02:07.0 PCI bridge: PLX Technology, Inc. PEX 9733 33-lane, \ 345 9-port PCI Express Gen 3 (8.0 GT/s) Switch (rev aa) 346 0022:17:00.0 Non-Volatile memory controller: Device 19e5:0123 (rev 45) 347 348 This updates the cached PCI slot's power state using the power 349 indication bits instead of power control bit, to fix above issue. 350 351Utilities 352--------- 353 354- opal-prd: Direct systemd to always restart opal-prd 355 Always restart the opal-prd daemon, irrespective of why it stopped. 356- external/ffspart: Simple C program to be able to make an FFS partition 357- getscom: Add chip info for P9. 358- gard: Fix make dist target 359- pflash/libflash: arch_flash_arm: Don't assume mtd labels are short 360 361libffs 362------ 363- libffs: Understand how to create FFS partition TOCs and entries. 364 365BMC Based systems 366----------------- 367- platforms/astbmc: Support PCI slots for palmetto 368- habanero/slottable: Remove Network Mezz(2, 0) from PHB1. 369- BMC/PCI: Check slot tables against detected devices 370 On BMC machines, we have slot tables of built in PHBs, slots and devices 371 that are physically present in the system (such as the BMC itself). We 372 can use these tables to check what we *detected* against what *should* 373 be in the system and throw an error if they differ. 374 375 We have seen this occur a couple of times while still booting, giving the 376 user just an empty petitboot screen and not much else to go on. This 377 patch helps in that we get a skiboot error message, and at some point 378 in the future when we pump them up to the OS we could get a big friendly 379 error message telling you you're having a bad day. 380- pci/quirk: Populate device tree for AST2400 VGA 381 382 Adding these properties enables the kernel to function in the same way 383 that it would if it could no longer access BMC configuration registers 384 through a backdoor, which may become the default in future. 385 386 The comments describe how isolating the host from the BMC could be 387 achieved in skiboot, assuming all kernels that the system boots 388 support this. Isolating the BMC and the host from each other is 389 important if they are owned by different parties; for example, a cloud 390 provider renting machines "bare metal". 391 392- astbmc/pnor: Use mbox-flash for flash accesses 393 394 If the BMC is MBOX protocol aware, request flash reads/writes over the 395 MBOX regs. This inits the blocklevel for pnor access with mbox-flash. 396- ast: Account for differences between 2400 vs 2500 397- platform: set default bmc_platform 398 The bmc_platform pointer is set to NULL by default and on non-AMI BMC 399 platforms. As a result a few places in hw/ipmi/ipmi-sel.c will blindly 400 dereference a NULL pointer. 401 402POWER9 403------ 404 405- external: Update xscom utils for type 1 indirect accesses 406- xscom: Harden indirect writes 407- xscom: Add POWER9 scom reset 408- homer : Enable HOMER region reservation for POWER9 409- slw: Define stop idle states for P9 DD1 410- slw: Fix parsing of supported STOP states 411- slw: only enable supported STOP states 412- dts: add support for p9 cores 413 414- asm: Add POWER9 case to init_shared_sprs 415 416 For now, setup the HID and HMEER. We'll add more as we get 417 good default values from HW. 418- xive/psi/lpc: Handle proper clearing of LPC SerIRQ latch on POWER9 DD1 419- lpc: Mark the power9 LPC bus as compatible with power8 420- Fix typo in PIR mask for POWER9. Fixes booting multi-chip. 421- vpd: add vpd_valid() to check keyword VPD blobs 422 423 Adds a function to check whether a blob is a valid IBM ASCII keyword 424 VPD blob. This allows us to recognise when we do and do not have a VPD 425 blob and act accordingly. 426- core/cpu.c: Use a device-tree node to detect nest mmu presence 427 The nest mmu address scom was hardcoded which could lead to boot 428 failure on POWER9 systems without a nest mmu. For example Mambo 429 doesn't model the nest mmu which results in failure when 430 calling opal_nmmu_set_ptcr() during kernel load. 431- psi: Fix P9 BAR setup on multi-chips 432 433PHB4: 434 435 - phb4: Fix TVE encoding for start address 436 - phb4: Always assign powerbus BARs 437 438 HostBoot configure them with weird values that confuse us, instead 439 let's just own the assignment. This is temporary, I will centralize 440 memory map management next but this gets us going. 441 - phb4: Fix endian issue with link control2/status2 registers 442 Fixes training at larger than PCIe Gen1 speeds. 443 - phb4: Add ability to log config space access 444 Useful for debugging 445 - phb4: Change debug prints 446 Currently we print "PHB4" and mean either "PHB version 4" or "PHB 447 number 4" which can be quite confusing. 448 - phb4: Fix config space enable bits on DD1 449 - phb4: Fix location of EEH enable bits 450 - phb4: Fix setting of max link speed 451 - phb4: Updated inits as of PHB4 spec 0.52 452 453HDAT fixes: 454 455 - hdat: Parse BMC nodes much earlier 456 457 This moves the parsing of the BMC and LPC details to the start of the 458 HDAT parsing. This allows us to enable the Skiboot log console earlier 459 so we can get debug output while parsing the rest of the HDAT. 460 - astbmc: Don't do P8 PSI or DT fixups on P9 461 462 Previously the HDAT format was only ever used with IBM hardware so it 463 would store vital product data (VPD) blobs in the IBM ASCII Keyword VPD 464 format. With P9 HDAT is used on OpenPower machines which use Industry 465 Standard DIMMs that provide their product data through a "Serial Present 466 Detect" EEPROM mounted on the DIMM. 467 468 The SPD blob has a different format and is exported in the device-tree 469 under the "spd" property rather than the "ibm,vpd" property. This patch 470 adds support for recognising these blobs and placing them in the 471 appropriate DT property. 472 - hdat: Add __packed to all HDAT structures and workaround HB reserve 473 474 Some HDAT structures aren't properly aligned. We were using __packed 475 on some but not others and got at least one wrong (HB reserve). This 476 adds it everywhere to avoid such problems. 477 478 However this then triggers another problem where HB gives us a 479 crazy range (0.256M) to reserve with no label, which triggers an 480 assertion failure later on in mem_regions.c. 481 482 So also add a test to skip any region starting at 0 until we can 483 undertand that better and have it fixed one way or another. 484 - hdat: Ignore broken memory reserves 485 486 Ignore HDAT memory reserves > 512MB. These are considered bogus and 487 workaround known HDAT bugs. 488 - hdat: Add BMC device-tree node for P9 OpenPOWER systems 489 - hdat: Fix interrupt & device_type of UART node 490 491 The interrupt should use a standard "interrupts" property. The UART 492 node also need a device_type="serial" property for historical reasons 493 otherwise Linux won't pick it up. 494 - parse and export STOP levels 495 - add new sppcrd_chip_info fields 496 - add radix-AP-encodings 497 - stop using proc_int_line in favor of pir 498 - rename add_icp() to add_xics_icp() 499 - Add support for PHB4 500 - create XIVE nodes under each xscom node 501 - Add P9 compatible property 502 - Parse hostboot memory reservations from HDAT 503 - Add new fields to IPL params structure and update sys family for p9. 504 - Fix ibm,pa-features for all CPU types 505 - Fix XSCOM nodes for P9 506 - Remove deprecated 'ibm, mem-interleave-scope' from DT on POWER9 507 - Grab system model name from HDAT when available 508 - Grab vendor information from HDAT when available 509 - SPIRA-H/S changes for P9 510 - Add BMC and LPC IOPATH support 511 - handle ISDIMM SPD blobs 512 - make HDIF_child() print more useful errors 513 - Add PSI HB xscom details 514 - Add new fields to proc_init_data structure 515 - Add processor version check for hs service ntuple 516 - add_iplparams_serial - Validate HDIF_get_iarray_size() return value 517 518 519XIVE: 520 521The list of XIVE fixes and updates is extensive. Below is only a portion of 522the changes that have gone into skiboot 5.5.0-rc1 for the new XIVE hardware 523that is present in POWER9: 524 525 - xive: Enable backlog on queues 526 - xive: Use for_each_present_cpu() for setting up XIVE 527 - xive: Fix logic in opal_xive_get_xirr() 528 - xive: Properly initialize new VP and EQ structures 529 - xive: Improve/fix EOI of LSIs 530 - xive: Add FIXME comments about mask/umask races 531 - xive: Fix memory barrier in opal_xive_get_xirr() 532 - xive: Don't try to find a target EQ for prio 0xff 533 - xive: Bump table sizes in direct mode 534 - xive: Properly register escalation interrupts 535 - xive: Split the OPAL irq flags from the internal ones 536 - xive: Don't touch ESB masks unless masking/unmasking 537 - xive: Fix xive_get_ir_targetting() 538 - xive: Cleanup escalation PQ on queue change 539 - xive: Add *any chip* for allocating interrupts 540 - xive: Add chip_id to get_vp_info 541 - xive: Add opal_xive_get/set_vp_info 542 - xive: Add VP alloc/free OPAL functions 543 - xive: Workaround for bad DD1 checker 544 - xive: Add more checks for exploitation mode 545 - xive: Add support for EOIs via OPAL 546 - xive/phb4: Work around broken LSI control on P9 DD1 547 - xive: Forward interrupt names callback 548 - xive: Export opal_xive_reset() arguments in OPAL API 549 - xive: Add interrupt allocator 550 - xive: Implement xive_reset 551 - xive: Don't assert if xive_get_vp() fails 552 - xive: Expose exploitation mode DT properties 553 - xive: Use a constant for max# of chips 554 - xive: Keep track of which interrupts were ever enabled 555 In order to speed up xive reset 556 - xive: Implement internal VP allocator 557 - xive: Add xive_get/set_queue_info 558 - xive: Add helpers to encode and decode VP numbers 559 - xive: Add API to donate pages in indirect mode 560 - xive: Add asynchronous cache updates and update irq targetting 561 - xive: Split xive_provision_cpu() and use cache watch for VP 562 - xive: Add cache scrub to push watch updates to memory 563 - xive: Mark XIVE owned EQs with a specific flag 564 - xive: Use an allocator for EQDs 565 - xive: Break assumption that block ID == chip ID 566 - xive/phb4: Handle bad ESB offsets in PHB4 DD1 567 - xive: Implement get/set_irq_config APIs 568 - xive: Rework xive_set_eq_info() to store all info even when masking 569 - xive: Implement cache watch and use it for EQs 570 - xive: Add locking to some API calls 571 - xive: Add opal_xive_get_irq_info() 572 - xive: Add CPU node "interrupts" properties representing the IPIs 573 - xive: Add basic opal_xive_reset() call and exploitation mode 574 - xive: Add support for escalation interrupts 575 - xive: OPAL API update 576 - xive: Add some dump facility for debugging 577 - xive: Document exploitation mode 578 (Pretty much work in progress) 579 - xive: Indirect table entries must have top bits "type" set 580 - xive: Remove unused field and clarify comment 581 - xive: Provide a way to override some IPI sources 582 - xive: Add helper to retrieve an IPI trigger port 583 - xive: Fix IPI EOI logic in opal_xive_eoi() 584 - xive: Don't try to EOI a masked source 585 - xive: Fix comments in xive_source_set_xive() 586 - xive: Fix comments in xive_get_ive() 587 - xive: Configure forwarding ports 588 - xive: Fix mangling of interrupt server# in opal_get/set_xive() 589 - xive: Fix interrupt number mangling 590 591 592Fast-reboot 593----------- 594- fast-reboot: creset PHBs on fast reboot 595 On fast reboot, perform a creset of all PHBs. This ensures that any PHBs 596 that are fenced will be working after the reboot. 597- fast-reboot: Enable fast reboot with CAPI adapters in CAPI mode 598 CAPI mode is disabled as part of OPAL_SYNC_HOST_REBOOT. 599- opal/fast-reboot: set fw_progress sensor status with IPMI_FW_PCI_INIT. 600 601CAPI 602---- 603 604- hmi: Print CAPP FIR information when handling CAPP malfunction alerts 605 606FSP based systems 607----------------- 608 609- hw/fsp: Do not queue SP and SPCN class messages during reset/reload 610 This could cause soft lockups if FSP reset reload was done while in OPAL 611 During FSP R/R, the FSP is inaccessible and will lose state. Messages to the 612 FSP are generally queued for sending later. 613 614Tests 615----- 616- core/test/run-trace: Reduce number of samples when running under valgrind 617 This reduces 'make check' run time by ~10 seconds on my laptop, 618 and just the run-trace test itself takes 15 seconds less (under valgrind). 619- test/sreset_world: Kind of like Hello World, but from the SRESET vector. 620 A regression test for the mambo implementation of OPAL_SIGNAL_SYSTEM_RESET. 621- nvram-format: Fix endian issues 622 NVRAM formats are always BE, so let's use the sparse annotation to catch 623 any issues (and correct said issues). 624 625 On LE platforms, the test was erroneously passing as with building the 626 nvram-format code on LE we were produces an incorrect NVRAM image. 627 628- test/hello_world: use P9MAMBO to differentiate from P8 629- hdata_to_dt: Specify PVR on command line 630- hdata/test: Add DTS output for the test cases 631- hdata/test: strip blobs from the DT output 632- mambo: add mprintf() 633 634 mprintf() is printf(), but it goes straight to the mambo console. This 635 allows it to be independent of Skiboot's actual console infrastructure 636 so it can be used for debugging the console drivers and for debugging 637 code that runs before the console is setup. 638- generate-fwts-olog: add support for parsing prerror() 639- Add bitmap test 640 The worst test suite ever 641- mambo_utils: add ascii output to hexdump 642- mambo_utils: add p_str <addr> [limit] 643- mambo_utils: make p return a value 644- hello_world: print out full path of missing MAMBO_BINARY 645- print-stb-container: Fix build on centos7 646 647- Travis-ci improvements: 648 - install expect on ubuntu 12.04, disable qemu on 16.04/latest 649 - build and test more on centos7 650 - hello_world: run p9 mambo tests 651 - install systemsim-p8 on centos7 652 - install systemsim-p8 on centos6 653 - install systemsim-p9 654 - enable fedora25 655 - always pull new docker image 656 - add fedora rawhide 657 658- Add fwts annotation for duplicate DT node entries. 659 660 Reference bug: https://github.com/open-power/op-build/issues/751 661- external/fwts: Add 'last-tag' to FWTS olog output 662 This isn't so useful at the moment, but this will make cleaning out 663 crufty old error definitions much easier. 664- external/fwts: Add FWTS olog merge script 665 A script to merge olog error definitions from multiple skiboot versions 666 into a single olog JSON file. Will prompt when conflicting patterns are 667 found to update the pattern, or add both. 668- mambo: fake NVRAM support 669- mambo: Add Fake NVRAM driver 670- external/mambo: add shortcut to print all GPRs 671 672 673 674Contributors 675------------ 676 677Processed 363 csets from 28 developers. 678A total of 18105 lines added, 16499 removed (delta 1606) 679 680Developers with the most changesets 681^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 682 683========================== === ======= 684Developer # % 685========================== === ======= 686Benjamin Herrenschmidt 138 (38.0%) 687Stewart Smith 56 (15.4%) 688Oliver O'Halloran 47 (12.9%) 689Michael Neuling 18 (5.0%) 690Gavin Shan 15 (4.1%) 691Claudio Carvalho 14 (3.9%) 692Vasant Hegde 11 (3.0%) 693Cyril Bur 11 (3.0%) 694Andrew Donnellan 11 (3.0%) 695Ananth N Mavinakayanahalli 5 (1.4%) 696Cédric Le Goater 5 (1.4%) 697Pridhiviraj Paidipeddi 5 (1.4%) 698Shilpasri G Bhat 4 (1.1%) 699Nicholas Piggin 4 (1.1%) 700Russell Currey 3 (0.8%) 701Alistair Popple 2 (0.6%) 702Jack Miller 2 (0.6%) 703Chris Smart 2 (0.6%) 704Matt Brown 1 (0.3%) 705Michael Ellerman 1 (0.3%) 706Frederic Barrat 1 (0.3%) 707Hank Chang 1 (0.3%) 708Willie Liauw 1 (0.3%) 709Werner Fischer 1 (0.3%) 710Jeremy Kerr 1 (0.3%) 711Patrick Williams 1 (0.3%) 712Joel Stanley 1 (0.3%) 713Alexey Kardashevskiy 1 (0.3%) 714========================== === ======= 715 716Developers with the most changed lines 717^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 718 719=========================== ===== ======= 720Developer # % 721=========================== ===== ======= 722Oliver O'Halloran 17961 (56.7%) 723Benjamin Herrenschmidt 5509 (17.4%) 724Cyril Bur 2801 (8.8%) 725Stewart Smith 1649 (5.2%) 726Gavin Shan 653 (2.1%) 727Claudio Carvalho 489 (1.5%) 728Willie Liauw 361 (1.1%) 729Ananth N Mavinakayanahalli 340 (1.1%) 730Andrew Donnellan 315 (1.0%) 731Michael Neuling 240 (0.8%) 732Shilpasri G Bhat 228 (0.7%) 733Nicholas Piggin 219 (0.7%) 734Vasant Hegde 207 (0.7%) 735Russell Currey 158 (0.5%) 736Jack Miller 127 (0.4%) 737Cédric Le Goater 126 (0.4%) 738Chris Smart 95 (0.3%) 739Hank Chang 56 (0.2%) 740Pridhiviraj Paidipeddi 47 (0.1%) 741Alistair Popple 39 (0.1%) 742Matt Brown 29 (0.1%) 743Michael Ellerman 3 (0.0%) 744Alexey Kardashevskiy 2 (0.0%) 745Frederic Barrat 1 (0.0%) 746Werner Fischer 1 (0.0%) 747Jeremy Kerr 1 (0.0%) 748Patrick Williams 1 (0.0%) 749Joel Stanley 1 (0.0%) 750=========================== ===== ======= 751 752Developers with the most lines removed 753^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 754 755=========================== ===== ======= 756Developer # % 757=========================== ===== ======= 758Oliver O'Halloran 8810 (53.4%) 759Ananth N Mavinakayanahalli 98 (0.6%) 760Alistair Popple 9 (0.1%) 761Michael Ellerman 3 (0.0%) 762Werner Fischer 1 (0.0%) 763=========================== ===== ======= 764 765Developers with the most signoffs 766^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 767 768Total 322 769 770======================== ===== ======= 771Developer # % 772======================== ===== ======= 773Stewart Smith 307 (95.3%) 774Michael Neuling 6 (1.9%) 775Oliver O'Halloran 3 (0.9%) 776Benjamin Herrenschmidt 2 (0.6%) 777Vaidyanathan Srinivasan 1 (0.3%) 778Hank Chang 1 (0.3%) 779Jack Miller 1 (0.3%) 780Gavin Shan 1 (0.3%) 781======================== ===== ======= 782 783Developers with the most reviews 784^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 785 786Total: 45 787 788======================== ===== ======= 789Developer # % 790======================== ===== ======= 791Vasant Hegde 10 (22.2%) 792Andrew Donnellan 9 (20.0%) 793Russell Currey 6 (13.3%) 794Cédric Le Goater 5 (11.1%) 795Oliver O'Halloran 4 (8.9%) 796Gavin Shan 3 (6.7%) 797Vaidyanathan Srinivasan 2 (4.4%) 798Alistair Popple 2 (4.4%) 799Frederic Barrat 2 (4.4%) 800Mahesh Salgaonkar 1 (2.2%) 801Cyril Bur 1 (2.2%) 802======================== ===== ======= 803 804Developers with the most test credits 805^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 806 807Total 11 808 809======================== ===== ======= 810Developer # % 811======================== ===== ======= 812Willie Liauw 4 (36.4%) 813Claudio Carvalho 3 (27.3%) 814Gavin Shan 1 (9.1%) 815Michael Neuling 1 (9.1%) 816Pridhiviraj Paidipeddi 1 (9.1%) 817Chris Smart 1 (9.1%) 818======================== ===== ======= 819 820Developers who gave the most tested-by credits 821^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 822 823Total 11 824 825========================== ===== ======= 826Developer # % 827========================== ===== ======= 828Gavin Shan 4 (36.4%) 829Stewart Smith 4 (36.4%) 830Chris Smart 1 (9.1%) 831Oliver O'Halloran 1 (9.1%) 832Ananth N Mavinakayanahalli 1 (9.1%) 833========================== ===== ======= 834 835Developers with the most report credits 836^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 837 838Total 7 839 840========================== === ======= 841Developer # % 842========================== === ======= 843Hank Chang 4 (57.1%) 844Guilherme G. Piccoli 1 (14.3%) 845Colin Ian King 1 (14.3%) 846Pradipta Ghosh 1 (14.3%) 847========================== === ======= 848 849 850Developers who gave the most report credits 851^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 852 853Total 7 854 855========================== === ======= 856Developer # % 857========================== === ======= 858Gavin Shan 5 (71.4%) 859Andrew Donnellan 1 (14.3%) 860Jeremy Kerr 1 (14.3%) 861========================== === ======= 862