1.. _skiboot-5.9.5: 2 3============= 4skiboot-5.9.5 5============= 6 7skiboot 5.9.5 was released on Wednesday December 13th, 2017. It replaces 8:ref:`skiboot-5.9.4` as the current stable release in the 5.9.x series. 9 10Over :ref:`skiboot-5.9.4`, we have a few bug fixes, they are: 11 12- Fix *extremely* rare race in timer code. 13- xive: Ensure VC informational FIRs are masked 14 15 Some HostBoot versions leave those as checkstop, they are harmless 16 and can sometimes occur during normal operations. 17- xive: Fix occasional VC checkstops in xive_reset 18 19 The current workaround for the scrub bug described in 20 __xive_cache_scrub() has an issue in that it can leave 21 dirty invalid entries in the cache. 22 23 When cleaning up EQs or VPs during reset, if we then 24 remove the underlying indirect page for these entries, 25 the XIVE will checkstop when trying to flush them out 26 of the cache. 27 28 This replaces the existing workaround with a new pair of 29 workarounds for VPs and EQs: 30 31 - The VP one does the dummy watch on another entry than 32 the one we scrubbed (which does the job of pushing old 33 stores out) using an entry that is known to be backed by 34 a permanent indirect page. 35 - The EQ one switches to a more efficient workaround 36 which consists of doing a non-side-effect ESB load from 37 the EQ's ESe control bits. 38- io: Add load_wait() helper 39 40 This uses the standard form twi/isync pair to ensure a load 41 is consumed by the core before continuing. This can be necessary 42 under some circumstances for example when having the following 43 sequence: 44 45 - Store reg A 46 - Load reg A (ensure above store pushed out) 47 - delay loop 48 - Store reg A 49 50 IE, a mandatory delay between 2 stores. In theory the first store 51 is only guaranteed to rach the device after the load from the same 52 location has completed. However the processor will start executing 53 the delay loop without waiting for the return value from the load. 54 55 This construct enforces that the delay loop isn't executed until 56 the load value has been returned. 57- xive: Do not return a trigger page for an escalation interrupt 58 59 This is bogus, we don't support them. (Thankfully the callers 60 didn't actually try to use this on escalation interrupts). 61- xive: Mark a freed IRQ's IVE as valid and masked 62 63 Removing the valid bit means a FIR will trip if it's accessed 64 inadvertently. Under some circumstances, the XIVE will speculatively 65 access an IVE for a masked interrupt and trip it. So make sure that 66 freed entries are still marked valid (but masked). 67- hw/nx: Fix NX BAR assignments 68 69 The NX rng BAR is used by each core to source random numbers for the 70 DARN instruction. Currently we configure each core to use the NX rng of 71 the chip that it exists on. Unfortunately, the NX can be deconfigured by 72 hostboot and in this case we need to use the NX of a different chip. 73 74 This patch moves the BAR assignments for the NX into the normal nx-rng 75 init path. This lets us check if the normal (chip local) NX is active 76 when configuring which NX a core should use so that we can fallback 77 gracefully. 78