1 /* Copyright 2013-2014 IBM Corp. 2 * 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or 12 * implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 /* 18 * PCI Configuration space definitions 19 */ 20 #ifndef __PCI_CFG_H 21 #define __PCI_CFG_H 22 23 /* Common cfg space header */ 24 #define PCI_CFG_VENDOR_ID 0x0000 25 #define PCI_CFG_DEVICE_ID 0x0002 26 #define PCI_CFG_CMD 0x0004 27 #define PCI_CFG_CMD_IO_EN 0x0001 28 #define PCI_CFG_CMD_MEM_EN 0x0002 29 #define PCI_CFG_CMD_BUS_MASTER_EN 0x0004 30 #define PCI_CFG_CMD_PERR_RESP 0x0040 31 #define PCI_CFG_CMD_SERR_EN 0x0100 32 #define PCI_CFG_CMD_INTx_DIS 0x0400 33 #define PCI_CFG_STAT 0x0006 34 #define PCI_CFG_STAT_INTx 0x0008 35 #define PCI_CFG_STAT_CAP 0x0010 36 #define PCI_CFG_STAT_MDATAPERR 0x0100 37 #define PCI_CFG_STAT_SENT_TABORT 0x0800 38 #define PCI_CFG_STAT_RECV_TABORT 0x1000 39 #define PCI_CFG_STAT_RECV_MABORT 0x2000 40 #define PCI_CFG_STAT_SENT_SERR 0x4000 41 #define PCI_CFG_STAT_RECV_PERR 0x8000 42 #define PCI_CFG_REV_ID 0x0008 43 #define PCI_CFG_CLAS_CODE 0x0009 44 #define PCI_CFG_CACHE_LINE_SIZE 0x000c 45 #define PCI_CFG_LAT_TIMER 0x000d 46 #define PCI_CFG_HDR_TYPE 0x000e 47 #define PCI_CFG_BIST 0x000f 48 #define PCI_CFG_BAR0 0x0010 49 #define PCI_CFG_BAR_TYPE 0x00000001 50 #define PCI_CFG_BAR_TYPE_MEM 0x00000000 51 #define PCI_CFG_BAR_TYPE_IO 0x00000001 52 #define PCI_CFG_BAR_MEM64 0x00000004 53 #define PCI_CFG_BAR_MEM_PREFETCH 0x00000008 54 #define PCI_CFG_BAR1 0x0014 55 56 /* Type 0 fields */ 57 #define PCI_CFG_BAR2 0x0018 58 #define PCI_CFG_BAR3 0x001c 59 #define PCI_CFG_BAR4 0x0020 60 #define PCI_CFG_BAR5 0x0024 61 #define PCI_CFG_CARDBUS_CIS 0x0028 62 #define PCI_CFG_SUBSYS_VENDOR_ID 0x002c 63 #define PCI_CFG_SUBSYS_ID 0x002e 64 #define PCI_CFG_ROMBAR 0x0030 65 #define PCI_CFG_CAP 0x0034 66 #define PCI_CFG_INT_LINE 0x003c 67 #define PCI_CFG_INT_PIN 0x003d 68 #define PCI_CFG_INT_MIN_GNT 0x003e 69 #define PCI_CFG_INT_MAX_LAT 0x003f 70 71 /* Type 1 fields */ 72 #define PCI_CFG_PRIMARY_BUS 0x0018 73 #define PCI_CFG_SECONDARY_BUS 0x0019 74 #define PCI_CFG_SUBORDINATE_BUS 0x001a 75 #define PCI_CFG_SEC_LAT_TIMER 0x001b 76 #define PCI_CFG_IO_BASE 0x001c 77 #define PCI_CFG_IO_LIMIT 0x001d 78 #define PCI_CFG_SECONDARY_STATUS 0x001e 79 #define PCI_CFG_MEM_BASE 0x0020 80 #define PCI_CFG_MEM_LIMIT 0x0022 81 #define PCI_CFG_PREF_MEM_BASE 0x0024 82 #define PCI_CFG_PREF_MEM_LIMIT 0x0026 83 #define PCI_CFG_PREF_MEM_BASE_U32 0x0028 84 #define PCI_CFG_PREF_MEM_LIMIT_U32 0x002c 85 #define PCI_CFG_IO_BASE_U16 0x0030 86 #define PCI_CFG_IO_LIMIT_U16 0x0032 87 #define PCI_CFG_BR_CAP 0x0034 /* Same as type 0 */ 88 #define PCI_CFG_BR_ROMBAR 0x0038 /* Different from type 0 */ 89 #define PCI_CFG_BR_INT_LINE 0x003c /* Same as type 0 */ 90 #define PCI_CFG_BR_INT_PIN 0x003d /* Same as type 0 */ 91 #define PCI_CFG_BRCTL 0x003e 92 #define PCI_CFG_BRCTL_PERR_RESP_EN 0x0001 93 #define PCI_CFG_BRCTL_SERR_EN 0x0002 94 #define PCI_CFG_BRCTL_ISA_EN 0x0004 95 #define PCI_CFG_BRCTL_VGA_EN 0x0008 96 #define PCI_CFG_BRCTL_VGA_16BIT 0x0010 97 #define PCI_CFG_BRCTL_MABORT_REPORT 0x0020 98 #define PCI_CFG_BRCTL_SECONDARY_RESET 0x0040 99 #define PCI_CFG_BRCTL_FAST_BACK2BACK 0x0080 100 #define PCI_CFG_BRCTL_PRI_DISC_TIMER 0x0100 101 #define PCI_CFG_BRCTL_SEC_DISC_TIMER 0x0200 102 #define PCI_CFG_BRCTL_DISC_TIMER_STAT 0x0400 103 #define PCI_CFG_BRCTL_DISC_TIMER_SERR 0x0800 104 105 /* 106 * Standard capabilties 107 */ 108 #define PCI_CFG_CAP_ID 0 109 #define PCI_CFG_CAP_NEXT 1 110 111 /* PCI Power Management capability */ 112 #define PCI_CFG_CAP_ID_PM 1 113 114 /* PCI bridge subsystem ID capability */ 115 #define PCI_CFG_CAP_ID_SUBSYS_VID 0x0d 116 #define PCICAP_SUBSYS_VID_VENDOR 4 117 #define PCICAP_SUBSYS_VID_DEVICE 6 118 119 /* Vendor specific capability */ 120 #define PCI_CFG_CAP_ID_VENDOR 9 121 122 /* PCI Express capability */ 123 #define PCI_CFG_CAP_ID_EXP 0x10 124 /* PCI Express capability fields */ 125 #define PCICAP_EXP_CAPABILITY_REG 0x02 126 #define PCICAP_EXP_CAP_VERSION 0x000f 127 #define PCICAP_EXP_CAP_TYPE 0x00f0 128 #define PCIE_TYPE_ENDPOINT 0x0 129 #define PCIE_TYPE_LEGACY 0x1 130 #define PCIE_TYPE_ROOT_PORT 0x4 131 #define PCIE_TYPE_SWITCH_UPPORT 0x5 132 #define PCIE_TYPE_SWITCH_DNPORT 0x6 133 #define PCIE_TYPE_PCIE_TO_PCIX 0x7 134 #define PCIE_TYPE_PCIX_TO_PCIE 0x8 135 #define PCIE_TYPE_RC_INTEGRATED 0x9 136 #define PCIE_TYPE_RC_EVT_COLL 0xa 137 #define PCICAP_EXP_CAP_SLOT 0x0100 138 #define PCICAP_EXP_CAP_MSI_NUM 0x3e00 139 #define PCICAP_EXP_CAP_TCS_ROUTING 0x4000 140 #define PCICAP_EXP_DEVCAP 0x04 141 #define PCICAP_EXP_DEVCAP_MPSS 0x00000007 142 #define PCIE_MPSS_128 0 143 #define PCIE_MPSS_256 1 144 #define PCIE_MPSS_512 2 145 #define PCIE_MPSS_1024 3 146 #define PCIE_MPSS_2048 4 147 #define PCIE_MPSS_4096 5 148 #define PCICAP_EXP_DEVCAP_PHANT 0x00000018 149 #define PCIE_PHANTOM_NONE 0 150 #define PCIE_PHANTOM_1MSB 1 151 #define PCIE_PHANTOM_2MSB 2 152 #define PCIE_PHANTOM_3MSB 3 153 #define PCICAP_EXP_DEVCAP_EXTTAG 0x00000020 154 #define PCICAP_EXP_DEVCAP_L0SL 0x000001c0 155 #define PCIE_L0SL_MAX_64NS 0 156 #define PCIE_L0SL_MAX_128NS 1 157 #define PCIE_L0SL_MAX_256NS 2 158 #define PCIE_L0SL_MAX_512NS 3 159 #define PCIE_L0SL_MAX_1US 4 160 #define PCIE_L0SL_MAX_2US 5 161 #define PCIE_L0SL_MAX_4US 6 162 #define PCIE_L0SL_MAX_NO_LIMIT 7 163 #define PCICAP_EXP_DEVCAP_L1L 0x00000e00 164 #define PCIE_L1L_MAX_1US 0 165 #define PCIE_L1L_MAX_2US 1 166 #define PCIE_L1L_MAX_4US 2 167 #define PCIE_L1L_MAX_8US 3 168 #define PCIE_L1L_MAX_16US 4 169 #define PCIE_L1L_MAX_32US 5 170 #define PCIE_L1L_MAX_64US 6 171 #define PCIE_L1L_MAX_NO_LIMIT 7 172 #define PCICAP_EXP_ROLE_BASED_ERR 0x00008000 173 #define PCICAP_EXP_DEVCAP_PWRVAL 0x03fc0000 174 #define PCICAP_EXP_DEVCAP_PWRSCA 0x0c000000 175 #define PCIE_SLOT_PWR_SCALE_1x 0 176 #define PCIE_SLOT_PWR_SCALE_0d1x 1 177 #define PCIE_SLOT_PWR_SCALE_0d01x 2 178 #define PCIE_SLOT_PWR_SCALE_0d001x 3 179 #define PCICAP_EXP_DEVCAP_FUNC_RESET 0x10000000 180 #define PCICAP_EXP_DEVCTL 0x08 181 #define PCICAP_EXP_DEVCTL_CE_REPORT 0x0001 182 #define PCICAP_EXP_DEVCTL_NFE_REPORT 0x0002 183 #define PCICAP_EXP_DEVCTL_FE_REPORT 0x0004 184 #define PCICAP_EXP_DEVCTL_UR_REPORT 0x0008 185 #define PCICAP_EXP_DEVCTL_RELAX_ORD 0x0010 186 #define PCICAP_EXP_DEVCTL_MPS 0x00e0 187 #define PCIE_MPS_128B 0 188 #define PCIE_MPS_256B 1 189 #define PCIE_MPS_512B 2 190 #define PCIE_MPS_1024B 3 191 #define PCIE_MPS_2048B 4 192 #define PCIE_MPS_4096B 5 193 #define PCICAP_EXP_DEVCTL_EXT_TAG 0x0100 194 #define PCICAP_EXP_DEVCTL_PHANTOM 0x0200 195 #define PCICAP_EXP_DEVCTL_AUX_POW_PM 0x0400 196 #define PCICAP_EXP_DEVCTL_NO_SNOOP 0x0800 197 #define PCICAP_EXP_DEVCTL_MRRS 0x7000 198 #define PCIE_MRSS_128B 0 199 #define PCIE_MRSS_256B 1 200 #define PCIE_MRSS_512B 2 201 #define PCIE_MRSS_1024B 3 202 #define PCIE_MRSS_2048B 4 203 #define PCIE_MRSS_4096B 5 204 #define PCICAP_EXP_DEVCTL_PCIX_RETRY 0x8000 /* PCIe - PCIX bridges only */ 205 #define PCICAP_EXP_DEVCTL_FUNC_RESET 0x8000 /* all others */ 206 #define PCICAP_EXP_DEVSTAT 0x0a 207 #define PCICAP_EXP_DEVSTAT_CE 0x0001 208 #define PCICAP_EXP_DEVSTAT_NFE 0x0002 209 #define PCICAP_EXP_DEVSTAT_FE 0x0004 210 #define PCICAP_EXP_DEVSTAT_UE 0x0008 211 #define PCICAP_EXP_DEVSTAT_AUX_POW 0x0010 212 #define PCICAP_EXP_DEVSTAT_TPEND 0x0020 213 #define PCICAP_EXP_LCAP 0x0c 214 #define PCICAP_EXP_LCAP_MAXSPD 0x0000000f 215 #define PCIE_LSPEED_VECBIT_0 0x1 216 #define PCIE_LSPEED_VECBIT_1 0x2 217 #define PCIE_LSPEED_VECBIT_2 0x3 218 #define PCIE_LSPEED_VECBIT_3 0x4 219 #define PCIE_LSPEED_VECBIT_4 0x5 220 #define PCIE_LSPEED_VECBIT_5 0x6 221 #define PCIE_LSPEED_VECBIT_6 0x7 222 #define PCICAP_EXP_LCAP_MAXWDTH 0x000003f0 223 #define PCIE_LWIDTH_1X 1 224 #define PCIE_LWIDTH_2X 2 225 #define PCIE_LWIDTH_4X 4 226 #define PCIE_LWIDTH_8X 8 227 #define PCIE_LWIDTH_12X 12 228 #define PCIE_LWIDTH_16X 16 229 #define PCIE_LWIDTH_32X 32 230 #define PCICAP_EXP_LCAP_ASPM_L0S 0x00000400 231 #define PCICAP_EXP_LCAP_ASPM_L1 0x00000800 232 #define PCICAP_EXP_LCAP_L0S_EXLT 0x00007000 233 #define PCIE_L0S_EXLT_LESS_64NS 0 234 #define PCIE_L0S_EXLT_64NS_128NS 1 235 #define PCIE_L0S_EXLT_128NS_256NS 2 236 #define PCIE_L0S_EXLT_256NS_512NS 3 237 #define PCIE_L0S_EXLT_512NS_1US 4 238 #define PCIE_L0S_EXLT_1US_2US 5 239 #define PCIE_L0S_EXLT_2US_4US 6 240 #define PCIE_L0S_EXLT_MORE_4US 7 241 #define PCICAP_EXP_LCAP_L1_EXLT 0x00038000 242 #define PCIE_L1_EXLT_LESS_1US 0 243 #define PCIE_L1_EXLT_1US_2US 1 244 #define PCIE_L1_EXLT_2US_4US 2 245 #define PCIE_L1_EXLT_4US_8US 3 246 #define PCIE_L1_EXLT_8US_16US 4 247 #define PCIE_L1_EXLT_16US_32US 5 248 #define PCIE_L1_EXLT_32US_64US 6 249 #define PCIE_L1_EXLT_MORE_64US 7 250 #define PCICAP_EXP_LCAP_CLK_PM 0x00040000 251 #define PCICAP_EXP_LCAP_SURP_DWN_ERR 0x00080000 252 #define PCICAP_EXP_LCAP_DL_ACT_REP 0x00100000 253 #define PCICAP_EXP_LCAP_LNKBWDTH_NOTF 0x00200000 254 #define PCICAP_EXP_LCAP_ASPM_OPT_CMPL 0x00400000 255 #define PCICAP_EXP_LCAP_PORTNUM 0xff000000 256 #define PCICAP_EXP_LCTL 0x10 257 #define PCICAP_EXP_LCTL_ASPM_L0S 0x0001 258 #define PCICAP_EXP_LCTL_ASPM_L1 0x0002 259 #define PCICAP_EXP_LCTL_RCB 0x0008 /* RO on root ports */ 260 #define PCICAP_EXP_LCTL_LINK_DIS 0x0010 261 #define PCICAP_EXP_LCTL_LINK_RETRAIN 0x0020 262 #define PCICAP_EXP_LCTL_COMMON_CLK 0x0040 263 #define PCICAP_EXP_LCTL_EXT_SYNCH 0x0080 264 #define PCICAP_EXP_LCTL_CLOCK_PM 0x0100 265 #define PCICAP_EXP_LCTL_HW_AWIDTH_DIS 0x0200 266 #define PCICAP_EXP_LCTL_LBWM_INT_EN 0x0400 267 #define PCICAP_EXP_LCTL_LAWD_INT_EN 0x0800 268 #define PCICAP_EXP_LSTAT 0x12 269 #define PCICAP_EXP_LSTAT_SPEED 0x000f /* use PCIE_LSPEED_* consts */ 270 #define PCICAP_EXP_LSTAT_WIDTH 0x03f0 /* use PCIE_LWIDTH_* consts */ 271 #define PCICAP_EXP_LSTAT_TRAINING 0x0800 272 #define PCICAP_EXP_LSTAT_SLOTCLKCFG 0x1000 273 #define PCICAP_EXP_LSTAT_DLLL_ACT 0x2000 274 #define PCICAP_EXP_LSTAT_LBWM_STAT 0x4000 275 #define PCICAP_EXP_LSTAT_LAWS_STAT 0x8000 276 #define PCICAP_EXP_SLOTCAP 0x14 277 #define PCICAP_EXP_SLOTCAP_ATTNB 0x00000001 278 #define PCICAP_EXP_SLOTCAP_PWCTRL 0x00000002 279 #define PCICAP_EXP_SLOTCAP_MRLSENS 0x00000004 280 #define PCICAP_EXP_SLOTCAP_ATTNI 0x00000008 281 #define PCICAP_EXP_SLOTCAP_PWRI 0x00000010 282 #define PCICAP_EXP_SLOTCAP_HPLUG_SURP 0x00000020 283 #define PCICAP_EXP_SLOTCAP_HPLUG_CAP 0x00000040 284 #define PCICAP_EXP_SLOTCAP_SPLVA 0x00007f80 285 #define PCICAP_EXP_SLOTCAP_SPLSC 0x00018000 286 #define PCICAP_EXP_SLOTCAP_EIP 0x00020000 287 #define PCICAP_EXP_SLOTCAP_NO_CMDCOMP 0x00040000 288 #define PCICAP_EXP_SLOTCAP_PSLOT 0xfff80000 289 #define PCICAP_EXP_SLOTCTL 0x18 290 #define PCICAP_EXP_SLOTCTL_ATTNB 0x0001 291 #define PCICAP_EXP_SLOTCTL_PFLT 0x0002 292 #define PCICAP_EXP_SLOTCTL_MRLSENSE 0x0004 293 #define PCICAP_EXP_SLOTCTL_PDETECT 0x0008 294 #define PCICAP_EXP_SLOTCTL_CMDCOMPINT 0x0010 295 #define PCICAP_EXP_SLOTCTL_HPINT 0x0020 296 #define PCICAP_EXP_SLOTCTL_ATTNI 0x00c0 297 #define PCIE_INDIC_ON 1 298 #define PCIE_INDIC_BLINK 2 299 #define PCIE_INDIC_OFF 3 300 #define PCICAP_EXP_SLOTCTL_PWRI 0x0300 /* Use PCIE_INDIC_* consts */ 301 #define PCICAP_EXP_SLOTCTL_PWRCTLR 0x0400 302 #define PCICAP_EXP_SLOTCTL_EIC 0x0800 303 #define PCICAP_EXP_SLOTCTL_DLLSTCHG 0x1000 304 #define PCICAP_EXP_SLOTSTAT 0x1a 305 #define PCICAP_EXP_SLOTSTAT_ATTNBCH 0x0001 306 #define PCICAP_EXP_SLOTSTAT_PWRFLTCH 0x0002 307 #define PCICAP_EXP_SLOTSTAT_MRLSENSCH 0x0004 308 #define PCICAP_EXP_SLOTSTAT_PDETECTCH 0x0008 309 #define PCICAP_EXP_SLOTSTAT_CMDCOMPCH 0x0010 310 #define PCICAP_EXP_SLOTSTAT_MRLSENSST 0x0020 311 #define PCICAP_EXP_SLOTSTAT_PDETECTST 0x0040 312 #define PCICAP_EXP_SLOTSTAT_EIS 0x0080 313 #define PCICAP_EXP_SLOTSTAT_DLLSTCH 0x0100 314 #define PCICAP_EXP_RC 0x1c 315 #define PCICAP_EXP_RC_SYSERR_ON_CE 0x0001 316 #define PCICAP_EXP_RC_SYSERR_ON_NFE 0x0002 317 #define PCICAP_EXP_RC_SYSERR_ON_FE 0x0004 318 #define PCICAP_EXP_RC_PME_INT_EN 0x0008 319 #define PCICAP_EXP_RC_CRS_VISIBLE 0x0010 320 #define PCICAP_EXP_RCAP 0x1e 321 #define PCICAP_EXP_RCAP_CRS_VISIBLE 0x0001 322 #define PCICAP_EXP_RSTAT 0x20 323 #define PCICAP_EXP_RSTAT_PME_RID 0x0000ffff 324 #define PCICAP_EXP_RSTAT_PME_STATUS 0x00010000 325 #define PCICAP_EXP_RSTAT_PME_PENDING 0x00020000 326 #define PCIECAP_EXP_DCAP2 0x24 327 #define PCICAP_EXP_DCAP2_CMPTOUT 0x0000000f 328 #define PCICAP_EXP_DCAP2_CMPTOUT_DIS 0x00000010 329 #define PCICAP_EXP_DCAP2_ARI_FWD 0x00000020 330 #define PCICAP_EXP_DCAP2_ATOMIC_RTE 0x00000040 331 #define PCICAP_EXP_DCAP2_ATOMIC32 0x00000080 332 #define PCICAP_EXP_DCAP2_ATOMIC64 0x00000100 333 #define PCICAP_EXP_DCAP2_CAS128 0x00000200 334 #define PCICAP_EXP_DCAP2_NORO_PRPR 0x00000400 335 #define PCICAP_EXP_DCAP2_LTR 0x00000800 336 #define PCICAP_EXP_DCAP2_TPHCOMP 0x00001000 337 #define PCICAP_EXP_DCAP2_TPHCOMP_EXT 0x00002000 338 #define PCICAP_EXP_DCAP2_OBFF_MSG 0x00040000 339 #define PCICAP_EXP_DCAP2_OBFF_WAKE 0x00080000 340 #define PCICAP_EXP_DCAP2_EXTFMT 0x00100000 341 #define PCICAP_EXP_DCAP2_EETLP_PFX 0x00200000 342 #define PCICAP_EXP_DCAP2_MAXEETP 0x00c00000 343 #define PCIE_EETLPP_1 1 344 #define PCIE_EETLPP_2 2 345 #define PCIE_EETLPP_3 3 346 #define PCIE_EETLPP_4 0 347 #define PCICAP_EXP_DCTL2 0x28 348 #define PCICAP_EXP_DCTL2_CMPTOUT 0x000f 349 #define PCICAP_EXP_DCTL2_CMPTOUT_DIS 0x0010 350 #define PCICAP_EXP_DCTL2_ARI_FWD 0x0020 351 #define PCICAP_EXP_DCTL2_ATOMIC_REQ 0x0040 352 #define PCICAP_EXP_DCTL2_ATOMIC_EGBLK 0x0080 353 #define PCICAP_EXP_DCTL2_IDO_REQ 0x0100 354 #define PCICAP_EXP_DCTL2_IDO_COMPL 0x0200 355 #define PCICAP_EXP_DCTL2_LTR 0x0400 356 #define PCICAP_EXP_DCTL2_OBFF 0x6000 357 #define PCIE_OBFF_MODE_DISABLED 0 358 #define PCIE_OBFF_MODE_MSG_A 1 359 #define PCIE_OBFF_MODE_MSG_B 2 360 #define PCIE_OBFF_MODE_WAKE 3 361 #define PCICAP_EXP_DCTL2_EETLPP_BLK 0x8000 362 #define PCICAP_EXP_DSTA2 0x2a 363 #define PCICAP_EXP_LCAP2 0x2c 364 #define PCICAP_EXP_LCAP2_SP_2d5GTs 0x00000002 365 #define PCICAP_EXP_LCAP2_SP_5d0GTs 0x00000004 366 #define PCICAP_EXP_LCAP2_SP_8d0GTs 0x00000008 367 #define PCICAP_EXP_LCAP2_XLINK 0x00000100 368 #define PCICAP_EXP_LCTL2 0x30 369 #define PCICAP_EXP_LCTL2_TLSPD 0x000f /* use PCIE_LSPEED_ consts */ 370 #define PCICAP_EXP_LCTL2_ENTER_COMPL 0x0010 371 #define PCICAP_EXP_LCTL2_HWAUTSPDIS 0x0020 372 #define PCICAP_EXP_LCTL2_SEL_DEEMPH 0x0040 373 #define PCICAP_EXP_LCTL2_XMTMARG 0x0380 374 #define PCICAP_EXP_LCTL2_ENTER_MCOMPL 0x0400 375 #define PCICAP_EXP_LCTL2_COMPL_SOS 0x0800 376 #define PCICAP_EXP_LCTL2_CMPPDEM 0xf000 377 #define PCICAP_EXP_LSTA2 0x32 378 #define PCICAP_EXP_LSTA2_DEMPH_LVL 0x0001 379 #define PCICAP_EXP_LSTA2_EQ_COMPLETE 0x0002 380 #define PCICAP_EXP_LSTA2_EQ_PH1_OK 0x0004 381 #define PCICAP_EXP_LSTA2_EQ_PH2_OK 0x0008 382 #define PCICAP_EXP_LSTA2_EQ_PH3_OK 0x0010 383 #define PCICAP_EXP_LSTA2_LINK_EQ_REQ 0x0020 384 #define PCICAP_EXP_SCAP2 0x34 385 #define PCICAP_EXP_SCTL2 0x38 386 #define PCICAP_EXP_SSTA2 0x3a 387 388 /* 389 * PCI-E Extended capabilties 390 */ 391 #define PCI_CFG_ECAP_START 0x100 392 #define PCI_CFG_ECAP_ID 0x0000ffff 393 #define PCI_CFG_ECAP_VERS 0x000f0000 394 #define PCI_CFG_ECAP_NEXT 0xfff00000 395 396 /* AER Ext. Capability */ 397 #define PCIECAP_ID_AER 0x0001 398 #define PCIECAP_AER_UE_STATUS 0x04 399 #define PCIECAP_AER_UE_DLP 0x00000010 400 #define PCIECAP_AER_UE_SURPRISE_DOWN 0x00000020 401 #define PCIECAP_AER_UE_POISON_TLP 0x00001000 402 #define PCIECAP_AER_UE_FLOW_CTL_PROT 0x00002000 403 #define PCIECAP_AER_UE_COMPL_TIMEOUT 0x00004000 404 #define PCIECAP_AER_UE_COMPL_ABORT 0x00008000 405 #define PCIECAP_AER_UE_UNEXP_COMPL 0x00010000 406 #define PCIECAP_AER_UE_RECV_OVFLOW 0x00020000 407 #define PCIECAP_AER_UE_MALFORMED_TLP 0x00040000 408 #define PCIECAP_AER_UE_ECRC 0x00080000 409 #define PCIECAP_AER_UE_UNSUPP_REQ 0x00100000 410 #define PCIECAP_AER_UE_ACS_VIOLATION 0x00200000 411 #define PCIECAP_AER_UE_INTERNAL 0x00400000 412 #define PCIECAP_AER_UE_MC_BLKD_TLP 0x00800000 413 #define PCIECAP_AER_UE_ATOMIC_EGBLK 0x01000000 414 #define PCIECAP_AER_UE_TLP_PRFX_BLK 0x02000000 415 #define PCIECAP_AER_UE_MASK 0x08 416 #define PCIECAP_AER_UE_MASK_DLLP 0x00000010 417 #define PCIECAP_AER_UE_MASK_SURPRISE_DOWN 0x00000020 418 #define PCIECAP_AER_UE_MASK_POISON_TLP 0x00001000 419 #define PCIECAP_AER_UE_MASK_FLOW_CTL_PROT 0x00002000 420 #define PCIECAP_AER_UE_MASK_COMPL_TIMEOUT 0x00004000 421 #define PCIECAP_AER_UE_MASK_COMPL_ABORT 0x00008000 422 #define PCIECAP_AER_UE_MASK_UNEXP_COMPL 0x00010000 423 #define PCIECAP_AER_UE_MASK_RECV_OVFLOW 0x00020000 424 #define PCIECAP_AER_UE_MASK_MALFORMED_TLP 0x00040000 425 #define PCIECAP_AER_UE_MASK_ECRC 0x00080000 426 #define PCIECAP_AER_UE_MASK_UNSUPP_REQ 0x00100000 427 #define PCIECAP_AER_UE_SEVERITY 0x0c 428 #define PCIECAP_AER_UE_SEVERITY_DLLP 0x00000010 429 #define PCIECAP_AER_UE_SEVERITY_SURPRISE_DOWN 0x00000020 430 #define PCIECAP_AER_UE_SEVERITY_POISON_TLP 0x00001000 431 #define PCIECAP_AER_UE_SEVERITY_FLOW_CTL_PROT 0x00002000 432 #define PCIECAP_AER_UE_SEVERITY_COMPL_TIMEOUT 0x00004000 433 #define PCIECAP_AER_UE_SEVERITY_COMPL_ABORT 0x00008000 434 #define PCIECAP_AER_UE_SEVERITY_UNEXP_COMPL 0x00010000 435 #define PCIECAP_AER_UE_SEVERITY_RECV_OVFLOW 0x00020000 436 #define PCIECAP_AER_UE_SEVERITY_MALFORMED_TLP 0x00040000 437 #define PCIECAP_AER_UE_SEVERITY_ECRC 0x00080000 438 #define PCIECAP_AER_UE_SEVERITY_UNSUPP_REQ 0x00100000 439 #define PCIECAP_AER_UE_SEVERITY_INTERNAL 0x00400000 440 #define PCIECAP_AER_CE_STATUS 0x10 441 #define PCIECAP_AER_CE_RECVR_ERR 0x00000001 442 #define PCIECAP_AER_CE_BAD_TLP 0x00000040 443 #define PCIECAP_AER_CE_BAD_DLLP 0x00000080 444 #define PCIECAP_AER_CE_REPLAY_ROLLVR 0x00000100 445 #define PCIECAP_AER_CE_REPLAY_TMR_TO 0x00001000 446 #define PCIECAP_AER_CE_ADV_NONFATAL 0x00002000 447 #define PCIECAP_AER_CE_CORTD_INTERNAL 0x00004000 448 #define PCIECAP_AER_CE_HDR_LOG_OVFL 0x00008000 449 #define PCIECAP_AER_CE_MASK 0x14 450 #define PCIECAP_AER_CE_MASK_RECVR_ERR 0x00000001 451 #define PCIECAP_AER_CE_MASK_BAD_TLP 0x00000040 452 #define PCIECAP_AER_CE_MASK_BAD_DLLP 0x00000080 453 #define PCIECAP_AER_CE_MASK_REPLAY_ROLLVR 0x00000100 454 #define PCIECAP_AER_CE_MASK_REPLAY_TMR_TO 0x00001000 455 #define PCIECAP_AER_CE_MASK_ADV_NONFATAL 0x00002000 456 #define PCIECAP_AER_CE_MASK_CORTD_INTERNAL 0x00004000 457 #define PCIECAP_AER_CE_MASK_HDR_LOG_OVFL 0x00008000 458 #define PCIECAP_AER_CAPCTL 0x18 459 #define PCIECAP_AER_CAPCTL_FPTR 0x0000001f 460 #define PCIECAP_AER_CAPCTL_ECRCG_CAP 0x00000020 461 #define PCIECAP_AER_CAPCTL_ECRCG_EN 0x00000040 462 #define PCIECAP_AER_CAPCTL_ECRCC_CAP 0x00000080 463 #define PCIECAP_AER_CAPCTL_ECRCC_EN 0x00000100 464 #define PCIECAP_AER_CAPCTL_MHREC_CAP 0x00000200 465 #define PCIECAP_AER_CAPCTL_MHREC_EN 0x00000400 466 #define PCIECAP_AER_CAPCTL_TLPPL_PR 0x00000800 467 #define PCIECAP_AER_HDR_LOG0 0x1c 468 #define PCIECAP_AER_HDR_LOG1 0x20 469 #define PCIECAP_AER_HDR_LOG2 0x24 470 #define PCIECAP_AER_HDR_LOG3 0x28 471 #define PCIECAP_AER_RERR_CMD 0x2c 472 #define PCIECAP_AER_RERR_CMD_FE 0x00000001 473 #define PCIECAP_AER_RERR_CMD_NFE 0x00000002 474 #define PCIECAP_AER_RERR_CMD_CE 0x00000004 475 #define PCIECAP_AER_RERR_STA 0x30 476 #define PCIECAP_AER_RERR_STA_CORR 0x00000001 477 #define PCIECAP_AER_RERR_STA_MCORR 0x00000002 478 #define PCIECAP_AER_RERR_STA_FNF 0x00000004 479 #define PCIECAP_AER_RERR_STA_MFNF 0x00000008 480 #define PCIECAP_AER_RERR_F_UFATAL 0x00000010 481 #define PCIECAP_AER_RERR_NFE 0x00000020 482 #define PCIECAP_AER_RERR_FE 0x00000040 483 #define PCIECAP_AER_RERR_MSINO 0xf8000000 484 #define PCIECAP_AER_SRCID 0x34 485 #define PCIECAP_AER_SRCID_CORR 0x0000ffff 486 #define PCIECAP_AER_SRCID_FNF 0xffff0000 487 #define PCIECAP_AER_TLP_PFX_LOG0 0x38 488 #define PCIECAP_AER_TLP_PFX_LOG1 0x3c 489 #define PCIECAP_AER_TLP_PFX_LOG2 0x40 490 #define PCIECAP_AER_TLP_PFX_LOG3 0x44 491 492 /* SRIOV capability */ 493 #define PCIECAP_ID_SRIOV 0x10 494 #define PCIECAP_SRIOV_CAP 0x04 495 #define PCIECAP_SRIOV_CAP_VFM 0x01 496 #define PCIECAP_SRIOV_CAP_INTR(x) ((x) >> 21) 497 #define PCIECAP_SRIOV_CTRL 0x08 498 #define PCIECAP_SRIOV_CTRL_VFE 0x01 499 #define PCIECAP_SRIOV_CTRL_VFM 0x02 500 #define PCIECAP_SRIOV_CTRL_INTR 0x04 501 #define PCIECAP_SRIOV_CTRL_MSE 0x08 502 #define PCIECAP_SRIOV_CTRL_ARI 0x10 503 #define PCIECAP_SRIOV_STATUS 0x0a 504 #define PCIECAP_SRIOV_STATUS_VFM 0x01 505 #define PCIECAP_SRIOV_INITIAL_VF 0x0c 506 #define PCIECAP_SRIOV_TOTAL_VF 0x0e 507 #define PCIECAP_SRIOV_NUM_VF 0x10 508 #define PCIECAP_SRIOV_FUNC_LINK 0x12 509 #define PCIECAP_SRIOV_VF_OFFSET 0x14 510 #define PCIECAP_SRIOV_VF_STRIDE 0x16 511 #define PCIECAP_SRIOV_VF_DID 0x1a 512 #define PCIECAP_SRIOV_SUP_PGSIZE 0x1c 513 #define PCIECAP_SRIOV_SYS_PGSIZE 0x20 514 #define PCIECAP_SRIOV_BAR 0x24 515 #define PCIECAP_SRIOV_NUM_BARS 6 516 #define PCIECAP_SRIOV_VFM 0x3c 517 #define PCIECAP_SRIOV_VFM_BIR(x) ((x) & 7) 518 #define PCIECAP_SRIOV_VFM_OFFSET(x) ((x) & ~7) 519 #define PCIECAP_SRIOV_VFM_UA 0x0 520 #define PCIECAP_SRIOV_VFM_MI 0x1 521 #define PCIECAP_SRIOV_VFM_MO 0x2 522 #define PCIECAP_SRIOV_VFM_AV 0x3 523 524 /* Vendor specific extend capability */ 525 #define PCIECAP_ID_VNDR 0x0b 526 #define PCIECAP_VNDR_HDR 0x04 527 #define PCIECAP_VNDR_HDR_ID_MASK 0x0000ffff 528 #define PCIECAP_VNDR_HDR_ID_LSH 0 529 #define PCIECAP_VNDR_HDR_REV_MASK 0x000f0000 530 #define PCIECAP_VNDR_HDR_REV_LSH 16 531 #define PCIECAP_VNDR_HDR_LEN_MASK 0xfff00000 532 #define PCIECAP_VNDR_HDR_LEN_LSH 20 533 534 #endif /* __PCI_CFG_H */ 535