1 /* Copyright 2013-2016 IBM Corp.
2 *
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at
6 *
7 * http://www.apache.org/licenses/LICENSE-2.0
8 *
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
12 * implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17 /*
18 */
19 #ifndef __PHB4_H
20 #define __PHB4_H
21
22 #include <interrupts.h>
23
24 /*
25 * Memory map
26 *
27 * In addition to the 4K MMIO registers window, the PBCQ will
28 * forward down one or two large MMIO regions for use by the
29 * PHB.
30 *
31 * We try to use the largest MMIO window for the M64 space and
32 * the smallest for the M32 space, but we require at least 2G
33 * of M32, otherwise we carve it out of M64.
34 */
35
36 #define M32_PCI_START 0x080000000 /* Offset of the actual M32 window in PCI */
37 #define M32_PCI_SIZE 0x80000000ul /* Size for M32 */
38
39 #if 0
40 /*
41 * Interrupt map.
42 *
43 * Each PHB supports 2K interrupt sources, which is shared by
44 * LSI and MSI. With default configuration, MSI would use range
45 * [0, 0x7f7] and LSI would use [0x7f8, 0x7ff]. The interrupt
46 * source should be combined with IRSN to form final hardware
47 * IRQ.
48 */
49 #define PHB4_MSI_IRQ_MIN 0x000
50 #define PHB4_MSI_IRQ_COUNT 0x7F8
51 #define PHB4_MSI_IRQ_MAX (PHB4_MSI_IRQ_MIN+PHB4_MSI_IRQ_COUNT-1)
52 #define PHB4_LSI_IRQ_MIN (PHB4_MSI_IRQ_COUNT)
53 #define PHB4_LSI_IRQ_COUNT 8
54 #define PHB4_LSI_IRQ_MAX (PHB4_LSI_IRQ_MIN+PHB4_LSI_IRQ_COUNT-1)
55
56 #define PHB4_MSI_IRQ_BASE(chip, phb) (p8_chip_irq_phb_base(chip, phb) | \
57 PHB4_MSI_IRQ_MIN)
58 #define PHB4_LSI_IRQ_BASE(chip, phb) (p8_chip_irq_phb_base(chip, phb) | \
59 PHB4_LSI_IRQ_MIN)
60 #define PHB4_IRQ_NUM(irq) (irq & 0x7FF)
61
62 #endif
63
64 /*
65 * LSI interrupts
66 *
67 * The LSI interrupt block supports 8 interrupts. 4 of them are the
68 * standard PCIe INTA..INTB. The rest is for additional functions
69 * of the PHB
70 */
71 #define PHB4_LSI_PCIE_INTA 0
72 #define PHB4_LSI_PCIE_INTB 1
73 #define PHB4_LSI_PCIE_INTC 2
74 #define PHB4_LSI_PCIE_INTD 3
75 #define PHB4_LSI_PCIE_INF 6
76 #define PHB4_LSI_PCIE_ER 7
77
78 /*
79 * In-memory tables
80 *
81 * PHB4 requires a bunch of tables to be in memory instead of
82 * arrays inside the chip (unlike previous versions of the
83 * design).
84 *
85 * Some of them (IVT, etc...) will be provided by the OS via an
86 * OPAL call, not only not all of them, we also need to make sure
87 * some like PELT-V exist before we do our internal slot probing
88 * or bad thing would happen on error (the whole PHB would go into
89 * Fatal error state).
90 *
91 * So we maintain a set of tables internally for those mandatory
92 * ones within our core memory. They are fairly small. They can
93 * still be replaced by OS provided ones via OPAL APIs (and reset
94 * to the internal ones) so the OS can provide node local allocation
95 * for better performances.
96 *
97 * All those tables have to be naturally aligned
98 */
99
100 /* RTT Table : 128KB - Maps RID to PE#
101 *
102 * Entries are 2 bytes indexed by PCIe RID
103 */
104 #define RTT_TABLE_ENTRIES 0x10000
105 #define RTT_TABLE_SIZE 0x20000
106 #define PELTV_TABLE_SIZE_MAX 0x20000
107
108 #define PHB4_RESERVED_PE_NUM(p) ((p)->num_pes - 1)
109
110 /*
111 * PHB4 PCI slot state. When you're going to apply any
112 * changes here, please make sure the base state isn't
113 * conflicting with those defined in pci-slot.h
114 */
115 #define PHB4_SLOT_NORMAL PCI_SLOT_STATE_NORMAL
116 #define PHB4_SLOT_LINK PCI_SLOT_STATE_LINK
117 #define PHB4_SLOT_LINK_START (PHB4_SLOT_LINK + 1)
118 #define PHB4_SLOT_LINK_WAIT_ELECTRICAL (PHB4_SLOT_LINK + 2)
119 #define PHB4_SLOT_LINK_WAIT (PHB4_SLOT_LINK + 3)
120 #define PHB4_SLOT_LINK_STABLE (PHB4_SLOT_LINK + 4)
121 #define PHB4_SLOT_HRESET PCI_SLOT_STATE_HRESET
122 #define PHB4_SLOT_HRESET_START (PHB4_SLOT_HRESET + 1)
123 #define PHB4_SLOT_HRESET_DELAY (PHB4_SLOT_HRESET + 2)
124 #define PHB4_SLOT_HRESET_DELAY2 (PHB4_SLOT_HRESET + 3)
125 #define PHB4_SLOT_FRESET PCI_SLOT_STATE_FRESET
126 #define PHB4_SLOT_FRESET_START (PHB4_SLOT_FRESET + 1)
127 #define PHB4_SLOT_FRESET_ASSERT_DELAY (PHB4_SLOT_FRESET + 2)
128 #define PHB4_SLOT_CRESET PCI_SLOT_STATE_CRESET
129 #define PHB4_SLOT_CRESET_START (PHB4_SLOT_CRESET + 1)
130 #define PHB4_SLOT_CRESET_WAIT_CQ (PHB4_SLOT_CRESET + 2)
131 #define PHB4_SLOT_CRESET_REINIT (PHB4_SLOT_CRESET + 3)
132 #define PHB4_SLOT_CRESET_FRESET (PHB4_SLOT_CRESET + 4)
133
134 /*
135 * PHB4 error descriptor. Errors from all components (PBCQ, PHB)
136 * will be cached to PHB4 instance. However, PBCQ errors would
137 * have higher priority than those from PHB
138 */
139 #define PHB4_ERR_SRC_NONE 0
140 #define PHB4_ERR_SRC_PBCQ 1
141 #define PHB4_ERR_SRC_PHB 2
142
143 #define PHB4_ERR_CLASS_NONE 0
144 #define PHB4_ERR_CLASS_DEAD 1
145 #define PHB4_ERR_CLASS_FENCED 2
146 #define PHB4_ERR_CLASS_ER 3
147 #define PHB4_ERR_CLASS_INF 4
148 #define PHB4_ERR_CLASS_LAST 5
149
150 struct phb4_err {
151 uint32_t err_src;
152 uint32_t err_class;
153 uint32_t err_bit;
154 };
155
156 #define PHB4_LINK_LINK_RETRIES 4
157 /* Link timeouts, increments of 10ms */
158 #define PHB4_LINK_ELECTRICAL_RETRIES 100
159 #define PHB4_LINK_WAIT_RETRIES 200
160
161 #define PHB4_RX_ERR_MAX 8
162
163 /* PHB4 flags */
164 #define PHB4_AIB_FENCED 0x00000001
165 #define PHB4_CFG_USE_ASB 0x00000002
166 #define PHB4_CFG_BLOCKED 0x00000004
167 #define PHB4_CAPP_RECOVERY 0x00000008
168 #define PHB4_CAPP_DISABLE 0x00000010
169
170 struct phb4 {
171 unsigned int index; /* 0..5 index inside p9 */
172 unsigned int flags;
173 unsigned int chip_id; /* Chip ID (== GCID on p9) */
174 unsigned int pec;
175 bool broken;
176 unsigned int rev; /* 00MMmmmm */
177 #define PHB4_REV_NIMBUS_DD10 0xa40001
178 #define PHB4_REV_NIMBUS_DD20 0xa40002
179 void *regs;
180 void *int_mmio;
181 uint64_t pe_xscom; /* XSCOM bases */
182 uint64_t pe_stk_xscom;
183 uint64_t pci_xscom;
184 uint64_t pci_stk_xscom;
185 uint64_t etu_xscom;
186 struct lock lock;
187 uint64_t mm0_base; /* Full MM window to PHB */
188 uint64_t mm0_size; /* '' '' '' */
189 uint64_t mm1_base; /* Full MM window to PHB */
190 uint64_t mm1_size; /* '' '' '' */
191 uint32_t base_msi;
192 uint32_t base_lsi;
193 uint64_t irq_port;
194 uint32_t num_pes;
195 uint32_t max_num_pes;
196 uint32_t num_irqs;
197 uint64_t creset_start_time;
198
199 /* SkiBoot owned in-memory tables */
200 uint16_t *tbl_rtt;
201 uint8_t *tbl_peltv;
202 uint64_t tbl_peltv_size;
203 uint64_t tbl_pest;
204 uint64_t tbl_pest_size;
205
206 bool skip_perst; /* Skip first perst */
207 bool has_link;
208 int64_t ecap; /* cached PCI-E cap offset */
209 int64_t aercap; /* cached AER ecap offset */
210 const __be64 *lane_eq;
211 bool lane_eq_en;
212 unsigned int max_link_speed;
213 unsigned int dt_max_link_speed;
214
215 uint64_t mrt_size;
216 uint64_t mbt_size;
217 uint64_t tvt_size;
218
219 /* FIXME: dynamically allocate only what's needed below */
220 uint64_t tve_cache[1024];
221 uint64_t mbt_cache[32][2];
222 uint64_t mdt_cache[512]; /* max num of PEs */
223 uint64_t mist_cache[4096/4];/* max num of MSIs */
224 uint64_t pfir_cache; /* Used by complete reset */
225 uint64_t nfir_cache; /* Used by complete reset */
226 bool err_pending;
227 struct phb4_err err;
228
229 /* Cache some RC registers that need to be emulated */
230 uint32_t rc_cache[4];
231
232 /* Current NPU2 relaxed ordering state */
233 bool ro_state;
234
235 /* Any capp instance attached to the PHB4 */
236 struct capp *capp;
237
238 struct phb phb;
239 };
240
phb_to_phb4(struct phb * phb)241 static inline struct phb4 *phb_to_phb4(struct phb *phb)
242 {
243 return container_of(phb, struct phb4, phb);
244 }
245
phb4_err_pending(struct phb4 * p)246 static inline bool phb4_err_pending(struct phb4 *p)
247 {
248 return p->err_pending;
249 }
250
phb4_set_err_pending(struct phb4 * p,bool pending)251 static inline void phb4_set_err_pending(struct phb4 *p, bool pending)
252 {
253 if (!pending) {
254 p->err.err_src = PHB4_ERR_SRC_NONE;
255 p->err.err_class = PHB4_ERR_CLASS_NONE;
256 p->err.err_bit = -1;
257 }
258
259 p->err_pending = pending;
260 }
261
262 #define PHB4_PER_CHIP 6 /* Max 6 PHBs per chip on p9 */
263
phb4_get_opal_id(unsigned int chip_id,unsigned int index)264 static inline int phb4_get_opal_id(unsigned int chip_id, unsigned int index)
265 {
266 return chip_id * PHB4_PER_CHIP + index;
267 }
268
269 #endif /* __PHB4_H */
270