1 /*
2 * (C) Copyright 2000-2009
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 *
25 * Based on the MPC83xx code.
26 */
27
28 #include <common.h>
29 #include <command.h>
30 #include <asm/io.h>
31 #include <asm/processor.h>
32
33 DECLARE_GLOBAL_DATA_PTR;
34
35 static int spmf_mult[] = {
36 68, 1, 12, 16,
37 20, 24, 28, 32,
38 36, 40, 44, 48,
39 52, 56, 60, 64
40 };
41
42 static int cpmf_mult[][2] = {
43 {0, 1}, {0, 1}, /* 0 and 1 are not valid */
44 {1, 1}, {3, 2},
45 {2, 1}, {5, 2},
46 {3, 1}, {7, 2},
47 {0, 1}, {0, 1}, /* and all above 7 are not valid too */
48 {0, 1}, {0, 1},
49 {0, 1}, {0, 1},
50 {0, 1}, {0, 1}
51 };
52
53 static int sys_dividors[][2] = {
54 {2, 1}, {5, 2}, {3, 1}, {7, 2}, {4, 1},
55 {9, 2}, {5, 1}, {7, 1}, {6, 1}, {8, 1},
56 {9, 1}, {11, 1}, {10, 1}, {12, 1}, {13, 1},
57 {15, 1}, {14, 1}, {16, 1}, {17, 1}, {19, 1},
58 {18, 1}, {20, 1}, {21, 1}, {23, 1}, {22, 1},
59 {24, 1}, {25, 1}, {27, 1}, {26, 1}, {28, 1},
60 {29, 1}, {31, 1}, {30, 1}, {32, 1}, {33, 1}
61 };
62
get_clocks(void)63 int get_clocks (void)
64 {
65 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
66 u8 spmf;
67 u8 cpmf;
68 u8 sys_div;
69 u8 ips_div;
70 u8 pci_div;
71 u32 ref_clk = CONFIG_SYS_MPC512X_CLKIN;
72 u32 spll;
73 u32 sys_clk;
74 u32 core_clk;
75 u32 csb_clk;
76 u32 ips_clk;
77 u32 pci_clk;
78 u32 reg;
79
80 reg = in_be32(&im->sysconf.immrbar);
81 if ((reg & IMMRBAR_BASE_ADDR) != (u32) im)
82 return -1;
83
84 reg = in_be32(&im->clk.spmr);
85 spmf = (reg & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
86 spll = ref_clk * spmf_mult[spmf];
87
88 reg = in_be32(&im->clk.scfr[1]);
89 sys_div = (reg & SCFR2_SYS_DIV) >> SCFR2_SYS_DIV_SHIFT;
90 sys_clk = (spll * sys_dividors[sys_div][1]) / sys_dividors[sys_div][0];
91
92 csb_clk = sys_clk / 2;
93
94 reg = in_be32(&im->clk.spmr);
95 cpmf = (reg & SPMR_CPMF) >> SPMR_CPMF_SHIFT;
96 core_clk = (csb_clk * cpmf_mult[cpmf][0]) / cpmf_mult[cpmf][1];
97
98 reg = in_be32(&im->clk.scfr[0]);
99 ips_div = (reg & SCFR1_IPS_DIV_MASK) >> SCFR1_IPS_DIV_SHIFT;
100 if (ips_div != 0) {
101 ips_clk = csb_clk / ips_div;
102 } else {
103 /* in case we cannot get a sane IPS divisor, fail gracefully */
104 ips_clk = 0;
105 }
106
107 reg = in_be32(&im->clk.scfr[0]);
108 pci_div = (reg & SCFR1_PCI_DIV_MASK) >> SCFR1_PCI_DIV_SHIFT;
109 if (pci_div != 0) {
110 pci_clk = csb_clk / pci_div;
111 } else {
112 /* in case we cannot get a sane IPS divisor, fail gracefully */
113 pci_clk = 333333;
114 }
115
116 gd->ips_clk = ips_clk;
117 gd->pci_clk = pci_clk;
118 gd->csb_clk = csb_clk;
119 gd->cpu_clk = core_clk;
120 gd->bus_clk = csb_clk;
121 return 0;
122
123 }
124
125 /********************************************
126 * get_bus_freq
127 * return system bus freq in Hz
128 *********************************************/
get_bus_freq(ulong dummy)129 ulong get_bus_freq (ulong dummy)
130 {
131 return gd->csb_clk;
132 }
133
do_clocks(cmd_tbl_t * cmdtp,int flag,int argc,char * argv[])134 int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
135 {
136 char buf[32];
137
138 printf("Clock configuration:\n");
139 printf(" CPU: %-4s MHz\n", strmhz(buf, gd->cpu_clk));
140 printf(" Coherent System Bus: %-4s MHz\n", strmhz(buf, gd->csb_clk));
141 printf(" IPS Bus: %-4s MHz\n", strmhz(buf, gd->ips_clk));
142 printf(" PCI: %-4s MHz\n", strmhz(buf, gd->pci_clk));
143 printf(" DDR: %-4s MHz\n", strmhz(buf, 2*gd->csb_clk));
144 return 0;
145 }
146
147 U_BOOT_CMD(clocks, 1, 0, do_clocks,
148 "print clock configuration",
149 " clocks"
150 );
151
prt_mpc512x_clks(void)152 int prt_mpc512x_clks (void)
153 {
154 do_clocks (NULL, 0, 0, NULL);
155 return (0);
156 }
157