1 /*
2 * Copyright 2008-2010 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
7 * any later version.
8 */
9
10 /*
11 * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
12 * Based on code from spd_sdram.c
13 * Author: James Yang [at freescale.com]
14 */
15
16 #include <common.h>
17 #include <asm/fsl_ddr_sdram.h>
18
19 #include "ddr.h"
20
21 extern unsigned int picos_to_mclk(unsigned int picos);
22 /*
23 * Determine Rtt value.
24 *
25 * This should likely be either board or controller specific.
26 *
27 * Rtt(nominal) - DDR2:
28 * 0 = Rtt disabled
29 * 1 = 75 ohm
30 * 2 = 150 ohm
31 * 3 = 50 ohm
32 * Rtt(nominal) - DDR3:
33 * 0 = Rtt disabled
34 * 1 = 60 ohm
35 * 2 = 120 ohm
36 * 3 = 40 ohm
37 * 4 = 20 ohm
38 * 5 = 30 ohm
39 *
40 * FIXME: Apparently 8641 needs a value of 2
41 * FIXME: Old code seys if 667 MHz or higher, use 3 on 8572
42 *
43 * FIXME: There was some effort down this line earlier:
44 *
45 * unsigned int i;
46 * for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL/2; i++) {
47 * if (popts->dimmslot[i].num_valid_cs
48 * && (popts->cs_local_opts[2*i].odt_rd_cfg
49 * || popts->cs_local_opts[2*i].odt_wr_cfg)) {
50 * rtt = 2;
51 * break;
52 * }
53 * }
54 */
fsl_ddr_get_rtt(void)55 static inline int fsl_ddr_get_rtt(void)
56 {
57 int rtt;
58
59 #if defined(CONFIG_FSL_DDR1)
60 rtt = 0;
61 #elif defined(CONFIG_FSL_DDR2)
62 rtt = 3;
63 #else
64 rtt = 0;
65 #endif
66
67 return rtt;
68 }
69
70 /*
71 * compute the CAS write latency according to DDR3 spec
72 * CWL = 5 if tCK >= 2.5ns
73 * 6 if 2.5ns > tCK >= 1.875ns
74 * 7 if 1.875ns > tCK >= 1.5ns
75 * 8 if 1.5ns > tCK >= 1.25ns
76 */
compute_cas_write_latency(void)77 static inline unsigned int compute_cas_write_latency(void)
78 {
79 unsigned int cwl;
80 const unsigned int mclk_ps = get_memory_clk_period_ps();
81
82 if (mclk_ps >= 2500)
83 cwl = 5;
84 else if (mclk_ps >= 1875)
85 cwl = 6;
86 else if (mclk_ps >= 1500)
87 cwl = 7;
88 else if (mclk_ps >= 1250)
89 cwl = 8;
90 else
91 cwl = 8;
92 return cwl;
93 }
94
95 /* Chip Select Configuration (CSn_CONFIG) */
set_csn_config(int i,fsl_ddr_cfg_regs_t * ddr,const memctl_options_t * popts,const dimm_params_t * dimm_params)96 static void set_csn_config(int i, fsl_ddr_cfg_regs_t *ddr,
97 const memctl_options_t *popts,
98 const dimm_params_t *dimm_params)
99 {
100 unsigned int cs_n_en = 0; /* Chip Select enable */
101 unsigned int intlv_en = 0; /* Memory controller interleave enable */
102 unsigned int intlv_ctl = 0; /* Interleaving control */
103 unsigned int ap_n_en = 0; /* Chip select n auto-precharge enable */
104 unsigned int odt_rd_cfg = 0; /* ODT for reads configuration */
105 unsigned int odt_wr_cfg = 0; /* ODT for writes configuration */
106 unsigned int ba_bits_cs_n = 0; /* Num of bank bits for SDRAM on CSn */
107 unsigned int row_bits_cs_n = 0; /* Num of row bits for SDRAM on CSn */
108 unsigned int col_bits_cs_n = 0; /* Num of ocl bits for SDRAM on CSn */
109
110 /* Compute CS_CONFIG only for existing ranks of each DIMM. */
111 if ((((i&1) == 0)
112 && (dimm_params[i/2].n_ranks == 1))
113 || (dimm_params[i/2].n_ranks == 2)) {
114 unsigned int n_banks_per_sdram_device;
115 cs_n_en = 1;
116 if (i == 0) {
117 /* These fields only available in CS0_CONFIG */
118 intlv_en = popts->memctl_interleaving;
119 intlv_ctl = popts->memctl_interleaving_mode;
120 }
121 ap_n_en = popts->cs_local_opts[i].auto_precharge;
122 odt_rd_cfg = popts->cs_local_opts[i].odt_rd_cfg;
123 odt_wr_cfg = popts->cs_local_opts[i].odt_wr_cfg;
124 n_banks_per_sdram_device
125 = dimm_params[i/2].n_banks_per_sdram_device;
126 ba_bits_cs_n = __ilog2(n_banks_per_sdram_device) - 2;
127 row_bits_cs_n = dimm_params[i/2].n_row_addr - 12;
128 col_bits_cs_n = dimm_params[i/2].n_col_addr - 8;
129 }
130
131 ddr->cs[i].config = (0
132 | ((cs_n_en & 0x1) << 31)
133 | ((intlv_en & 0x3) << 29)
134 | ((intlv_ctl & 0xf) << 24)
135 | ((ap_n_en & 0x1) << 23)
136
137 /* XXX: some implementation only have 1 bit starting at left */
138 | ((odt_rd_cfg & 0x7) << 20)
139
140 /* XXX: Some implementation only have 1 bit starting at left */
141 | ((odt_wr_cfg & 0x7) << 16)
142
143 | ((ba_bits_cs_n & 0x3) << 14)
144 | ((row_bits_cs_n & 0x7) << 8)
145 | ((col_bits_cs_n & 0x7) << 0)
146 );
147 debug("FSLDDR: cs[%d]_config = 0x%08x\n", i,ddr->cs[i].config);
148 }
149
150 /* Chip Select Configuration 2 (CSn_CONFIG_2) */
151 /* FIXME: 8572 */
set_csn_config_2(int i,fsl_ddr_cfg_regs_t * ddr)152 static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr)
153 {
154 unsigned int pasr_cfg = 0; /* Partial array self refresh config */
155
156 ddr->cs[i].config_2 = ((pasr_cfg & 7) << 24);
157 debug("FSLDDR: cs[%d]_config_2 = 0x%08x\n", i, ddr->cs[i].config_2);
158 }
159
160 /* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */
161
162 #if !defined(CONFIG_FSL_DDR1)
163 /*
164 * DDR SDRAM Timing Configuration 0 (TIMING_CFG_0)
165 *
166 * Avoid writing for DDR I. The new PQ38 DDR controller
167 * dreams up non-zero default values to be backwards compatible.
168 */
set_timing_cfg_0(fsl_ddr_cfg_regs_t * ddr)169 static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr)
170 {
171 unsigned char trwt_mclk = 0; /* Read-to-write turnaround */
172 unsigned char twrt_mclk = 0; /* Write-to-read turnaround */
173 /* 7.5 ns on -3E; 0 means WL - CL + BL/2 + 1 */
174 unsigned char trrt_mclk = 0; /* Read-to-read turnaround */
175 unsigned char twwt_mclk = 0; /* Write-to-write turnaround */
176
177 /* Active powerdown exit timing (tXARD and tXARDS). */
178 unsigned char act_pd_exit_mclk;
179 /* Precharge powerdown exit timing (tXP). */
180 unsigned char pre_pd_exit_mclk;
181 /* Precharge powerdown exit timing (tAXPD). */
182 unsigned char taxpd_mclk;
183 /* Mode register set cycle time (tMRD). */
184 unsigned char tmrd_mclk;
185
186 #if defined(CONFIG_FSL_DDR3)
187 /*
188 * (tXARD and tXARDS). Empirical?
189 * The DDR3 spec has not tXARD,
190 * we use the tXP instead of it.
191 * tXP=max(3nCK, 7.5ns) for DDR3.
192 * spec has not the tAXPD, we use
193 * tAXPD=8, need design to confirm.
194 */
195 int tXP = max((get_memory_clk_period_ps() * 3), 7500); /* unit=ps */
196 act_pd_exit_mclk = picos_to_mclk(tXP);
197 /* Mode register MR0[A12] is '1' - fast exit */
198 pre_pd_exit_mclk = act_pd_exit_mclk;
199 taxpd_mclk = 8;
200 tmrd_mclk = 4;
201 /* set the turnaround time */
202 trwt_mclk = 1;
203 #else /* CONFIG_FSL_DDR2 */
204 /*
205 * (tXARD and tXARDS). Empirical?
206 * tXARD = 2 for DDR2
207 * tXP=2
208 * tAXPD=8
209 */
210 act_pd_exit_mclk = 2;
211 pre_pd_exit_mclk = 2;
212 taxpd_mclk = 8;
213 tmrd_mclk = 2;
214 #endif
215
216 ddr->timing_cfg_0 = (0
217 | ((trwt_mclk & 0x3) << 30) /* RWT */
218 | ((twrt_mclk & 0x3) << 28) /* WRT */
219 | ((trrt_mclk & 0x3) << 26) /* RRT */
220 | ((twwt_mclk & 0x3) << 24) /* WWT */
221 | ((act_pd_exit_mclk & 0x7) << 20) /* ACT_PD_EXIT */
222 | ((pre_pd_exit_mclk & 0xF) << 16) /* PRE_PD_EXIT */
223 | ((taxpd_mclk & 0xf) << 8) /* ODT_PD_EXIT */
224 | ((tmrd_mclk & 0xf) << 0) /* MRS_CYC */
225 );
226 debug("FSLDDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
227 }
228 #endif /* defined(CONFIG_FSL_DDR2) */
229
230 /* DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) */
set_timing_cfg_3(fsl_ddr_cfg_regs_t * ddr,const common_timing_params_t * common_dimm,unsigned int cas_latency)231 static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr,
232 const common_timing_params_t *common_dimm,
233 unsigned int cas_latency)
234 {
235 /* Extended Activate to precharge interval (tRAS) */
236 unsigned int ext_acttopre = 0;
237 unsigned int ext_refrec; /* Extended refresh recovery time (tRFC) */
238 unsigned int ext_caslat = 0; /* Extended MCAS latency from READ cmd */
239 unsigned int cntl_adj = 0; /* Control Adjust */
240
241 /* If the tRAS > 19 MCLK, we use the ext mode */
242 if (picos_to_mclk(common_dimm->tRAS_ps) > 0x13)
243 ext_acttopre = 1;
244
245 ext_refrec = (picos_to_mclk(common_dimm->tRFC_ps) - 8) >> 4;
246
247 /* If the CAS latency more than 8, use the ext mode */
248 if (cas_latency > 8)
249 ext_caslat = 1;
250
251 ddr->timing_cfg_3 = (0
252 | ((ext_acttopre & 0x1) << 24)
253 | ((ext_refrec & 0xF) << 16)
254 | ((ext_caslat & 0x1) << 12)
255 | ((cntl_adj & 0x7) << 0)
256 );
257 debug("FSLDDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3);
258 }
259
260 /* DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) */
set_timing_cfg_1(fsl_ddr_cfg_regs_t * ddr,const memctl_options_t * popts,const common_timing_params_t * common_dimm,unsigned int cas_latency)261 static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr,
262 const memctl_options_t *popts,
263 const common_timing_params_t *common_dimm,
264 unsigned int cas_latency)
265 {
266 /* Precharge-to-activate interval (tRP) */
267 unsigned char pretoact_mclk;
268 /* Activate to precharge interval (tRAS) */
269 unsigned char acttopre_mclk;
270 /* Activate to read/write interval (tRCD) */
271 unsigned char acttorw_mclk;
272 /* CASLAT */
273 unsigned char caslat_ctrl;
274 /* Refresh recovery time (tRFC) ; trfc_low */
275 unsigned char refrec_ctrl;
276 /* Last data to precharge minimum interval (tWR) */
277 unsigned char wrrec_mclk;
278 /* Activate-to-activate interval (tRRD) */
279 unsigned char acttoact_mclk;
280 /* Last write data pair to read command issue interval (tWTR) */
281 unsigned char wrtord_mclk;
282
283 pretoact_mclk = picos_to_mclk(common_dimm->tRP_ps);
284 acttopre_mclk = picos_to_mclk(common_dimm->tRAS_ps);
285 acttorw_mclk = picos_to_mclk(common_dimm->tRCD_ps);
286
287 /*
288 * Translate CAS Latency to a DDR controller field value:
289 *
290 * CAS Lat DDR I DDR II Ctrl
291 * Clocks SPD Bit SPD Bit Value
292 * ------- ------- ------- -----
293 * 1.0 0 0001
294 * 1.5 1 0010
295 * 2.0 2 2 0011
296 * 2.5 3 0100
297 * 3.0 4 3 0101
298 * 3.5 5 0110
299 * 4.0 4 0111
300 * 4.5 1000
301 * 5.0 5 1001
302 */
303 #if defined(CONFIG_FSL_DDR1)
304 caslat_ctrl = (cas_latency + 1) & 0x07;
305 #elif defined(CONFIG_FSL_DDR2)
306 caslat_ctrl = 2 * cas_latency - 1;
307 #else
308 /*
309 * if the CAS latency more than 8 cycle,
310 * we need set extend bit for it at
311 * TIMING_CFG_3[EXT_CASLAT]
312 */
313 if (cas_latency > 8)
314 cas_latency -= 8;
315 caslat_ctrl = 2 * cas_latency - 1;
316 #endif
317
318 refrec_ctrl = picos_to_mclk(common_dimm->tRFC_ps) - 8;
319 wrrec_mclk = picos_to_mclk(common_dimm->tWR_ps);
320 if (popts->OTF_burst_chop_en)
321 wrrec_mclk += 2;
322
323 acttoact_mclk = picos_to_mclk(common_dimm->tRRD_ps);
324 /*
325 * JEDEC has min requirement for tRRD
326 */
327 #if defined(CONFIG_FSL_DDR3)
328 if (acttoact_mclk < 4)
329 acttoact_mclk = 4;
330 #endif
331 wrtord_mclk = picos_to_mclk(common_dimm->tWTR_ps);
332 /*
333 * JEDEC has some min requirements for tWTR
334 */
335 #if defined(CONFIG_FSL_DDR2)
336 if (wrtord_mclk < 2)
337 wrtord_mclk = 2;
338 #elif defined(CONFIG_FSL_DDR3)
339 if (wrtord_mclk < 4)
340 wrtord_mclk = 4;
341 #endif
342 if (popts->OTF_burst_chop_en)
343 wrtord_mclk += 2;
344
345 ddr->timing_cfg_1 = (0
346 | ((pretoact_mclk & 0x0F) << 28)
347 | ((acttopre_mclk & 0x0F) << 24)
348 | ((acttorw_mclk & 0xF) << 20)
349 | ((caslat_ctrl & 0xF) << 16)
350 | ((refrec_ctrl & 0xF) << 12)
351 | ((wrrec_mclk & 0x0F) << 8)
352 | ((acttoact_mclk & 0x07) << 4)
353 | ((wrtord_mclk & 0x07) << 0)
354 );
355 debug("FSLDDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1);
356 }
357
358 /* DDR SDRAM Timing Configuration 2 (TIMING_CFG_2) */
set_timing_cfg_2(fsl_ddr_cfg_regs_t * ddr,const memctl_options_t * popts,const common_timing_params_t * common_dimm,unsigned int cas_latency,unsigned int additive_latency)359 static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr,
360 const memctl_options_t *popts,
361 const common_timing_params_t *common_dimm,
362 unsigned int cas_latency,
363 unsigned int additive_latency)
364 {
365 /* Additive latency */
366 unsigned char add_lat_mclk;
367 /* CAS-to-preamble override */
368 unsigned short cpo;
369 /* Write latency */
370 unsigned char wr_lat;
371 /* Read to precharge (tRTP) */
372 unsigned char rd_to_pre;
373 /* Write command to write data strobe timing adjustment */
374 unsigned char wr_data_delay;
375 /* Minimum CKE pulse width (tCKE) */
376 unsigned char cke_pls;
377 /* Window for four activates (tFAW) */
378 unsigned short four_act;
379
380 /* FIXME add check that this must be less than acttorw_mclk */
381 add_lat_mclk = additive_latency;
382 cpo = popts->cpo_override;
383
384 #if defined(CONFIG_FSL_DDR1)
385 /*
386 * This is a lie. It should really be 1, but if it is
387 * set to 1, bits overlap into the old controller's
388 * otherwise unused ACSM field. If we leave it 0, then
389 * the HW will magically treat it as 1 for DDR 1. Oh Yea.
390 */
391 wr_lat = 0;
392 #elif defined(CONFIG_FSL_DDR2)
393 wr_lat = cas_latency - 1;
394 #else
395 wr_lat = compute_cas_write_latency();
396 #endif
397
398 rd_to_pre = picos_to_mclk(common_dimm->tRTP_ps);
399 /*
400 * JEDEC has some min requirements for tRTP
401 */
402 #if defined(CONFIG_FSL_DDR2)
403 if (rd_to_pre < 2)
404 rd_to_pre = 2;
405 #elif defined(CONFIG_FSL_DDR3)
406 if (rd_to_pre < 4)
407 rd_to_pre = 4;
408 #endif
409 if (additive_latency)
410 rd_to_pre += additive_latency;
411 if (popts->OTF_burst_chop_en)
412 rd_to_pre += 2; /* according to UM */
413
414 wr_data_delay = popts->write_data_delay;
415 cke_pls = picos_to_mclk(popts->tCKE_clock_pulse_width_ps);
416 four_act = picos_to_mclk(popts->tFAW_window_four_activates_ps);
417
418 ddr->timing_cfg_2 = (0
419 | ((add_lat_mclk & 0xf) << 28)
420 | ((cpo & 0x1f) << 23)
421 | ((wr_lat & 0xf) << 19)
422 | ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT)
423 | ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT)
424 | ((cke_pls & 0x7) << 6)
425 | ((four_act & 0x3f) << 0)
426 );
427 debug("FSLDDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2);
428 }
429
430 /* DDR SDRAM control configuration (DDR_SDRAM_CFG) */
set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t * ddr,const memctl_options_t * popts,const common_timing_params_t * common_dimm)431 static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
432 const memctl_options_t *popts,
433 const common_timing_params_t *common_dimm)
434 {
435 unsigned int mem_en; /* DDR SDRAM interface logic enable */
436 unsigned int sren; /* Self refresh enable (during sleep) */
437 unsigned int ecc_en; /* ECC enable. */
438 unsigned int rd_en; /* Registered DIMM enable */
439 unsigned int sdram_type; /* Type of SDRAM */
440 unsigned int dyn_pwr; /* Dynamic power management mode */
441 unsigned int dbw; /* DRAM dta bus width */
442 unsigned int eight_be = 0; /* 8-beat burst enable, DDR2 is zero */
443 unsigned int ncap = 0; /* Non-concurrent auto-precharge */
444 unsigned int threeT_en; /* Enable 3T timing */
445 unsigned int twoT_en; /* Enable 2T timing */
446 unsigned int ba_intlv_ctl; /* Bank (CS) interleaving control */
447 unsigned int x32_en = 0; /* x32 enable */
448 unsigned int pchb8 = 0; /* precharge bit 8 enable */
449 unsigned int hse; /* Global half strength override */
450 unsigned int mem_halt = 0; /* memory controller halt */
451 unsigned int bi = 0; /* Bypass initialization */
452
453 mem_en = 1;
454 sren = popts->self_refresh_in_sleep;
455 if (common_dimm->all_DIMMs_ECC_capable) {
456 /* Allow setting of ECC only if all DIMMs are ECC. */
457 ecc_en = popts->ECC_mode;
458 } else {
459 ecc_en = 0;
460 }
461
462 rd_en = (common_dimm->all_DIMMs_registered
463 && !common_dimm->all_DIMMs_unbuffered);
464
465 sdram_type = CONFIG_FSL_SDRAM_TYPE;
466
467 dyn_pwr = popts->dynamic_power;
468 dbw = popts->data_bus_width;
469 /* 8-beat burst enable DDR-III case
470 * we must clear it when use the on-the-fly mode,
471 * must set it when use the 32-bits bus mode.
472 */
473 if (sdram_type == SDRAM_TYPE_DDR3) {
474 if (popts->burst_length == DDR_BL8)
475 eight_be = 1;
476 if (popts->burst_length == DDR_OTF)
477 eight_be = 0;
478 if (dbw == 0x1)
479 eight_be = 1;
480 }
481
482 threeT_en = popts->threeT_en;
483 twoT_en = popts->twoT_en;
484 ba_intlv_ctl = popts->ba_intlv_ctl;
485 hse = popts->half_strength_driver_enable;
486
487 ddr->ddr_sdram_cfg = (0
488 | ((mem_en & 0x1) << 31)
489 | ((sren & 0x1) << 30)
490 | ((ecc_en & 0x1) << 29)
491 | ((rd_en & 0x1) << 28)
492 | ((sdram_type & 0x7) << 24)
493 | ((dyn_pwr & 0x1) << 21)
494 | ((dbw & 0x3) << 19)
495 | ((eight_be & 0x1) << 18)
496 | ((ncap & 0x1) << 17)
497 | ((threeT_en & 0x1) << 16)
498 | ((twoT_en & 0x1) << 15)
499 | ((ba_intlv_ctl & 0x7F) << 8)
500 | ((x32_en & 0x1) << 5)
501 | ((pchb8 & 0x1) << 4)
502 | ((hse & 0x1) << 3)
503 | ((mem_halt & 0x1) << 1)
504 | ((bi & 0x1) << 0)
505 );
506 debug("FSLDDR: ddr_sdram_cfg = 0x%08x\n", ddr->ddr_sdram_cfg);
507 }
508
509 /* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */
set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t * ddr,const memctl_options_t * popts)510 static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
511 const memctl_options_t *popts)
512 {
513 unsigned int frc_sr = 0; /* Force self refresh */
514 unsigned int sr_ie = 0; /* Self-refresh interrupt enable */
515 unsigned int dll_rst_dis; /* DLL reset disable */
516 unsigned int dqs_cfg; /* DQS configuration */
517 unsigned int odt_cfg; /* ODT configuration */
518 unsigned int num_pr; /* Number of posted refreshes */
519 unsigned int obc_cfg; /* On-The-Fly Burst Chop Cfg */
520 unsigned int ap_en; /* Address Parity Enable */
521 unsigned int d_init; /* DRAM data initialization */
522 unsigned int rcw_en = 0; /* Register Control Word Enable */
523 unsigned int md_en = 0; /* Mirrored DIMM Enable */
524
525 dll_rst_dis = 1; /* Make this configurable */
526 dqs_cfg = popts->DQS_config;
527 if (popts->cs_local_opts[0].odt_rd_cfg
528 || popts->cs_local_opts[0].odt_wr_cfg) {
529 /* FIXME */
530 odt_cfg = 2;
531 } else {
532 odt_cfg = 0;
533 }
534
535 num_pr = 1; /* Make this configurable */
536
537 /*
538 * 8572 manual says
539 * {TIMING_CFG_1[PRETOACT]
540 * + [DDR_SDRAM_CFG_2[NUM_PR]
541 * * ({EXT_REFREC || REFREC} + 8 + 2)]}
542 * << DDR_SDRAM_INTERVAL[REFINT]
543 */
544 #if defined(CONFIG_FSL_DDR3)
545 obc_cfg = popts->OTF_burst_chop_en;
546 #else
547 obc_cfg = 0;
548 #endif
549
550 ap_en = 0; /* Make this configurable? */
551
552 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
553 /* Use the DDR controller to auto initialize memory. */
554 d_init = 1;
555 ddr->ddr_data_init = CONFIG_MEM_INIT_VALUE;
556 debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init);
557 #else
558 /* Memory will be initialized via DMA, or not at all. */
559 d_init = 0;
560 #endif
561
562 #if defined(CONFIG_FSL_DDR3)
563 md_en = popts->mirrored_dimm;
564 #endif
565 ddr->ddr_sdram_cfg_2 = (0
566 | ((frc_sr & 0x1) << 31)
567 | ((sr_ie & 0x1) << 30)
568 | ((dll_rst_dis & 0x1) << 29)
569 | ((dqs_cfg & 0x3) << 26)
570 | ((odt_cfg & 0x3) << 21)
571 | ((num_pr & 0xf) << 12)
572 | ((obc_cfg & 0x1) << 6)
573 | ((ap_en & 0x1) << 5)
574 | ((d_init & 0x1) << 4)
575 | ((rcw_en & 0x1) << 2)
576 | ((md_en & 0x1) << 0)
577 );
578 debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2);
579 }
580
581 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t * ddr,const memctl_options_t * popts)582 static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
583 const memctl_options_t *popts)
584 {
585 unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */
586 unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */
587
588 #if defined(CONFIG_FSL_DDR3)
589 unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */
590 unsigned int srt = 0; /* self-refresh temerature, normal range */
591 unsigned int asr = 0; /* auto self-refresh disable */
592 unsigned int cwl = compute_cas_write_latency() - 5;
593 unsigned int pasr = 0; /* partial array self refresh disable */
594
595 if (popts->rtt_override)
596 rtt_wr = popts->rtt_wr_override_value;
597
598 esdmode2 = (0
599 | ((rtt_wr & 0x3) << 9)
600 | ((srt & 0x1) << 7)
601 | ((asr & 0x1) << 6)
602 | ((cwl & 0x7) << 3)
603 | ((pasr & 0x7) << 0));
604 #endif
605 ddr->ddr_sdram_mode_2 = (0
606 | ((esdmode2 & 0xFFFF) << 16)
607 | ((esdmode3 & 0xFFFF) << 0)
608 );
609 debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
610 }
611
612 /* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */
set_ddr_sdram_interval(fsl_ddr_cfg_regs_t * ddr,const memctl_options_t * popts,const common_timing_params_t * common_dimm)613 static void set_ddr_sdram_interval(fsl_ddr_cfg_regs_t *ddr,
614 const memctl_options_t *popts,
615 const common_timing_params_t *common_dimm)
616 {
617 unsigned int refint; /* Refresh interval */
618 unsigned int bstopre; /* Precharge interval */
619
620 refint = picos_to_mclk(common_dimm->refresh_rate_ps);
621
622 bstopre = popts->bstopre;
623
624 /* refint field used 0x3FFF in earlier controllers */
625 ddr->ddr_sdram_interval = (0
626 | ((refint & 0xFFFF) << 16)
627 | ((bstopre & 0x3FFF) << 0)
628 );
629 debug("FSLDDR: ddr_sdram_interval = 0x%08x\n", ddr->ddr_sdram_interval);
630 }
631
632 #if defined(CONFIG_FSL_DDR3)
633 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
set_ddr_sdram_mode(fsl_ddr_cfg_regs_t * ddr,const memctl_options_t * popts,const common_timing_params_t * common_dimm,unsigned int cas_latency,unsigned int additive_latency)634 static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
635 const memctl_options_t *popts,
636 const common_timing_params_t *common_dimm,
637 unsigned int cas_latency,
638 unsigned int additive_latency)
639 {
640 unsigned short esdmode; /* Extended SDRAM mode */
641 unsigned short sdmode; /* SDRAM mode */
642
643 /* Mode Register - MR1 */
644 unsigned int qoff = 0; /* Output buffer enable 0=yes, 1=no */
645 unsigned int tdqs_en = 0; /* TDQS Enable: 0=no, 1=yes */
646 unsigned int rtt;
647 unsigned int wrlvl_en = 0; /* Write level enable: 0=no, 1=yes */
648 unsigned int al = 0; /* Posted CAS# additive latency (AL) */
649 unsigned int dic = 1; /* Output driver impedance, 34ohm */
650 unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal),
651 1=Disable (Test/Debug) */
652
653 /* Mode Register - MR0 */
654 unsigned int dll_on; /* DLL control for precharge PD, 0=off, 1=on */
655 unsigned int wr; /* Write Recovery */
656 unsigned int dll_rst; /* DLL Reset */
657 unsigned int mode; /* Normal=0 or Test=1 */
658 unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */
659 /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */
660 unsigned int bt;
661 unsigned int bl; /* BL: Burst Length */
662
663 unsigned int wr_mclk;
664
665 const unsigned int mclk_ps = get_memory_clk_period_ps();
666
667 rtt = fsl_ddr_get_rtt();
668 if (popts->rtt_override)
669 rtt = popts->rtt_override_value;
670
671 if (additive_latency == (cas_latency - 1))
672 al = 1;
673 if (additive_latency == (cas_latency - 2))
674 al = 2;
675
676 /*
677 * The esdmode value will also be used for writing
678 * MR1 during write leveling for DDR3, although the
679 * bits specifically related to the write leveling
680 * scheme will be handled automatically by the DDR
681 * controller. so we set the wrlvl_en = 0 here.
682 */
683 esdmode = (0
684 | ((qoff & 0x1) << 12)
685 | ((tdqs_en & 0x1) << 11)
686 | ((rtt & 0x4) << 7) /* rtt field is split */
687 | ((wrlvl_en & 0x1) << 7)
688 | ((rtt & 0x2) << 5) /* rtt field is split */
689 | ((dic & 0x2) << 4) /* DIC field is split */
690 | ((al & 0x3) << 3)
691 | ((rtt & 0x1) << 2) /* rtt field is split */
692 | ((dic & 0x1) << 1) /* DIC field is split */
693 | ((dll_en & 0x1) << 0)
694 );
695
696 /*
697 * DLL control for precharge PD
698 * 0=slow exit DLL off (tXPDLL)
699 * 1=fast exit DLL on (tXP)
700 */
701 dll_on = 1;
702 wr_mclk = (common_dimm->tWR_ps + mclk_ps - 1) / mclk_ps;
703 if (wr_mclk >= 12)
704 wr = 6;
705 else if (wr_mclk >= 9)
706 wr = 5;
707 else
708 wr = wr_mclk - 4;
709 dll_rst = 0; /* dll no reset */
710 mode = 0; /* normal mode */
711
712 /* look up table to get the cas latency bits */
713 if (cas_latency >= 5 && cas_latency <= 11) {
714 unsigned char cas_latency_table[7] = {
715 0x2, /* 5 clocks */
716 0x4, /* 6 clocks */
717 0x6, /* 7 clocks */
718 0x8, /* 8 clocks */
719 0xa, /* 9 clocks */
720 0xc, /* 10 clocks */
721 0xe /* 11 clocks */
722 };
723 caslat = cas_latency_table[cas_latency - 5];
724 }
725 bt = 0; /* Nibble sequential */
726
727 switch (popts->burst_length) {
728 case DDR_BL8:
729 bl = 0;
730 break;
731 case DDR_OTF:
732 bl = 1;
733 break;
734 case DDR_BC4:
735 bl = 2;
736 break;
737 default:
738 printf("Error: invalid burst length of %u specified. "
739 " Defaulting to on-the-fly BC4 or BL8 beats.\n",
740 popts->burst_length);
741 bl = 1;
742 break;
743 }
744
745 sdmode = (0
746 | ((dll_on & 0x1) << 12)
747 | ((wr & 0x7) << 9)
748 | ((dll_rst & 0x1) << 8)
749 | ((mode & 0x1) << 7)
750 | (((caslat >> 1) & 0x7) << 4)
751 | ((bt & 0x1) << 3)
752 | ((bl & 0x3) << 0)
753 );
754
755 ddr->ddr_sdram_mode = (0
756 | ((esdmode & 0xFFFF) << 16)
757 | ((sdmode & 0xFFFF) << 0)
758 );
759
760 debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
761 }
762
763 #else /* !CONFIG_FSL_DDR3 */
764
765 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
set_ddr_sdram_mode(fsl_ddr_cfg_regs_t * ddr,const memctl_options_t * popts,const common_timing_params_t * common_dimm,unsigned int cas_latency,unsigned int additive_latency)766 static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
767 const memctl_options_t *popts,
768 const common_timing_params_t *common_dimm,
769 unsigned int cas_latency,
770 unsigned int additive_latency)
771 {
772 unsigned short esdmode; /* Extended SDRAM mode */
773 unsigned short sdmode; /* SDRAM mode */
774
775 /*
776 * FIXME: This ought to be pre-calculated in a
777 * technology-specific routine,
778 * e.g. compute_DDR2_mode_register(), and then the
779 * sdmode and esdmode passed in as part of common_dimm.
780 */
781
782 /* Extended Mode Register */
783 unsigned int mrs = 0; /* Mode Register Set */
784 unsigned int outputs = 0; /* 0=Enabled, 1=Disabled */
785 unsigned int rdqs_en = 0; /* RDQS Enable: 0=no, 1=yes */
786 unsigned int dqs_en = 0; /* DQS# Enable: 0=enable, 1=disable */
787 unsigned int ocd = 0; /* 0x0=OCD not supported,
788 0x7=OCD default state */
789 unsigned int rtt;
790 unsigned int al; /* Posted CAS# additive latency (AL) */
791 unsigned int ods = 0; /* Output Drive Strength:
792 0 = Full strength (18ohm)
793 1 = Reduced strength (4ohm) */
794 unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal),
795 1=Disable (Test/Debug) */
796
797 /* Mode Register (MR) */
798 unsigned int mr; /* Mode Register Definition */
799 unsigned int pd; /* Power-Down Mode */
800 unsigned int wr; /* Write Recovery */
801 unsigned int dll_res; /* DLL Reset */
802 unsigned int mode; /* Normal=0 or Test=1 */
803 unsigned int caslat = 0;/* CAS# latency */
804 /* BT: Burst Type (0=Sequential, 1=Interleaved) */
805 unsigned int bt;
806 unsigned int bl; /* BL: Burst Length */
807
808 #if defined(CONFIG_FSL_DDR2)
809 const unsigned int mclk_ps = get_memory_clk_period_ps();
810 #endif
811
812 rtt = fsl_ddr_get_rtt();
813
814 al = additive_latency;
815
816 esdmode = (0
817 | ((mrs & 0x3) << 14)
818 | ((outputs & 0x1) << 12)
819 | ((rdqs_en & 0x1) << 11)
820 | ((dqs_en & 0x1) << 10)
821 | ((ocd & 0x7) << 7)
822 | ((rtt & 0x2) << 5) /* rtt field is split */
823 | ((al & 0x7) << 3)
824 | ((rtt & 0x1) << 2) /* rtt field is split */
825 | ((ods & 0x1) << 1)
826 | ((dll_en & 0x1) << 0)
827 );
828
829 mr = 0; /* FIXME: CHECKME */
830
831 /*
832 * 0 = Fast Exit (Normal)
833 * 1 = Slow Exit (Low Power)
834 */
835 pd = 0;
836
837 #if defined(CONFIG_FSL_DDR1)
838 wr = 0; /* Historical */
839 #elif defined(CONFIG_FSL_DDR2)
840 wr = (common_dimm->tWR_ps + mclk_ps - 1) / mclk_ps - 1;
841 #endif
842 dll_res = 0;
843 mode = 0;
844
845 #if defined(CONFIG_FSL_DDR1)
846 if (1 <= cas_latency && cas_latency <= 4) {
847 unsigned char mode_caslat_table[4] = {
848 0x5, /* 1.5 clocks */
849 0x2, /* 2.0 clocks */
850 0x6, /* 2.5 clocks */
851 0x3 /* 3.0 clocks */
852 };
853 caslat = mode_caslat_table[cas_latency - 1];
854 } else {
855 printf("Warning: unknown cas_latency %d\n", cas_latency);
856 }
857 #elif defined(CONFIG_FSL_DDR2)
858 caslat = cas_latency;
859 #endif
860 bt = 0;
861
862 switch (popts->burst_length) {
863 case DDR_BL4:
864 bl = 2;
865 break;
866 case DDR_BL8:
867 bl = 3;
868 break;
869 default:
870 printf("Error: invalid burst length of %u specified. "
871 " Defaulting to 4 beats.\n",
872 popts->burst_length);
873 bl = 2;
874 break;
875 }
876
877 sdmode = (0
878 | ((mr & 0x3) << 14)
879 | ((pd & 0x1) << 12)
880 | ((wr & 0x7) << 9)
881 | ((dll_res & 0x1) << 8)
882 | ((mode & 0x1) << 7)
883 | ((caslat & 0x7) << 4)
884 | ((bt & 0x1) << 3)
885 | ((bl & 0x7) << 0)
886 );
887
888 ddr->ddr_sdram_mode = (0
889 | ((esdmode & 0xFFFF) << 16)
890 | ((sdmode & 0xFFFF) << 0)
891 );
892 debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
893 }
894 #endif
895
896 /* DDR SDRAM Data Initialization (DDR_DATA_INIT) */
set_ddr_data_init(fsl_ddr_cfg_regs_t * ddr)897 static void set_ddr_data_init(fsl_ddr_cfg_regs_t *ddr)
898 {
899 unsigned int init_value; /* Initialization value */
900
901 init_value = 0xDEADBEEF;
902 ddr->ddr_data_init = init_value;
903 }
904
905 /*
906 * DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL)
907 * The old controller on the 8540/60 doesn't have this register.
908 * Hope it's OK to set it (to 0) anyway.
909 */
set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t * ddr,const memctl_options_t * popts)910 static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr,
911 const memctl_options_t *popts)
912 {
913 unsigned int clk_adjust; /* Clock adjust */
914
915 clk_adjust = popts->clk_adjust;
916 ddr->ddr_sdram_clk_cntl = (clk_adjust & 0xF) << 23;
917 }
918
919 /* DDR Initialization Address (DDR_INIT_ADDR) */
set_ddr_init_addr(fsl_ddr_cfg_regs_t * ddr)920 static void set_ddr_init_addr(fsl_ddr_cfg_regs_t *ddr)
921 {
922 unsigned int init_addr = 0; /* Initialization address */
923
924 ddr->ddr_init_addr = init_addr;
925 }
926
927 /* DDR Initialization Address (DDR_INIT_EXT_ADDR) */
set_ddr_init_ext_addr(fsl_ddr_cfg_regs_t * ddr)928 static void set_ddr_init_ext_addr(fsl_ddr_cfg_regs_t *ddr)
929 {
930 unsigned int uia = 0; /* Use initialization address */
931 unsigned int init_ext_addr = 0; /* Initialization address */
932
933 ddr->ddr_init_ext_addr = (0
934 | ((uia & 0x1) << 31)
935 | (init_ext_addr & 0xF)
936 );
937 }
938
939 /* DDR SDRAM Timing Configuration 4 (TIMING_CFG_4) */
set_timing_cfg_4(fsl_ddr_cfg_regs_t * ddr,const memctl_options_t * popts)940 static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr,
941 const memctl_options_t *popts)
942 {
943 unsigned int rwt = 0; /* Read-to-write turnaround for same CS */
944 unsigned int wrt = 0; /* Write-to-read turnaround for same CS */
945 unsigned int rrt = 0; /* Read-to-read turnaround for same CS */
946 unsigned int wwt = 0; /* Write-to-write turnaround for same CS */
947 unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */
948
949 #if defined(CONFIG_FSL_DDR3)
950 if (popts->burst_length == DDR_BL8) {
951 /* We set BL/2 for fixed BL8 */
952 rrt = 0; /* BL/2 clocks */
953 wwt = 0; /* BL/2 clocks */
954 } else {
955 /* We need to set BL/2 + 2 to BC4 and OTF */
956 rrt = 2; /* BL/2 + 2 clocks */
957 wwt = 2; /* BL/2 + 2 clocks */
958 }
959 dll_lock = 1; /* tDLLK = 512 clocks from spec */
960 #endif
961 ddr->timing_cfg_4 = (0
962 | ((rwt & 0xf) << 28)
963 | ((wrt & 0xf) << 24)
964 | ((rrt & 0xf) << 20)
965 | ((wwt & 0xf) << 16)
966 | (dll_lock & 0x3)
967 );
968 debug("FSLDDR: timing_cfg_4 = 0x%08x\n", ddr->timing_cfg_4);
969 }
970
971 /* DDR SDRAM Timing Configuration 5 (TIMING_CFG_5) */
set_timing_cfg_5(fsl_ddr_cfg_regs_t * ddr)972 static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr)
973 {
974 unsigned int rodt_on = 0; /* Read to ODT on */
975 unsigned int rodt_off = 0; /* Read to ODT off */
976 unsigned int wodt_on = 0; /* Write to ODT on */
977 unsigned int wodt_off = 0; /* Write to ODT off */
978
979 #if defined(CONFIG_FSL_DDR3)
980 rodt_on = 3; /* 2 clocks */
981 rodt_off = 4; /* 4 clocks */
982 wodt_on = 2; /* 1 clocks */
983 wodt_off = 4; /* 4 clocks */
984 #endif
985
986 ddr->timing_cfg_5 = (0
987 | ((rodt_on & 0x1f) << 24)
988 | ((rodt_off & 0x7) << 20)
989 | ((wodt_on & 0x1f) << 12)
990 | ((wodt_off & 0x7) << 8)
991 );
992 debug("FSLDDR: timing_cfg_5 = 0x%08x\n", ddr->timing_cfg_5);
993 }
994
995 /* DDR ZQ Calibration Control (DDR_ZQ_CNTL) */
set_ddr_zq_cntl(fsl_ddr_cfg_regs_t * ddr,unsigned int zq_en)996 static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en)
997 {
998 unsigned int zqinit = 0;/* POR ZQ Calibration Time (tZQinit) */
999 /* Normal Operation Full Calibration Time (tZQoper) */
1000 unsigned int zqoper = 0;
1001 /* Normal Operation Short Calibration Time (tZQCS) */
1002 unsigned int zqcs = 0;
1003
1004 if (zq_en) {
1005 zqinit = 9; /* 512 clocks */
1006 zqoper = 8; /* 256 clocks */
1007 zqcs = 6; /* 64 clocks */
1008 }
1009
1010 ddr->ddr_zq_cntl = (0
1011 | ((zq_en & 0x1) << 31)
1012 | ((zqinit & 0xF) << 24)
1013 | ((zqoper & 0xF) << 16)
1014 | ((zqcs & 0xF) << 8)
1015 );
1016 }
1017
1018 /* DDR Write Leveling Control (DDR_WRLVL_CNTL) */
set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t * ddr,unsigned int wrlvl_en,const memctl_options_t * popts)1019 static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en,
1020 const memctl_options_t *popts)
1021 {
1022 /*
1023 * First DQS pulse rising edge after margining mode
1024 * is programmed (tWL_MRD)
1025 */
1026 unsigned int wrlvl_mrd = 0;
1027 /* ODT delay after margining mode is programmed (tWL_ODTEN) */
1028 unsigned int wrlvl_odten = 0;
1029 /* DQS/DQS_ delay after margining mode is programmed (tWL_DQSEN) */
1030 unsigned int wrlvl_dqsen = 0;
1031 /* WRLVL_SMPL: Write leveling sample time */
1032 unsigned int wrlvl_smpl = 0;
1033 /* WRLVL_WLR: Write leveling repeition time */
1034 unsigned int wrlvl_wlr = 0;
1035 /* WRLVL_START: Write leveling start time */
1036 unsigned int wrlvl_start = 0;
1037
1038 /* suggest enable write leveling for DDR3 due to fly-by topology */
1039 if (wrlvl_en) {
1040 /* tWL_MRD min = 40 nCK, we set it 64 */
1041 wrlvl_mrd = 0x6;
1042 /* tWL_ODTEN 128 */
1043 wrlvl_odten = 0x7;
1044 /* tWL_DQSEN min = 25 nCK, we set it 32 */
1045 wrlvl_dqsen = 0x5;
1046 /*
1047 * Write leveling sample time at least need 6 clocks
1048 * higher than tWLO to allow enough time for progagation
1049 * delay and sampling the prime data bits.
1050 */
1051 wrlvl_smpl = 0xf;
1052 /*
1053 * Write leveling repetition time
1054 * at least tWLO + 6 clocks clocks
1055 * we set it 32
1056 */
1057 wrlvl_wlr = 0x5;
1058 /*
1059 * Write leveling start time
1060 * The value use for the DQS_ADJUST for the first sample
1061 * when write leveling is enabled.
1062 */
1063 wrlvl_start = 0x8;
1064 /*
1065 * Override the write leveling sample and start time
1066 * according to specific board
1067 */
1068 if (popts->wrlvl_override) {
1069 wrlvl_smpl = popts->wrlvl_sample;
1070 wrlvl_start = popts->wrlvl_start;
1071 }
1072 }
1073
1074 ddr->ddr_wrlvl_cntl = (0
1075 | ((wrlvl_en & 0x1) << 31)
1076 | ((wrlvl_mrd & 0x7) << 24)
1077 | ((wrlvl_odten & 0x7) << 20)
1078 | ((wrlvl_dqsen & 0x7) << 16)
1079 | ((wrlvl_smpl & 0xf) << 12)
1080 | ((wrlvl_wlr & 0x7) << 8)
1081 | ((wrlvl_start & 0x1F) << 0)
1082 );
1083 }
1084
1085 /* DDR Self Refresh Counter (DDR_SR_CNTR) */
set_ddr_sr_cntr(fsl_ddr_cfg_regs_t * ddr,unsigned int sr_it)1086 static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr, unsigned int sr_it)
1087 {
1088 /* Self Refresh Idle Threshold */
1089 ddr->ddr_sr_cntr = (sr_it & 0xF) << 16;
1090 }
1091
1092 /* DDR SDRAM Register Control Word 1 (DDR_SDRAM_RCW_1) */
set_ddr_sdram_rcw_1(fsl_ddr_cfg_regs_t * ddr)1093 static void set_ddr_sdram_rcw_1(fsl_ddr_cfg_regs_t *ddr)
1094 {
1095 unsigned int rcw0 = 0; /* RCW0: Register Control Word 0 */
1096 unsigned int rcw1 = 0; /* RCW1: Register Control Word 1 */
1097 unsigned int rcw2 = 0; /* RCW2: Register Control Word 2 */
1098 unsigned int rcw3 = 0; /* RCW3: Register Control Word 3 */
1099 unsigned int rcw4 = 0; /* RCW4: Register Control Word 4 */
1100 unsigned int rcw5 = 0; /* RCW5: Register Control Word 5 */
1101 unsigned int rcw6 = 0; /* RCW6: Register Control Word 6 */
1102 unsigned int rcw7 = 0; /* RCW7: Register Control Word 7 */
1103
1104 ddr->ddr_sdram_rcw_1 = (0
1105 | ((rcw0 & 0xF) << 28)
1106 | ((rcw1 & 0xF) << 24)
1107 | ((rcw2 & 0xF) << 20)
1108 | ((rcw3 & 0xF) << 16)
1109 | ((rcw4 & 0xF) << 12)
1110 | ((rcw5 & 0xF) << 8)
1111 | ((rcw6 & 0xF) << 4)
1112 | ((rcw7 & 0xF) << 0)
1113 );
1114 }
1115
1116 /* DDR SDRAM Register Control Word 2 (DDR_SDRAM_RCW_2) */
set_ddr_sdram_rcw_2(fsl_ddr_cfg_regs_t * ddr)1117 static void set_ddr_sdram_rcw_2(fsl_ddr_cfg_regs_t *ddr)
1118 {
1119 unsigned int rcw8 = 0; /* RCW0: Register Control Word 8 */
1120 unsigned int rcw9 = 0; /* RCW1: Register Control Word 9 */
1121 unsigned int rcw10 = 0; /* RCW2: Register Control Word 10 */
1122 unsigned int rcw11 = 0; /* RCW3: Register Control Word 11 */
1123 unsigned int rcw12 = 0; /* RCW4: Register Control Word 12 */
1124 unsigned int rcw13 = 0; /* RCW5: Register Control Word 13 */
1125 unsigned int rcw14 = 0; /* RCW6: Register Control Word 14 */
1126 unsigned int rcw15 = 0; /* RCW7: Register Control Word 15 */
1127
1128 ddr->ddr_sdram_rcw_2 = (0
1129 | ((rcw8 & 0xF) << 28)
1130 | ((rcw9 & 0xF) << 24)
1131 | ((rcw10 & 0xF) << 20)
1132 | ((rcw11 & 0xF) << 16)
1133 | ((rcw12 & 0xF) << 12)
1134 | ((rcw13 & 0xF) << 8)
1135 | ((rcw14 & 0xF) << 4)
1136 | ((rcw15 & 0xF) << 0)
1137 );
1138 }
1139
1140 unsigned int
check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t * ddr)1141 check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
1142 {
1143 unsigned int res = 0;
1144
1145 /*
1146 * Check that DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] are
1147 * not set at the same time.
1148 */
1149 if (ddr->ddr_sdram_cfg & 0x10000000
1150 && ddr->ddr_sdram_cfg & 0x00008000) {
1151 printf("Error: DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] "
1152 " should not be set at the same time.\n");
1153 res++;
1154 }
1155
1156 return res;
1157 }
1158
1159 unsigned int
compute_fsl_memctl_config_regs(const memctl_options_t * popts,fsl_ddr_cfg_regs_t * ddr,const common_timing_params_t * common_dimm,const dimm_params_t * dimm_params,unsigned int dbw_cap_adj)1160 compute_fsl_memctl_config_regs(const memctl_options_t *popts,
1161 fsl_ddr_cfg_regs_t *ddr,
1162 const common_timing_params_t *common_dimm,
1163 const dimm_params_t *dimm_params,
1164 unsigned int dbw_cap_adj)
1165 {
1166 unsigned int i;
1167 unsigned int cas_latency;
1168 unsigned int additive_latency;
1169 unsigned int sr_it;
1170 unsigned int zq_en;
1171 unsigned int wrlvl_en;
1172
1173 memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t));
1174
1175 if (common_dimm == NULL) {
1176 printf("Error: subset DIMM params struct null pointer\n");
1177 return 1;
1178 }
1179
1180 /*
1181 * Process overrides first.
1182 *
1183 * FIXME: somehow add dereated caslat to this
1184 */
1185 cas_latency = (popts->cas_latency_override)
1186 ? popts->cas_latency_override_value
1187 : common_dimm->lowest_common_SPD_caslat;
1188
1189 additive_latency = (popts->additive_latency_override)
1190 ? popts->additive_latency_override_value
1191 : common_dimm->additive_latency;
1192
1193 sr_it = (popts->auto_self_refresh_en)
1194 ? popts->sr_it
1195 : 0;
1196 /* ZQ calibration */
1197 zq_en = (popts->zq_en) ? 1 : 0;
1198 /* write leveling */
1199 wrlvl_en = (popts->wrlvl_en) ? 1 : 0;
1200
1201 /* Chip Select Memory Bounds (CSn_BNDS) */
1202 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1203 unsigned long long ea = 0, sa = 0;
1204
1205 if (popts->ba_intlv_ctl && (i > 0) &&
1206 ((popts->ba_intlv_ctl & 0x60) != FSL_DDR_CS2_CS3 )) {
1207 /* Don't set up boundaries for other CS
1208 * other than CS0, if bank interleaving
1209 * is enabled and not CS2+CS3 interleaved.
1210 * But we need to set the ODT_RD_CFG and
1211 * ODT_WR_CFG for CS1_CONFIG here.
1212 */
1213 set_csn_config(i, ddr, popts, dimm_params);
1214 break;
1215 }
1216
1217 if (dimm_params[i/2].n_ranks == 0) {
1218 debug("Skipping setup of CS%u "
1219 "because n_ranks on DIMM %u is 0\n", i, i/2);
1220 continue;
1221 }
1222 if (popts->memctl_interleaving && popts->ba_intlv_ctl) {
1223 /*
1224 * This works superbank 2CS
1225 * There are 2 memory controllers configured
1226 * identically, memory is interleaved between them,
1227 * and each controller uses rank interleaving within
1228 * itself. Therefore the starting and ending address
1229 * on each controller is twice the amount present on
1230 * each controller.
1231 */
1232 unsigned long long rank_density
1233 = dimm_params[0].capacity;
1234 ea = (2 * (rank_density >> dbw_cap_adj)) - 1;
1235 }
1236 else if (!popts->memctl_interleaving && popts->ba_intlv_ctl) {
1237 /*
1238 * If memory interleaving between controllers is NOT
1239 * enabled, the starting address for each memory
1240 * controller is distinct. However, because rank
1241 * interleaving is enabled, the starting and ending
1242 * addresses of the total memory on that memory
1243 * controller needs to be programmed into its
1244 * respective CS0_BNDS.
1245 */
1246 unsigned long long rank_density
1247 = dimm_params[i/2].rank_density;
1248 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
1249 case FSL_DDR_CS0_CS1_CS2_CS3:
1250 /* CS0+CS1+CS2+CS3 interleaving, only CS0_CNDS
1251 * needs to be set.
1252 */
1253 sa = common_dimm->base_address;
1254 ea = sa + (4 * (rank_density >> dbw_cap_adj))-1;
1255 break;
1256 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
1257 /* CS0+CS1 and CS2+CS3 interleaving, CS0_CNDS
1258 * and CS2_CNDS need to be set.
1259 */
1260 if (!(i&1)) {
1261 sa = dimm_params[i/2].base_address;
1262 ea = sa + (i * (rank_density >>
1263 dbw_cap_adj)) - 1;
1264 }
1265 break;
1266 case FSL_DDR_CS0_CS1:
1267 /* CS0+CS1 interleaving, CS0_CNDS needs
1268 * to be set
1269 */
1270 sa = common_dimm->base_address;
1271 ea = sa + (2 * (rank_density >> dbw_cap_adj))-1;
1272 break;
1273 case FSL_DDR_CS2_CS3:
1274 /* CS2+CS3 interleaving*/
1275 if (i == 2) {
1276 sa = dimm_params[i/2].base_address;
1277 ea = sa + (2 * (rank_density >>
1278 dbw_cap_adj)) - 1;
1279 }
1280 break;
1281 default: /* No bank(chip-select) interleaving */
1282 break;
1283 }
1284 }
1285 else if (popts->memctl_interleaving && !popts->ba_intlv_ctl) {
1286 /*
1287 * Only the rank on CS0 of each memory controller may
1288 * be used if memory controller interleaving is used
1289 * without rank interleaving within each memory
1290 * controller. However, the ending address programmed
1291 * into each CS0 must be the sum of the amount of
1292 * memory in the two CS0 ranks.
1293 */
1294 if (i == 0) {
1295 unsigned long long rank_density
1296 = dimm_params[0].rank_density;
1297 ea = (2 * (rank_density >> dbw_cap_adj)) - 1;
1298 }
1299
1300 }
1301 else if (!popts->memctl_interleaving && !popts->ba_intlv_ctl) {
1302 /*
1303 * No rank interleaving and no memory controller
1304 * interleaving.
1305 */
1306 unsigned long long rank_density
1307 = dimm_params[i/2].rank_density;
1308 sa = dimm_params[i/2].base_address;
1309 ea = sa + (rank_density >> dbw_cap_adj) - 1;
1310 if (i&1) {
1311 if ((dimm_params[i/2].n_ranks == 1)) {
1312 /* Odd chip select, single-rank dimm */
1313 sa = 0;
1314 ea = 0;
1315 } else {
1316 /* Odd chip select, dual-rank DIMM */
1317 sa += rank_density >> dbw_cap_adj;
1318 ea += rank_density >> dbw_cap_adj;
1319 }
1320 }
1321 }
1322
1323 sa >>= 24;
1324 ea >>= 24;
1325
1326 ddr->cs[i].bnds = (0
1327 | ((sa & 0xFFF) << 16) /* starting address MSB */
1328 | ((ea & 0xFFF) << 0) /* ending address MSB */
1329 );
1330
1331 debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds);
1332 set_csn_config(i, ddr, popts, dimm_params);
1333 set_csn_config_2(i, ddr);
1334 }
1335
1336 #if !defined(CONFIG_FSL_DDR1)
1337 set_timing_cfg_0(ddr);
1338 #endif
1339
1340 set_timing_cfg_3(ddr, common_dimm, cas_latency);
1341 set_timing_cfg_1(ddr, popts, common_dimm, cas_latency);
1342 set_timing_cfg_2(ddr, popts, common_dimm,
1343 cas_latency, additive_latency);
1344
1345 set_ddr_sdram_cfg(ddr, popts, common_dimm);
1346
1347 set_ddr_sdram_cfg_2(ddr, popts);
1348 set_ddr_sdram_mode(ddr, popts, common_dimm,
1349 cas_latency, additive_latency);
1350 set_ddr_sdram_mode_2(ddr, popts);
1351 set_ddr_sdram_interval(ddr, popts, common_dimm);
1352 set_ddr_data_init(ddr);
1353 set_ddr_sdram_clk_cntl(ddr, popts);
1354 set_ddr_init_addr(ddr);
1355 set_ddr_init_ext_addr(ddr);
1356 set_timing_cfg_4(ddr, popts);
1357 set_timing_cfg_5(ddr);
1358
1359 set_ddr_zq_cntl(ddr, zq_en);
1360 set_ddr_wrlvl_cntl(ddr, wrlvl_en, popts);
1361
1362 set_ddr_sr_cntr(ddr, sr_it);
1363
1364 set_ddr_sdram_rcw_1(ddr);
1365 set_ddr_sdram_rcw_2(ddr);
1366
1367 return check_fsl_memctl_config_regs(ddr);
1368 }
1369