1 /* 2 * Copyright 2008 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * Version 2 as published by the Free Software Foundation. 7 */ 8 9 #ifndef DDR2_DIMM_PARAMS_H 10 #define DDR2_DIMM_PARAMS_H 11 12 /* Parameters for a DDR2 dimm computed from the SPD */ 13 typedef struct dimm_params_s { 14 15 /* DIMM organization parameters */ 16 char mpart[19]; /* guaranteed null terminated */ 17 18 unsigned int n_ranks; 19 unsigned long long rank_density; 20 unsigned long long capacity; 21 unsigned int data_width; 22 unsigned int primary_sdram_width; 23 unsigned int ec_sdram_width; 24 unsigned int registered_dimm; 25 26 /* SDRAM device parameters */ 27 unsigned int n_row_addr; 28 unsigned int n_col_addr; 29 unsigned int edc_config; /* 0 = none, 1 = parity, 2 = ECC */ 30 unsigned int n_banks_per_sdram_device; 31 unsigned int burst_lengths_bitmask; /* BL=4 bit 2, BL=8 = bit 3 */ 32 unsigned int row_density; 33 34 /* used in computing base address of DIMMs */ 35 unsigned long long base_address; 36 /* mirrored DIMMs */ 37 unsigned int mirrored_dimm; /* only for ddr3 */ 38 39 /* DIMM timing parameters */ 40 41 unsigned int mtb_ps; /* medium timebase ps, only for ddr3 */ 42 unsigned int tAA_ps; /* minimum CAS latency time, only for ddr3 */ 43 unsigned int tFAW_ps; /* four active window delay, only for ddr3 */ 44 45 /* 46 * SDRAM clock periods 47 * The range for these are 1000-10000 so a short should be sufficient 48 */ 49 unsigned int tCKmin_X_ps; 50 unsigned int tCKmin_X_minus_1_ps; 51 unsigned int tCKmin_X_minus_2_ps; 52 unsigned int tCKmax_ps; 53 54 /* SPD-defined CAS latencies */ 55 unsigned int caslat_X; 56 unsigned int caslat_X_minus_1; 57 unsigned int caslat_X_minus_2; 58 59 unsigned int caslat_lowest_derated; /* Derated CAS latency */ 60 61 /* basic timing parameters */ 62 unsigned int tRCD_ps; 63 unsigned int tRP_ps; 64 unsigned int tRAS_ps; 65 66 unsigned int tWR_ps; /* maximum = 63750 ps */ 67 unsigned int tWTR_ps; /* maximum = 63750 ps */ 68 unsigned int tRFC_ps; /* max = 255 ns + 256 ns + .75 ns 69 = 511750 ps */ 70 71 unsigned int tRRD_ps; /* maximum = 63750 ps */ 72 unsigned int tRC_ps; /* maximum = 254 ns + .75 ns = 254750 ps */ 73 74 unsigned int refresh_rate_ps; 75 76 /* DDR3 doesn't need these as below */ 77 unsigned int tIS_ps; /* byte 32, spd->ca_setup */ 78 unsigned int tIH_ps; /* byte 33, spd->ca_hold */ 79 unsigned int tDS_ps; /* byte 34, spd->data_setup */ 80 unsigned int tDH_ps; /* byte 35, spd->data_hold */ 81 unsigned int tRTP_ps; /* byte 38, spd->trtp */ 82 unsigned int tDQSQ_max_ps; /* byte 44, spd->tdqsq */ 83 unsigned int tQHS_ps; /* byte 45, spd->tqhs */ 84 } dimm_params_t; 85 86 extern unsigned int ddr_compute_dimm_parameters( 87 const generic_spd_eeprom_t *spd, 88 dimm_params_t *pdimm, 89 unsigned int dimm_number); 90 91 #endif 92