1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * (C) Copyright 2017 Rockchip Electronics Co., Ltd
4  */
5 #ifndef _ASM_ARCH_GRF_RK3128_H
6 #define _ASM_ARCH_GRF_RK3128_H
7 
8 #include <common.h>
9 
10 struct rk3128_grf {
11 	unsigned int reserved[0x2a];
12 	unsigned int gpio0a_iomux;
13 	unsigned int gpio0b_iomux;
14 	unsigned int gpio0c_iomux;
15 	unsigned int gpio0d_iomux;
16 	unsigned int gpio1a_iomux;
17 	unsigned int gpio1b_iomux;
18 	unsigned int gpio1c_iomux;
19 	unsigned int gpio1d_iomux;
20 	unsigned int gpio2a_iomux;
21 	unsigned int gpio2b_iomux;
22 	unsigned int gpio2c_iomux;
23 	unsigned int gpio2d_iomux;
24 	unsigned int gpio3a_iomux;
25 	unsigned int gpio3b_iomux;
26 	unsigned int gpio3c_iomux;
27 	unsigned int gpio3d_iomux;
28 	unsigned int gpio2c_iomux2;
29 	unsigned int grf_cif_iomux;
30 	unsigned int grf_cif_iomux1;
31 	unsigned int reserved1[(0x118 - 0xf0) / 4 - 1];
32 	unsigned int gpio0l_pull;
33 	unsigned int gpio0h_pull;
34 	unsigned int gpio1l_pull;
35 	unsigned int gpio1h_pull;
36 	unsigned int gpio2l_pull;
37 	unsigned int gpio2h_pull;
38 	unsigned int gpio3l_pull;
39 	unsigned int gpio3h_pull;
40 	unsigned int reserved2;
41 	unsigned int soc_con0;
42 	unsigned int soc_con1;
43 	unsigned int soc_con2;
44 	unsigned int soc_status0;
45 	unsigned int reserved3[6];
46 	unsigned int mac_con0;
47 	unsigned int mac_con1;
48 	unsigned int reserved4[4];
49 	unsigned int uoc0_con0;
50 	unsigned int reserved5;
51 	unsigned int uoc1_con1;
52 	unsigned int uoc1_con2;
53 	unsigned int uoc1_con3;
54 	unsigned int uoc1_con4;
55 	unsigned int uoc1_con5;
56 	unsigned int reserved6;
57 	unsigned int ddrc_stat;
58 	unsigned int reserved9;
59 	unsigned int soc_status1;
60 	unsigned int cpu_con0;
61 	unsigned int cpu_con1;
62 	unsigned int cpu_con2;
63 	unsigned int cpu_con3;
64 	unsigned int reserved10;
65 	unsigned int reserved11;
66 	unsigned int cpu_status0;
67 	unsigned int cpu_status1;
68 	unsigned int os_reg[8];
69 	unsigned int reserved12[(0x280 - 0x1e4) / 4 - 1];
70 	unsigned int usbphy0_con[8];
71 	unsigned int usbphy1_con[8];
72 	unsigned int uoc_status0;
73 	unsigned int reserved13[(0x300 - 0x2c0) / 4 - 1];
74 	unsigned int chip_tag;
75 	unsigned int sdmmc_det_cnt;
76 };
77 check_member(rk3128_grf, sdmmc_det_cnt, 0x304);
78 
79 struct rk3128_pmu {
80 	unsigned int wakeup_cfg;
81 	unsigned int pwrdn_con;
82 	unsigned int pwrdn_st;
83 	unsigned int idle_req;
84 	unsigned int idle_st;
85 	unsigned int pwrmode_con;
86 	unsigned int pwr_state;
87 	unsigned int osc_cnt;
88 	unsigned int core_pwrdwn_cnt;
89 	unsigned int core_pwrup_cnt;
90 	unsigned int sft_con;
91 	unsigned int ddr_sref_st;
92 	unsigned int int_con;
93 	unsigned int int_st;
94 	unsigned int sys_reg[4];
95 };
96 check_member(rk3128_pmu, int_st, 0x34);
97 
98 /* GRF_GPIO0A_IOMUX */
99 enum {
100 	GPIO0A7_SHIFT		= 14,
101 	GPIO0A7_MASK		= 3 << GPIO0A7_SHIFT,
102 	GPIO0A7_GPIO		= 0,
103 	GPIO0A7_I2C3_SDA,
104 
105 	GPIO0A6_SHIFT		= 12,
106 	GPIO0A6_MASK		= 3 << GPIO0A6_SHIFT,
107 	GPIO0A6_GPIO		= 0,
108 	GPIO0A6_I2C3_SCL,
109 
110 	GPIO0A3_SHIFT		= 6,
111 	GPIO0A3_MASK		= 3 << GPIO0A3_SHIFT,
112 	GPIO0A3_GPIO		= 0,
113 	GPIO0A3_I2C1_SDA,
114 
115 	GPIO0A2_SHIFT		= 4,
116 	GPIO0A2_MASK		= 1 << GPIO0A2_SHIFT,
117 	GPIO0A2_GPIO		= 0,
118 	GPIO0A2_I2C1_SCL,
119 
120 	GPIO0A1_SHIFT		= 2,
121 	GPIO0A1_MASK		= 1 << GPIO0A1_SHIFT,
122 	GPIO0A1_GPIO		= 0,
123 	GPIO0A1_I2C0_SDA,
124 
125 	GPIO0A0_SHIFT		= 0,
126 	GPIO0A0_MASK		= 1 << GPIO0A0_SHIFT,
127 	GPIO0A0_GPIO		= 0,
128 	GPIO0A0_I2C0_SCL,
129 };
130 
131 /* GRF_GPIO0B_IOMUX */
132 enum {
133 	GPIO0B6_SHIFT		= 12,
134 	GPIO0B6_MASK		= 3 << GPIO0B6_SHIFT,
135 	GPIO0B6_GPIO		= 0,
136 	GPIO0B6_I2S_SDI,
137 	GPIO0B6_SPI_CSN0,
138 
139 	GPIO0B5_SHIFT		= 10,
140 	GPIO0B5_MASK		= 3 << GPIO0B5_SHIFT,
141 	GPIO0B5_GPIO		= 0,
142 	GPIO0B5_I2S_SDO,
143 	GPIO0B5_SPI_RXD,
144 
145 	GPIO0B4_SHIFT		= 8,
146 	GPIO0B4_MASK		= 1 << GPIO0B4_SHIFT,
147 	GPIO0B4_GPIO		= 0,
148 	GPIO0B4_I2S_LRCKTX,
149 
150 	GPIO0B3_SHIFT		= 6,
151 	GPIO0B3_MASK		= 3 << GPIO0B3_SHIFT,
152 	GPIO0B3_GPIO		= 0,
153 	GPIO0B3_I2S_LRCKRX,
154 	GPIO0B3_SPI_TXD,
155 
156 	GPIO0B1_SHIFT		= 2,
157 	GPIO0B1_MASK		= 3,
158 	GPIO0B1_GPIO		= 0,
159 	GPIO0B1_I2S_SCLK,
160 	GPIO0B1_SPI_CLK,
161 
162 	GPIO0B0_SHIFT		= 0,
163 	GPIO0B0_MASK		= 3,
164 	GPIO0B0_GPIO		= 0,
165 	GPIO0B0_I2S1_MCLK,
166 };
167 
168 /* GRF_GPIO0D_IOMUX */
169 enum {
170 	GPIO0D4_SHIFT		= 8,
171 	GPIO0D4_MASK		= 1 << GPIO0D4_SHIFT,
172 	GPIO0D4_GPIO		= 0,
173 	GPIO0D4_PWM2,
174 
175 	GPIO0D3_SHIFT		= 6,
176 	GPIO0D3_MASK		= 1 << GPIO0D3_SHIFT,
177 	GPIO0D3_GPIO		= 0,
178 	GPIO0D3_PWM1,
179 
180 	GPIO0D2_SHIFT		= 4,
181 	GPIO0D2_MASK		= 1 << GPIO0D2_SHIFT,
182 	GPIO0D2_GPIO		= 0,
183 	GPIO0D2_PWM0,
184 
185 	GPIO0D1_SHIFT		= 2,
186 	GPIO0D1_MASK		= 1 << GPIO0D1_SHIFT,
187 	GPIO0D1_GPIO		= 0,
188 	GPIO0D1_UART2_CTSN,
189 
190 	GPIO0D0_SHIFT		= 0,
191 	GPIO0D0_MASK		= 3 << GPIO0D0_SHIFT,
192 	GPIO0D0_GPIO		= 0,
193 	GPIO0D0_UART2_RTSN,
194 	GPIO0D0_PMIC_SLEEP,
195 };
196 
197 /* GRF_GPIO1A_IOMUX */
198 enum {
199 	GPIO1A5_SHIFT		= 10,
200 	GPIO1A5_MASK		= 3 << GPIO1A5_SHIFT,
201 	GPIO1A5_GPIO		= 0,
202 	GPIO1A5_I2S_SDI,
203 	GPIO1A5_SDMMC_DATA3,
204 
205 	GPIO1A4_SHIFT		= 8,
206 	GPIO1A4_MASK		= 3 << GPIO1A4_SHIFT,
207 	GPIO1A4_GPIO		= 0,
208 	GPIO1A4_I2S_SD0,
209 	GPIO1A4_SDMMC_DATA2,
210 
211 	GPIO1A3_SHIFT		= 6,
212 	GPIO1A3_MASK		= 1 << GPIO1A3_SHIFT,
213 	GPIO1A3_GPIO		= 0,
214 	GPIO1A3_I2S_LRCKTX,
215 
216 	GPIO1A2_SHIFT		= 4,
217 	GPIO1A2_MASK		= 3 << GPIO1A2_SHIFT,
218 	GPIO1A2_GPIO		= 0,
219 	GPIO1A2_I2S_LRCKRX,
220 	GPIO1A2_SDMMC_DATA1,
221 
222 	GPIO1A1_SHIFT		= 2,
223 	GPIO1A1_MASK		= 3 << GPIO1A1_SHIFT,
224 	GPIO1A1_GPIO		= 0,
225 	GPIO1A1_I2S_SCLK,
226 	GPIO1A1_SDMMC_DATA0,
227 	GPIO1A1_PMIC_SLEEP,
228 
229 	GPIO1A0_SHIFT		= 0,
230 	GPIO1A0_MASK		= 3,
231 	GPIO1A0_GPIO		= 0,
232 	GPIO1A0_I2S_MCLK,
233 	GPIO1A0_SDMMC_CLKOUT,
234 	GPIO1A0_XIN32K,
235 
236 };
237 
238 /* GRF_GPIO1B_IOMUX */
239 enum {
240 	GPIO1B7_SHIFT		= 14,
241 	GPIO1B7_MASK		= 1 << GPIO1B7_SHIFT,
242 	GPIO1B7_GPIO		= 0,
243 	GPIO1B7_MMC0_CMD,
244 
245 	GPIO1B6_SHIFT		= 12,
246 	GPIO1B6_MASK		= 1 << GPIO1B6_SHIFT,
247 	GPIO1B6_GPIO		= 0,
248 	GPIO1B6_MMC_PWREN,
249 
250 	GPIO1B2_SHIFT		= 4,
251 	GPIO1B2_MASK		= 3 << GPIO1B2_SHIFT,
252 	GPIO1B2_GPIO		= 0,
253 	GPIO1B2_SPI_RXD,
254 	GPIO1B2_UART1_SIN,
255 
256 	GPIO1B1_SHIFT		= 2,
257 	GPIO1B1_MASK		= 3 << GPIO1B1_SHIFT,
258 	GPIO1B1_GPIO		= 0,
259 	GPIO1B1_SPI_TXD,
260 	GPIO1B1_UART1_SOUT,
261 
262 	GPIO1B0_SHIFT		= 0,
263 	GPIO1B0_MASK		= 3 << GPIO1B0_SHIFT,
264 	GPIO1B0_GPIO		= 0,
265 	GPIO1B0_SPI_CLK,
266 	GPIO1B0_UART1_CTSN
267 };
268 
269 /* GRF_GPIO1C_IOMUX */
270 enum {
271 	GPIO1C6_SHIFT		= 12,
272 	GPIO1C6_MASK		= 3 << GPIO1C6_SHIFT,
273 	GPIO1C6_GPIO		= 0,
274 	GPIO1C6_NAND_CS2,
275 	GPIO1C6_EMMC_CMD,
276 
277 	GPIO1C5_SHIFT		= 10,
278 	GPIO1C5_MASK		= 3 << GPIO1C5_SHIFT,
279 	GPIO1C5_GPIO		= 0,
280 	GPIO1C5_MMC0_D3,
281 	GPIO1C5_JTAG_TMS,
282 
283 	GPIO1C4_SHIFT		= 8,
284 	GPIO1C4_MASK		= 3 << GPIO1C4_SHIFT,
285 	GPIO1C4_GPIO		= 0,
286 	GPIO1C4_MMC0_D2,
287 	GPIO1C4_JTAG_TCK,
288 
289 	GPIO1C3_SHIFT		= 6,
290 	GPIO1C3_MASK		= 3 << GPIO1C3_SHIFT,
291 	GPIO1C3_GPIO		= 0,
292 	GPIO1C3_MMC0_D1,
293 	GPIO1C3_UART2_RX,
294 
295 	GPIO1C2_SHIFT		= 4,
296 	GPIO1C2_MASK		= 3 << GPIO1C2_SHIFT,
297 	GPIO1C2_GPIO		= 0,
298 	GPIO1C2_MMC0_D0,
299 	GPIO1C2_UART2_TX,
300 
301 	GPIO1C1_SHIFT		= 2,
302 	GPIO1C1_MASK		= 1 << GPIO1C1_SHIFT,
303 	GPIO1C1_GPIO		= 0,
304 	GPIO1C1_MMC0_DETN,
305 
306 	GPIO1C0_SHIFT		= 0,
307 	GPIO1C0_MASK		= 1 << GPIO1C0_SHIFT,
308 	GPIO1C0_GPIO		= 0,
309 	GPIO1C0_MMC0_CLKOUT,
310 };
311 
312 /* GRF_GPIO1D_IOMUX */
313 enum {
314 	GPIO1D7_SHIFT		= 14,
315 	GPIO1D7_MASK		= 3 << GPIO1D7_SHIFT,
316 	GPIO1D7_GPIO		= 0,
317 	GPIO1D7_NAND_D7,
318 	GPIO1D7_EMMC_D7,
319 	GPIO1D7_SPI_CSN1,
320 
321 	GPIO1D6_SHIFT		= 12,
322 	GPIO1D6_MASK		= 3 << GPIO1D6_SHIFT,
323 	GPIO1D6_GPIO		= 0,
324 	GPIO1D6_NAND_D6,
325 	GPIO1D6_EMMC_D6,
326 	GPIO1D6_SPI_CSN0,
327 
328 	GPIO1D5_SHIFT		= 10,
329 	GPIO1D5_MASK		= 3 << GPIO1D5_SHIFT,
330 	GPIO1D5_GPIO		= 0,
331 	GPIO1D5_NAND_D5,
332 	GPIO1D5_EMMC_D5,
333 	GPIO1D5_SPI_TXD1,
334 
335 	GPIO1D4_SHIFT		= 8,
336 	GPIO1D4_MASK		= 3 << GPIO1D4_SHIFT,
337 	GPIO1D4_GPIO		= 0,
338 	GPIO1D4_NAND_D4,
339 	GPIO1D4_EMMC_D4,
340 	GPIO1D4_SPI_RXD1,
341 
342 	GPIO1D3_SHIFT		= 6,
343 	GPIO1D3_MASK		= 3 << GPIO1D3_SHIFT,
344 	GPIO1D3_GPIO		= 0,
345 	GPIO1D3_NAND_D3,
346 	GPIO1D3_EMMC_D3,
347 	GPIO1D3_SFC_SIO3,
348 
349 	GPIO1D2_SHIFT		= 4,
350 	GPIO1D2_MASK		= 3 << GPIO1D2_SHIFT,
351 	GPIO1D2_GPIO		= 0,
352 	GPIO1D2_NAND_D2,
353 	GPIO1D2_EMMC_D2,
354 	GPIO1D2_SFC_SIO2,
355 
356 	GPIO1D1_SHIFT		= 2,
357 	GPIO1D1_MASK		= 3 << GPIO1D1_SHIFT,
358 	GPIO1D1_GPIO		= 0,
359 	GPIO1D1_NAND_D1,
360 	GPIO1D1_EMMC_D1,
361 	GPIO1D1_SFC_SIO1,
362 
363 	GPIO1D0_SHIFT		= 0,
364 	GPIO1D0_MASK		= 3 << GPIO1D0_SHIFT,
365 	GPIO1D0_GPIO		= 0,
366 	GPIO1D0_NAND_D0,
367 	GPIO1D0_EMMC_D0,
368 	GPIO1D0_SFC_SIO0,
369 };
370 
371 /* GRF_GPIO2A_IOMUX */
372 enum {
373 	GPIO2A7_SHIFT		= 14,
374 	GPIO2A7_MASK		= 3 << GPIO2A7_SHIFT,
375 	GPIO2A7_GPIO		= 0,
376 	GPIO2A7_NAND_DQS,
377 	GPIO2A7_EMMC_CLKOUT,
378 
379 	GPIO2A6_SHIFT		= 12,
380 	GPIO2A6_MASK		= 1 << GPIO2A6_SHIFT,
381 	GPIO2A6_GPIO		= 0,
382 	GPIO2A6_NAND_CS0,
383 
384 	GPIO2A5_SHIFT		= 10,
385 	GPIO2A5_MASK		= 3 << GPIO2A5_SHIFT,
386 	GPIO2A5_GPIO		= 0,
387 	GPIO2A5_NAND_WP,
388 	GPIO2A5_EMMC_PWREN,
389 
390 	GPIO2A4_SHIFT		= 8,
391 	GPIO2A4_MASK		= 3 << GPIO2A4_SHIFT,
392 	GPIO2A4_GPIO		= 0,
393 	GPIO2A4_NAND_RDY,
394 	GPIO2A4_EMMC_CMD,
395 	GPIO2A3_SFC_CLK,
396 
397 	GPIO2A3_SHIFT		= 6,
398 	GPIO2A3_MASK		= 3 << GPIO2A3_SHIFT,
399 	GPIO2A3_GPIO		= 0,
400 	GPIO2A3_NAND_RDN,
401 	GPIO2A4_SFC_CSN1,
402 
403 	GPIO2A2_SHIFT		= 4,
404 	GPIO2A2_MASK		= 3 << GPIO2A2_SHIFT,
405 	GPIO2A2_GPIO		= 0,
406 	GPIO2A2_NAND_WRN,
407 	GPIO2A4_SFC_CSN0,
408 
409 	GPIO2A1_SHIFT		= 2,
410 	GPIO2A1_MASK		= 3 << GPIO2A1_SHIFT,
411 	GPIO2A1_GPIO		= 0,
412 	GPIO2A1_NAND_CLE,
413 	GPIO2A1_EMMC_CLKOUT,
414 
415 	GPIO2A0_SHIFT		= 0,
416 	GPIO2A0_MASK		= 3 << GPIO2A0_SHIFT,
417 	GPIO2A0_GPIO		= 0,
418 	GPIO2A0_NAND_ALE,
419 	GPIO2A0_SPI_CLK,
420 };
421 
422 /* GRF_GPIO2B_IOMUX */
423 enum {
424 	GPIO2B7_SHIFT		= 14,
425 	GPIO2B7_MASK		= 3 << GPIO2B7_SHIFT,
426 	GPIO2B7_GPIO		= 0,
427 	GPIO2B7_LCDC0_D13,
428 	GPIO2B7_EBC_SDCE5,
429 	GPIO2B7_GMAC_RXER,
430 
431 	GPIO2B6_SHIFT		= 12,
432 	GPIO2B6_MASK		= 3 << GPIO2B6_SHIFT,
433 	GPIO2B6_GPIO		= 0,
434 	GPIO2B6_LCDC0_D12,
435 	GPIO2B6_EBC_SDCE4,
436 	GPIO2B6_GMAC_CLK,
437 
438 	GPIO2B5_SHIFT		= 10,
439 	GPIO2B5_MASK		= 3 << GPIO2B5_SHIFT,
440 	GPIO2B5_GPIO		= 0,
441 	GPIO2B5_LCDC0_D11,
442 	GPIO2B5_EBC_SDCE3,
443 	GPIO2B5_GMAC_TXEN,
444 
445 	GPIO2B4_SHIFT		= 8,
446 	GPIO2B4_MASK		= 3 << GPIO2B4_SHIFT,
447 	GPIO2B4_GPIO		= 0,
448 	GPIO2B4_LCDC0_D10,
449 	GPIO2B4_EBC_SDCE2,
450 	GPIO2B4_GMAC_MDIO,
451 
452 	GPIO2B3_SHIFT		= 6,
453 	GPIO2B3_MASK		= 3 << GPIO2B3_SHIFT,
454 	GPIO2B3_GPIO		= 0,
455 	GPIO2B3_LCDC0_DEN,
456 	GPIO2B3_EBC_GDCLK,
457 	GPIO2B3_GMAC_RXCLK,
458 
459 	GPIO2B2_SHIFT		= 4,
460 	GPIO2B2_MASK		= 3 << GPIO2B2_SHIFT,
461 	GPIO2B2_GPIO		= 0,
462 	GPIO2B2_LCDC0_VSYNC,
463 	GPIO2B2_EBC_SDOE,
464 	GPIO2B2_GMAC_CRS,
465 
466 	GPIO2B1_SHIFT		= 2,
467 	GPIO2B1_MASK		= 3 << GPIO2B1_SHIFT,
468 	GPIO2B1_GPIO		= 0,
469 	GPIO2B1_LCDC0_HSYNC,
470 	GPIO2B1_EBC_SDLE,
471 	GPIO2B1_GMAC_TXCLK,
472 
473 	GPIO2B0_SHIFT		= 0,
474 	GPIO2B0_MASK		= 3 << GPIO2B0_SHIFT,
475 	GPIO2B0_GPIO		= 0,
476 	GPIO2B0_LCDC0_DCLK,
477 	GPIO2B0_EBC_SDCLK,
478 	GPIO2B0_GMAC_RXDV,
479 };
480 
481 /* GRF_GPIO2C_IOMUX */
482 enum {
483 	GPIO2C3_SHIFT		= 6,
484 	GPIO2C3_MASK		= 3 << GPIO2C3_SHIFT,
485 	GPIO2C3_GPIO		= 0,
486 	GPIO2C3_LCDC0_D17,
487 	GPIO2C3_EBC_GDPWR0,
488 	GPIO2C3_GMAC_TXD0,
489 
490 	GPIO2C2_SHIFT		= 4,
491 	GPIO2C2_MASK		= 3 << GPIO2C2_SHIFT,
492 	GPIO2C2_GPIO		= 0,
493 	GPIO2C2_LCDC0_D16,
494 	GPIO2C2_EBC_GDSP,
495 	GPIO2C2_GMAC_TXD1,
496 
497 	GPIO2C1_SHIFT		= 2,
498 	GPIO2C1_MASK		= 3 << GPIO2C1_SHIFT,
499 	GPIO2C1_GPIO		= 0,
500 	GPIO2C1_LCDC0_D15,
501 	GPIO2C1_EBC_GDOE,
502 	GPIO2C1_GMAC_RXD0,
503 
504 	GPIO2C0_SHIFT		= 0,
505 	GPIO2C0_MASK		= 3 << GPIO2C0_SHIFT,
506 	GPIO2C0_GPIO		= 0,
507 	GPIO2C0_LCDC0_D14,
508 	GPIO2C0_EBC_VCOM,
509 	GPIO2C0_GMAC_RXD1,
510 };
511 
512 /* GRF_GPIO2D_IOMUX */
513 enum {
514 	GPIO2D6_SHIFT		= 12,
515 	GPIO2D6_MASK		= 3 << GPIO2D6_SHIFT,
516 	GPIO2D6_GPIO		= 0,
517 	GPIO2D6_LCDC0_D22,
518 	GPIO2D6_GMAC_COL	= 4,
519 
520 	GPIO2D1_SHIFT		= 2,
521 	GPIO2D1_MASK		= 3 << GPIO2D1_SHIFT,
522 	GPIO2D1_GPIO		= 0,
523 	GPIO2D1_GMAC_MDC	= 3,
524 };
525 
526 /* GRF_GPIO2C_IOMUX2 */
527 enum {
528 	GPIO2C7_SHIFT		= 12,
529 	GPIO2C7_MASK		= 7 << GPIO2C7_SHIFT,
530 	GPIO2C7_GPIO		= 0,
531 	GPIO2C7_GMAC_TXD3	= 4,
532 
533 	GPIO2C6_SHIFT		= 12,
534 	GPIO2C6_MASK		= 7 << GPIO2C6_SHIFT,
535 	GPIO2C6_GPIO		= 0,
536 	GPIO2C6_GMAC_TXD2	= 4,
537 
538 	GPIO2C5_SHIFT		= 4,
539 	GPIO2C5_MASK		= 7 << GPIO2C5_SHIFT,
540 	GPIO2C5_GPIO		= 0,
541 	GPIO2C5_I2C2_SCL	= 3,
542 	GPIO2C5_GMAC_RXD2,
543 
544 	GPIO2C4_SHIFT		= 0,
545 	GPIO2C4_MASK		= 7 << GPIO2C4_SHIFT,
546 	GPIO2C4_GPIO		= 0,
547 	GPIO2C4_I2C2_SDA	= 3,
548 	GPIO2C4_GMAC_RXD2,
549 };
550 #endif
551