1 /* hp3000_sel.c: HP 3000 30030C Selector Channel simulator
2
3 Copyright (c) 2016-2021, J. David Bryan
4
5 Permission is hereby granted, free of charge, to any person obtaining a copy
6 of this software and associated documentation files (the "Software"), to deal
7 in the Software without restriction, including without limitation the rights
8 to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
9 copies of the Software, and to permit persons to whom the Software is
10 furnished to do so, subject to the following conditions:
11
12 The above copyright notice and this permission notice shall be included in
13 all copies or substantial portions of the Software.
14
15 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18 AUTHOR BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
19 ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
20 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
21
22 Except as contained in this notice, the name of the author shall not be used
23 in advertising or otherwise to promote the sale, use or other dealings in
24 this Software without prior written authorization from the author.
25
26 SEL HP 3000 Series III Selector Channel
27
28 08-Apr-21 JDB Expanded bank register width from 4 to 6 bits
29 01-Apr-21 JDB Removed REG_FIT from register definitions (obsolete)
30 09-Dec-19 JDB Replaced debugging macros with tracing macros
31 27-Dec-18 JDB Revised fall through comments to comply with gcc 7
32 05-Sep-17 JDB Changed REG_A (permit any symbolic override) to REG_X
33 10-Oct-16 JDB Renumbered debug flags to start at 0
34 Added port_read_memory, port_write_memory macros
35 11-Jul-16 JDB Change "sel_unit" from a UNIT to an array of one UNIT
36 30-Jun-16 JDB Reestablish active_dib pointer during sel_initialize
37 08-Jun-16 JDB Corrected %d format to %u for unsigned values
38 16-May-16 JDB abort_channel parameter is now a pointer-to-constant
39 21-Mar-16 JDB Changed uint16 types to HP_WORD
40 23-Sep-15 JDB First release version
41 27-Jan-15 JDB Passes the selector channel diagnostic (D429A)
42 10-Feb-13 JDB Created
43
44 References:
45 - HP 3000 Series II/III System Reference Manual
46 (30000-90020, July 1978)
47 - Stand-Alone HP 30030B/C Selector Channel Diagnostic
48 (30030-90011, July 1978)
49 - HP 3000 Series III Engineering Diagrams Set
50 (30000-90141, Apr-1980)
51
52
53 The HP 30030C Selector Channel provides high-speed data transfer between a
54 device and main memory. While several interfaces may be connected to the
55 selector channel bus, only one transfer is active at a time, and the channel
56 remains dedicated to that interface until the transfer is complete. The
57 channel contains its own memory port controller, so transfers to and from
58 memory bypass the I/O Processor.
59
60 Interfaces must have additional hardware to be channel-capable, as the
61 channel uses separate control and data signals from those used for direct
62 I/O. In addition, the multiplexer and selector channels differ somewhat in
63 their use of the signals, so interfaces are generally designed for use with
64 one or the other (the Selector Channel Maintenance Board is a notable
65 exception that uses jumpers to indicate which channel to use).
66
67 The transfer rate of the Series III selector channel is poorly documented.
68 Various rates are quoted in different publications: a 1.9 MB/second rate in
69 one, a 2.86 MB/second rate in another. Main memory access time is given as
70 300 nanoseconds, and the cycle time is 700 nanoseconds.
71
72 Once started by an SIO instruction, the channel executes I/O programs
73 independently of the CPU. Program words are read, and device status is
74 written back, directly via the port controller.
75
76 32-bit I/O program words are formed from a 16-bit I/O control word (IOCW) and
77 a 16-bit I/O address word (IOAW) in this general format:
78
79 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15
80 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
81 | C | order | X | control word 1/word count | IOCW
82 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
83 | control word 2/status/address | IOAW
84 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
85
86 Most orders are fully decoded by bits 1-3, but a few use bit 4 to extend the
87 definition where bits 4-15 are not otherwise used. I/O programs always
88 reside in memory bank 0. The current I/O program pointer resides in word 0
89 of the Device Reference Table entry for the active interface.
90
91 The Jump and Jump Conditional orders use this format:
92
93 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15
94 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
95 | - | 0 0 0 | C | - - - - - - - - - - - | IOCW
96 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
97 | jump target address | IOAW
98 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
99
100 ...where C is 0 for an unconditional jump and 1 for a conditional jump. An
101 unconditional jump is handled entirely within the channel. A conditional
102 jump asserts the SETJMP signal to the interface. If the interface returns
103 JMPMET, the jump will occur; otherwise, execution continues with the next
104 program word.
105
106 The Return Residue order uses this format:
107
108 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15
109 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
110 | - | 0 0 1 0 | - - - - - - - - - - - | IOCW
111 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
112 | residue of word count | IOAW
113 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
114
115 The remaining word count from the last transfer will be returned in the IOAW
116 as a two's-complement value. If the transfer completed normally, the
117 returned value will be zero.
118
119 The Set Bank order uses this format:
120
121 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15
122 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
123 | - | 0 0 1 1 | - - - - - - - - - - - | IOCW
124 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
125 | - - - - - - - - - - | * * : * * : bank | IOAW
126 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
127
128 The bank number occupies two bits in a Series II or four bits in a Series
129 III, although MPE-V/R can accommodate bank numbers up to six bits in length.
130 This establishes the memory bank to be used for subsequent Write or Read
131 orders. Program addresses always use bank 0.
132
133 The Interrupt order uses this format:
134
135 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15
136 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
137 | - | 0 1 0 | - - - - - - - - - - - - | IOCW
138 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
139 | - - - - - - - - - - - - - - - - | IOAW
140 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
141
142 The SETINT signal is asserted to the interface for this order.
143
144 The End and End with Interrupt orders use this format:
145
146 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15
147 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
148 | - | 0 1 1 | I | - - - - - - - - - - - | IOCW
149 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
150 | device status | IOAW
151 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
152
153 ...where I is 0 for an End and 1 for an End with Interrupt. The PSTATSTB
154 signal is asserted to the interface to obtain the device status, which is
155 stored in the IOAW location. If the I bit is set, SETINT will also be
156 asserted,
157
158 The Control order uses this format:
159
160 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15
161 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
162 | - | 1 0 0 | control word 1 | IOCW
163 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
164 | control word 2 | IOAW
165 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
166
167 Both control words are sent to the interface. The full IOCW containing
168 control word 1 is sent with the PCMD1 signal asserted. It is followed by the
169 IOAW with PCONTSTB asserted.
170
171 The Sense order uses this format:
172
173 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15
174 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
175 | - | 1 0 1 | - - - - - - - - - - - - | IOCW
176 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
177 | device status | IOAW
178 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
179
180 The PSTATSTB signal is asserted to the interface to obtain the device status,
181 which is stored in the IOAW location.
182
183 The Write and Read orders use these formats:
184
185 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15
186 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
187 | C | 1 1 0 | negative word count to write | IOCW
188 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
189 | C | 1 1 1 | negative word count to read | IOCW
190 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
191 | transfer address | IOAW
192 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
193
194 The C bit is the "data chain" flag. If it is set, then this transfer is a
195 continuation of a previous Write or Read transfer. This is used to
196 circumvent the transfer size limitation inherent in the 12-bit word count
197 allocated in the IOCW. For single transfers larger than 4K words, multiple
198 contiguous Write or Read orders are used, with all but the last order having
199 their data chain bits set.
200
201 In simulation, IOCW bits 1-4 are used to index into a 16-element lookup table
202 to produce the final I/O order (because some of the orders define IOCW bit 4
203 as "don't care", there are only thirteen distinct orders).
204
205 Channel-capable interfaces connect via the selector channel bus and request
206 channel service by asserting the CHANSR signal. An interface may initiate an
207 I/O program on the channel only if the channel is not busy with a transfer
208 involving another interface. The SIO instruction microcode tests status bit
209 0 ("SIO OK") from the interface before starting the I/O program. This bit
210 reflects the SIOENABLE signal from the channel, which is true only when the
211 channel is idle. If the channel is busy, the SIO instruction sets CCG and
212 returns without disturbing the channel.
213
214 The channel uses double-buffering for both data and I/O program words,
215 allowing concurrent channel/interface and channel/memory transfers.
216 Prefetching of the next I/O program word increases channel speed by reducing
217 the wait on memory transfers.
218
219 In simulation, an interface is implicitly connected to the selector channel
220 bus by calling the "sel_assert_REQ" routine. This initiates the transfer
221 between the device number of the interface and the channel. The
222 "service_request" field in the DIB is not used (it must be set to the
223 SRNO_UNUSED value).
224
225 The channel simulator provides these global objects:
226
227 t_bool sel_is_idle
228
229 TRUE if the selector channel is idle; FALSE otherwise. Corresponds to
230 the hardware SIOENABLE signal and reflects the value of the Selector
231 Active flip-flop. Used by device interfaces to qualify their SIO OK
232 status bits.
233
234 sel_assert_REQ (DIB *)
235
236 Called by the device interface while processing a DSTARTIO signal to
237 request that the selector channel begin an SIO operation, or called at
238 any time while the channel is active to abort the operation. Corresponds
239 to asserting the REQ signal. If the channel is idle, it initializes the
240 channel and starts the sequencer. If the channel is active, it aborts
241 the I/O program execution and idles the channel.
242
243 sel_assert_CHANSR (DIB *)
244
245 Called by the device controller to request service from the selector
246 channel asynchronously. Corresponds to asserting the CHANSR signal.
247 Typically called from a device service routine; device controller
248 interface routines return the CHANSR signal to request service
249 synchronously. Sets the service_request flag in the DIB and sets
250 sel_request.
251
252 t_bool sel_request
253
254 TRUE if an interface is requesting service from the selector channel or
255 the channel is servicing an internal request; FALSE otherwise.
256 Corresponds to the CHANSR signal received by the channel. Used by the
257 CPU to determine if a request is pending and the selector channel service
258 routine should be called.
259
260 sel_initialize (void)
261
262 Called in the instruction execution prelude to allow devices to be
263 reassigned or reset. If a device is under channel control, the routine
264 reestablishes the device number for the channel. It also sets
265 sel_request TRUE if the device has a service request pending or FALSE
266 otherwise.
267
268 sel_service (uint32)
269
270 Called to service a request from the device interface or an internal
271 request from the selector channel. Executes one or more channel cycles
272 for the associated interface. Used by the CPU to run the selector
273 channel.
274
275
276 Implementation notes:
277
278 1. In hardware, the installed memory size must be set with jumper S3 on the
279 Selector Channel Register PCA. In simulation, the size is determined by
280 using the MEMSIZE macro that tests the "capac" field of the CPU unit.
281
282 2. Multiple channels and interleaved memory operation and its associated
283 configuration jumpers are not supported.
284
285 3. The selectable trigger/freeze and error logging register features of the
286 Selector Channel Control PCA are not supported. Debug tracing may be
287 enabled to determine why an I/O program aborted.
288
289 3. The selector channel must execute more than one I/O order per CPU
290 instruction in order to meet the timing requirements of the diagnostic.
291 The timing is modeled by establishing a count of channel clock pulses at
292 poll entry and then executing orders until the count is exhausted. If
293 the clock count was exceeded, the excess count is saved and then
294 subtracted from the next entry's count, so that the typical execution
295 time is preserved over a number of entries.
296 */
297
298
299
300 #include "hp3000_defs.h"
301 #include "hp3000_cpu_ims.h"
302 #include "hp3000_io.h"
303 #include "hp3000_mem.h"
304
305
306
307 /* Program constants.
308
309 The selector channel clock period is 175 nanoseconds. The channel runs
310 concurrently with the CPU, which executes instructions in an average of 2.57
311 microseconds, so multiple cycles are executed per CPU instruction.
312
313 In simulation, the channel is called from the instruction execution loop
314 after every instruction, and sometimes additionally within instructions that
315 have long execution times (e.g., MOVE). The number of event ticks that have
316 elapsed since the last call are passed to the channel; this determines the
317 number of channel cycles to execute.
318
319
320 Implementation notes:
321
322 1. The number of cycles consumed by the channel for various operations are
323 educated guesses. There is no documentation available that details the
324 cycle timing.
325
326 2. In simulation, the Wait Sequence exists separately from the Transfer
327 Sequence only to avoid cancelling the SR wait timer for each word
328 transferred. It is reported as a Transfer Sequence cycle.
329 */
330
331 #define SR_WAIT_TIMER mS (1000) /* 1000 millisecond SR wait timer */
332
333 #define NS_PER_CYCLE 175 /* each clock cycle is 175 nanoseconds */
334
335 #define CYCLES_PER_FETCH 6
336 #define CYCLES_PER_PREFETCH 1
337 #define CYCLES_PER_EXECUTE 1
338 #define CYCLES_PER_RELOAD 3
339 #define CYCLES_PER_READ 4
340 #define CYCLES_PER_WRITE 4
341
342 #define CYCLES_PER_EVENT (uint32) (USEC_PER_EVENT * 1000 / NS_PER_CYCLE)
343
344 #define CNTR_MASK 0007777u /* word counter count mask */
345 #define CNTR_MAX 0007777u /* word counter maximum value */
346
347
348 typedef enum { /* selector channel sequencer state */
349 Idle_Sequence,
350 Fetch_Sequence,
351 Execute_Sequence,
352 Wait_Sequence,
353 Transfer_Sequence,
354 Reload_Sequence
355 } SEQ_STATE;
356
357 static const char *const seq_name [] = { /* indexed by SEQ_STATE */
358 "Idle",
359 "Fetch",
360 "Execute",
361 "Transfer", /* the wait sequence is reported as a transfer sequence */
362 "Transfer",
363 "Reload"
364 };
365
366 static const char *const action_name [] = { /* indexed by SEQ_STATE */
367 NULL, /* no loading occurs in the Idle_Sequence */
368 "loaded", /* loads occur in the Fetch_Sequence */
369 "prefetched", /* prefetches occur in the Execute_Sequence */
370 NULL, /* no loading occurs in the Wait_Sequence */
371 "prefetched", /* prefetches occur in the Transfer_Sequence */
372 "loaded" /* loads occur in the Reload_Sequence */
373 };
374
375
376 /* Debug flags */
377
378 #define DEB_CSRW (1u << 0) /* trace channel command initiations and completions */
379 #define DEB_PIO (1u << 1) /* trace programmed I/O commands */
380 #define DEB_STATE (1u << 2) /* trace state changes */
381 #define DEB_SR (1u << 3) /* trace service requests */
382
383
384 /* Memory access macros */
385
386 #define port_read_memory(c,o,v) mem_read (&sel_dev, c, o, v)
387 #define port_write_memory(c,o,v) mem_write (&sel_dev, c, o, v)
388
389
390 /* Channel global state */
391
392 t_bool sel_is_idle = TRUE; /* TRUE if the channel is idle */
393 t_bool sel_request = FALSE; /* TRUE if the channel sequencer is to be invoked */
394
395
396 /* Channel local state */
397
398 static SEQ_STATE sequencer = Idle_Sequence; /* the current sequencer execution state */
399 static SIO_ORDER order; /* the current SIO order */
400 static DIB *active_dib; /* a pointer to the participating interface's DIB */
401 static uint32 device_index; /* the index into the device table */
402 static t_bool prefetch_control; /* TRUE if the IOCW should be prefetched */
403 static t_bool prefetch_address; /* TRUE if the IOAW should be prefetched */
404
405 static uint32 device_number; /* the participating interface's device number */
406 static uint32 bank; /* the transfer bank register */
407 static uint32 word_count; /* the transfer word count register */
408
409 static HP_WORD program_counter; /* the I/O program counter */
410 static HP_WORD control_word; /* the current IOCW */
411 static HP_WORD control_buffer; /* the prefetched IOCW */
412 static HP_WORD address_word; /* the current IOAW */
413 static HP_WORD address_buffer; /* the prefetched IOAW */
414 static HP_WORD input_buffer; /* the input data word buffer */
415 static HP_WORD output_buffer; /* the output data word buffer */
416
417 static FLIP_FLOP rollover; /* SET if the transfer word count rolls over */
418 static int32 excess_cycles; /* the count of cycles in excess of allocation */
419
420
421 /* Channel local SCP support routines */
422
423 static t_stat sel_timer (UNIT *uptr);
424 static t_stat sel_reset (DEVICE *dptr);
425
426 /* Channel local utility routines */
427
428 static void end_channel (DIB *dibptr);
429 static SIGNALS_DATA abort_channel (const char *reason);
430 static void load_control (HP_WORD *value);
431 static void load_address (HP_WORD *value);
432
433
434 /* Channel SCP data structures */
435
436
437 /* Unit list */
438
439 static UNIT sel_unit [] = {
440 { UDATA (&sel_timer, 0, 0), SR_WAIT_TIMER }
441 };
442
443 /* Register list */
444
445 static REG sel_reg [] = {
446 /* Macro Name Location Width Offset Flags */
447 /* ------ ------ --------------- ----- ------ ----------------- */
448 { FLDATA (IDLE, sel_is_idle, 0) },
449 { FLDATA (SREQ, sel_request, 0) },
450 { DRDATA (DEVNO, device_number, 8), PV_LEFT },
451 { DRDATA (EXCESS, excess_cycles, 32), PV_LEFT },
452 { DRDATA (INDEX, device_index, 32), PV_LEFT | REG_HRO },
453
454 { DRDATA (SEQ, sequencer, 3) },
455 { ORDATA (ORDER, order, 4) },
456 { FLDATA (ROLOVR, rollover, 0) },
457 { FLDATA (PFCNTL, prefetch_control, 0) },
458 { FLDATA (PFADDR, prefetch_address, 0) },
459
460 { ORDATA (BANK, bank, 6), PV_LEFT },
461 { DRDATA (WCOUNT, word_count, 12) },
462
463 { ORDATA (PCNTR, program_counter, 16), },
464 { ORDATA (CNTL, control_word, 16), },
465 { ORDATA (CNBUF, control_buffer, 16), },
466 { ORDATA (ADDR, address_word, 16), },
467 { ORDATA (ADBUF, address_buffer, 16), },
468 { ORDATA (INBUF, input_buffer, 16), REG_X },
469 { ORDATA (OUTBUF, output_buffer, 16), REG_X },
470
471 { NULL }
472 };
473
474 /* Debugging trace list */
475
476 static DEBTAB sel_deb [] = {
477 { "CSRW", DEB_CSRW }, /* channel command initiations and completions */
478 { "PIO", DEB_PIO }, /* programmed I/O commands executed */
479 { "STATE", DEB_STATE }, /* channel state changes executed */
480 { "SR", DEB_SR }, /* service requests received */
481 { "DATA", DEB_MDATA }, /* I/O data accesses to memory */
482 { NULL, 0 }
483 };
484
485 /* Device descriptor */
486
487 DEVICE sel_dev = {
488 "SEL", /* device name */
489 sel_unit, /* unit array */
490 sel_reg, /* register array */
491 NULL, /* modifier array */
492 1, /* number of units */
493 8, /* address radix */
494 PA_WIDTH, /* address width */
495 1, /* address increment */
496 8, /* data radix */
497 16, /* data width */
498 NULL, /* examine routine */
499 NULL, /* deposit routine */
500 &sel_reset, /* reset routine */
501 NULL, /* boot routine */
502 NULL, /* attach routine */
503 NULL, /* detach routine */
504 NULL, /* device information block pointer */
505 DEV_DEBUG, /* device flags */
506 0, /* debug control flags */
507 sel_deb, /* debug flag name array */
508 NULL, /* memory size change routine */
509 NULL /* logical device name */
510 };
511
512
513
514 /* Channel global routines */
515
516
517
518 /* Initialize the channel.
519
520 This routine is called in the CPU instruction execution prelude to allow the
521 device number of the participating interface to be reassigned. It also sets
522 up the service request value from the device DIB. This allows the device
523 state to be changed during a simulation stop.
524
525 Implementation notes:
526
527 1. The active DIB pointer is restored from the device context to support
528 resuming after a SAVE and RESTORE is performed.
529
530 2. In simulation, we allow the device number to be changed during a
531 simulation stop, so this routine must recover it from the device.
532 Normally, the device number register would be reset from the device
533 number field in the DIB. However, the SCMB may be spoofing the device
534 number, and it is this spoofed number that must be restored. To do this,
535 we first assert the DEVNODB signal to the interface. The SCMB will
536 respond to the DEVNODB signal, as it supports connection to the
537 multiplexer channel. Devices that connect only to the selector channel
538 will not respond to DEVNODB, returning an outbound value of zero. In
539 this case, we use the DIB field to obtain the device number.
540 */
541
sel_initialize(void)542 void sel_initialize (void)
543 {
544 SIGNALS_DATA outbound;
545
546 if (sel_is_idle == FALSE) { /* if the channel is controlling a device */
547 active_dib = (DIB *) sim_devices [device_index]->ctxt; /* then restore the active DIB pointer */
548
549 outbound = active_dib->io_interface (active_dib, DEVNODB, 0); /* see if the device responds to DEVNODB */
550
551 if (IODATA (outbound) > 0) /* if it does (e.g., the SCMB) */
552 device_number = IODATA (outbound) / 4; /* then use the returned device number */
553 else /* otherwise */
554 device_number = active_dib->device_number; /* use the device number from the DIB */
555
556 sel_request = active_dib->service_request; /* restore the service request state */
557 }
558
559 return;
560 }
561
562
563 /* Start an I/O program.
564
565 This routine is called by a device interface in response to a Start I/O (SIO)
566 instruction to request that the selector channel begin an I/O program. It
567 corresponds in hardware to asserting the REQ signal.
568
569 If REQ is asserted while the channel is servicing the interface, the channel
570 aborts the transfer. This occurs when an interface decides to terminate a
571 transfer, for example when an error retry count has expired or a device has
572 become not ready.
573
574
575 Implementation notes:
576
577 1. Both the HP 3000 Series II/III System Reference Manual and the HP 3000
578 Series III Reference/Training manuals say that the selector channel
579 asserts a DEVNODB signal as part of the REQ processing. This is
580 incorrect; the DEVNODB line is tied inactive by the channel, per the
581 Selector Channel Control PCA schematic. Instead, the channel expects the
582 device number, multiplied by four, to be present on the SRn bus during
583 REQ signal assertion, when it is loaded into the device number register.
584 Selector channel devices gate their device numbers onto SR6-13 when an
585 SIO instruction is decoded.
586 */
587
sel_assert_REQ(DIB * dibptr)588 void sel_assert_REQ (DIB *dibptr)
589 {
590 if (sel_is_idle) { /* if the channel is idle then set it up */
591 tprintf (sel_dev, DEB_CSRW, "Device number %u asserted REQ for channel initialization\n",
592 dibptr->device_number);
593
594 sel_is_idle = FALSE; /* the channel is now busy */
595 sel_request = TRUE; /* set the request flag */
596
597 sequencer = Fetch_Sequence; /* initialize the sequencer */
598 bank = 0; /* set the bank to bank 0 */
599
600 word_count = 0; /* clear the word counter */
601 rollover = CLEAR; /* and the word count rollover flip-flop */
602 excess_cycles = 0; /* clear the excess cycle count */
603
604 device_index = 0; /* find the device index */
605 /* corresponding to */
606 while ((DIB *) sim_devices [device_index]->ctxt != dibptr) /* the active DIB pointer */
607 device_index = device_index + 1; /* to aid later restoration */
608
609 active_dib = dibptr; /* save the interface's DIB pointer */
610 device_number = dibptr->device_number; /* and set the device number register */
611
612 port_read_memory (absolute, device_number * 4, /* read the initial program counter from the DRT */
613 &program_counter);
614 }
615
616 else { /* otherwise abort the transfer in progress */
617 tprintf (sel_dev, DEB_CSRW, "Device number %u asserted REQ for channel abort\n",
618 device_number);
619
620 end_channel (dibptr); /* idle the channel */
621 sim_cancel (&sel_unit [0]); /* and cancel the CHANSR timer */
622 }
623
624 return;
625 }
626
627
628 /* Request channel service.
629
630 This routine is called by a device interface to request service from the
631 channel. It is called either directly by the interface or indirectly by the
632 channel in response to a CHANSR signal returned by the interface. A direct
633 call is needed for asynchronous assertion, e.g., in response to an event
634 service call. Synchronous assertion, i.e., in response to an interface call,
635 is made by returning the CHANSR to the channel. The routine corresponds in
636 hardware to asserting the CHANSR signal on the selector channel bus.
637
638 Sets the service_request flag in the DIB and sets the sel_request flag to
639 cause the channel sequencer to be invoked.
640 */
641
sel_assert_CHANSR(DIB * dibptr)642 void sel_assert_CHANSR (DIB *dibptr)
643 {
644 tprintf (sel_dev, DEB_SR, "Device number %u asserted CHANSR\n",
645 device_number);
646
647 dibptr->service_request = TRUE; /* set the service request flag in the interface */
648 sel_request = TRUE; /* and the selector request flag */
649
650 return;
651 }
652
653
654 /* Invoke the channel sequencer in response to a service request.
655
656 This routine is called in the CPU instruction execution loop to service a
657 channel request, asserted either by the participating interface, or
658 generated internally by the channel. It executes one or more channel cycles
659 for the associated device interface and resets the service request flag in
660 the DIB before exiting. The routine is called after every instruction, and
661 sometimes additionally within instructions that have long execution times
662 (e.g., MOVE). The number of event ticks that have elapsed since the last
663 call are passed in; this determines the number of channel cycles available to
664 execute.
665
666 The selector channel clock period is 175 nanoseconds. The channel runs
667 concurrently with the CPU, which executes instructions in an average of 2.57
668 microseconds, so multiple cycles are executed per CPU instruction.
669
670 On entry, the routine executes the next state in the transfer for the
671 currently participating interface. The number of channel clock counts
672 consumed for the specified state execution is subtracted from the number of
673 clock counts available. If more time remains, and the service request is
674 still active, another channel cycle is run for the interface.
675
676 The actions for the orders are:
677
678 Transfer Last
679 SIO Order State Type Word Signals Asserted
680 --------- -------- -------- ---- -------------------------------
681 sioJUMP Execute -- -- (none)
682
683 sioJUMPC Execute -- -- SETJMP
684
685 sioRTRES Execute -- -- (none)
686
687 sioSBANK Execute -- -- (none)
688
689 sioINTRP Execute -- -- SETINT
690
691 sioEND Execute -- -- TOGGLESIOOK | PSTATSTB
692
693 sioENDIN Execute -- -- TOGGLESIOOK | PSTATSTB | SETINT
694
695 sioCNTL Execute -- -- PCMD1 | CHANSO
696 " Transfer -- -- PCONTSTB
697
698 sioSENSE Execute -- -- PSTATSTB
699
700 sioWRITE Execute -- -- TOGGLEOUTXFER
701 Transfer Normal No PWRITESTB
702 Transfer Normal Yes PWRITESTB | EOT
703 Transfer DEVEND No EOT | TOGGLEOUTXFER
704 Transfer DEVEND Yes (none)
705
706 sioWRITEC Execute -- -- TOGGLEOUTXFER
707 Transfer Normal No PWRITESTB
708 Transfer Normal Yes PWRITESTB | EOT | TOGGLEOUTXFER
709 Transfer DEVEND No EOT
710 Transfer DEVEND Yes (none)
711
712 sioREAD Execute -- -- TOGGLEINXFER | READNEXTWD
713 Transfer Normal No PREADSTB | READNEXTWD
714 Transfer Normal Yes PREADSTB | EOT | READNEXTWD
715 Transfer Devend No EOT | TOGGLEINXFER
716 Transfer DEVEND Yes (none)
717
718 sioREADC Execute -- -- TOGGLEINXFER | READNEXTWD
719 Transfer Normal No PREADSTB | READNEXTWD
720 Transfer Normal Yes PREADSTB | EOT | TOGGLEINXFER
721 Transfer Devend No EOT
722 Transfer DEVEND Yes (none)
723
724 A fundamental difference between the multiplexer and selector channels is
725 that the latter needs an external service request (i.e., CHANSR assertion)
726 only for operations on the interface. All other channel operations apply an
727 internal service request and so occur automatically without CHANSR being
728 asserted. In simulation, sel_request is set TRUE during channel
729 initialization and is only cleared when the channel is waiting for a response
730 from the interface during a control, read, or write operation. The following
731 signal assertions to the interface must return CHANSR to permit the channel
732 sequencer to advance:
733
734 - PCMD1
735 - PCONTSTB
736 - TOGGLEINXFER | READNEXTWD
737 - PREADSTB
738 - TOGGLEOUTXFER
739 - PWRITESTB
740
741 Because the channel is dedicated to an interface for the duration of a
742 transfer, a non-responding interface would tie up the channel forever. To
743 prevent this, the channel starts a one-millisecond timer whenever it is
744 waiting for the interface to assert CHANSR. If the timer expires, the
745 transfer is aborted, and the channel is freed. The channel also checks for
746 CHANACK in response to CHANSO assertion to the interface and will terminate
747 (but not abort) the transfer if the interface fails to return it.
748
749 To maintain the maximum transfer rate across chained read or write transfers,
750 the channel will attempt to prefetch the next set of I/O Control and Address
751 words during the current data transfer. The two memory reads are interleaved
752 between successive channel data transfers, but only if the input or output
753 data buffers are both empty (read) or full (write), respectively. This will
754 normally occur unless the device is using all available channel bandwidth;
755 the SCMB in high speed mode is an example of a device that asserts SR
756 continuously.
757
758 The selector channel diagnostic checks for the expected prefetching. With
759 the SCMB in slow mode, both the control and address prefetches will occur
760 within three (read) or five (write) I/O cycles. In fast mode, prefetches are
761 locked out during a write operation, and only the control word prefetch
762 occurs during a read operation.
763
764
765 Implementation notes:
766
767 1. Conceptually, the selector channel has three internal states: initiate,
768 fetch, and execute. The initiator sequence begins with a REQ
769 assertion from the interface and sets up the I/O program for execution.
770 The fetch sequence obtains the IOCW and IOAW. The execute sequence
771 generates the signals needed for each I/O order.
772
773 In hardware, the Selector Channel Sequencer PCA contains several state
774 machines (initiator, fetch, prefetch, buffer transfer, etc.) that provide
775 substates. In simulation, the prefetch, transfer, and reload actions are
776 given separate states, rather than making them substates of the execute
777 state.
778
779 2. In hardware, a ten-microsecond CHANACK timer is started when CHANSO is
780 asserted to the interface. In simulation, a timer is not needed;
781 instead, the interface must return CHANACK to avoid a CHANACK timeout
782 error.
783
784 3. In hardware, the CHANACK and CHANSR timers run on every channel cycle.
785 In simulation, CHANACK is tested only during a read or write transfer,
786 and CHANSR is tested only at the beginning of a read or write transfer,
787 and at the beginning and end of a control transfer. This limits overhead
788 while passing the diagnostic and providing some measure of protection.
789
790 4. In hardware, there are two input and two output buffers. This enables
791 memory transfers to overlap with interface data transfers. In
792 simulation, only one of each buffer is implemented, and memory transfers
793 occur synchronously with interface transfers.
794
795 5. In hardware, prefetches of the IOCW and IOAW are interleaved with channel
796 memory accesses and only occur when the port controller is idle. In
797 simulation, prefetches are not counted against the sequencer execution
798 time. Normal fetches, by contrast, wait for memory access and so the
799 time taken is counted.
800
801 6. The default label in the Execute Sequence switch statement is necessary
802 to quiet a warning that inbound_signals may be used uninitialized, even
803 though all cases are covered.
804 */
805
sel_service(uint32 ticks_elapsed)806 void sel_service (uint32 ticks_elapsed)
807 {
808 HP_WORD inbound_data, outbound_data;
809 INBOUND_SET inbound_signals;
810 SIGNALS_DATA outbound;
811 int32 cycles;
812 uint32 return_address;
813
814 cycles = CYCLES_PER_EVENT - excess_cycles; /* decrease the cycles available by any left over */
815
816 while (sel_request && cycles > 0) { /* execute as long as a request and cycles remain */
817 outbound = IORETURN (NO_SIGNALS, 0); /* initialize in case we don't call the interface */
818
819 tprintf (sel_dev, DEB_STATE, "Channel entered the %s sequence with %d clock cycles remaining\n",
820 seq_name [sequencer], cycles);
821
822 switch (sequencer) { /* dispatch based on the selector state */
823
824 case Idle_Sequence: /* if the selector is idle */
825 sel_request = FALSE; /* then the request is invalid */
826 break;
827
828
829 case Fetch_Sequence:
830 sim_cancel (&sel_unit [0]); /* cancel the CHANSR timer */
831
832 load_control (&control_word); /* load the IOCW */
833 load_address (&address_word); /* and the IOAW */
834 cycles = cycles - 2 * CYCLES_PER_READ /* and count the accesses */
835 - CYCLES_PER_FETCH; /* and the fetch sequence */
836
837 order = IOCW_ORDER (control_word); /* save the current order */
838
839 if (control_word & IOCW_DC /* if the data chain bit is set */
840 && order != sioREADC && order != sioWRITEC) /* but the order isn't a chained order */
841 outbound = abort_channel ("an illegal order"); /* then abort the channel program */
842
843 else /* otherwise the order is valid */
844 sequencer = Execute_Sequence; /* and execution is next */
845 break;
846
847
848 case Execute_Sequence:
849 switch (order) { /* dispatch based on the I/O order */
850
851 case sioJUMPC:
852 inbound_signals = SETJMP | CHANSO;
853 break;
854
855 case sioRTRES:
856 inbound_signals = NO_SIGNALS; /* no interface call is needed */
857
858 if (rollover == SET) /* if the count terminated */
859 outbound = IORETURN (NO_SIGNALS, 0); /* then return a zero count */
860 else /* otherwise return the two's-complement remainder */
861 outbound = IORETURN (NO_SIGNALS,
862 IOCW_COUNT (word_count));
863 break;
864
865 case sioINTRP:
866 inbound_signals = SETINT | CHANSO;
867 break;
868
869 case sioEND:
870 inbound_signals = TOGGLESIOOK | PSTATSTB | CHANSO;
871 break;
872
873 case sioENDIN:
874 inbound_signals = TOGGLESIOOK | PSTATSTB | SETINT | CHANSO;
875 break;
876
877 case sioCNTL:
878 inbound_signals = PCMD1 | CHANSO;
879
880 sel_request = FALSE; /* wait until the interface requests the next word */
881 break;
882
883 case sioSENSE:
884 inbound_signals = PSTATSTB | CHANSO;
885 break;
886
887 case sioWRITE:
888 case sioWRITEC:
889 inbound_signals = TOGGLEOUTXFER | CHANSO;
890
891 word_count = IOCW_WCNT (control_word); /* load the word count */
892 sel_request = FALSE; /* wait until the interface requests the next word */
893 break;
894
895 case sioREAD:
896 case sioREADC:
897 inbound_signals = TOGGLEINXFER | READNEXTWD | CHANSO;
898
899 word_count = IOCW_WCNT (control_word); /* load the word count */
900 sel_request = FALSE; /* wait until the interface requests the next word */
901 break;
902
903 default: /* needed to quiet warning about inbound_signals */
904 case sioJUMP: /* these orders do not need */
905 case sioSBANK: /* to call the interface */
906 inbound_signals = NO_SIGNALS;
907 break;
908 } /* end switch */
909
910 if (inbound_signals) { /* if there are signals to assert */
911 outbound = active_dib->io_interface (active_dib, /* then pass them to the interface */
912 inbound_signals,
913 control_word);
914
915 if ((outbound & CHANACK) == NO_SIGNALS) { /* if CHANACK was not returned */
916 tprintf (sel_dev, DEB_SR, "Device number %u CHANACK timeout\n",
917 device_number);
918
919 end_channel (active_dib); /* terminate the channel program */
920
921 tprintf (sel_dev, DEB_CSRW, "Channel program ended\n");
922 break;
923 }
924 }
925
926 switch (order) { /* dispatch based on the I/O order */
927
928 case sioJUMP:
929 program_counter = address_word; /* load the program counter with the new address */
930 sequencer = Fetch_Sequence; /* next state is Fetch */
931 break;
932
933 case sioJUMPC:
934 if (outbound & JMPMET) /* if the jump condition is true */
935 program_counter = address_word; /* then load the program counter with the new address */
936
937 sequencer = Fetch_Sequence; /* the next state is Fetch */
938 break;
939
940 case sioRTRES:
941 case sioEND:
942 case sioENDIN:
943 case sioSENSE:
944 outbound_data = IODATA (outbound); /* get the status or residue to return */
945 return_address = program_counter - 1 & LA_MASK; /* point at the second of the program words */
946
947 port_write_memory (absolute, return_address, outbound_data); /* save the word */
948 cycles = cycles - CYCLES_PER_WRITE; /* and count the access */
949
950 tprintf (sel_dev, DEB_PIO, "Channel stored IOAW %06o to address %06o\n",
951 outbound_data, return_address);
952
953 if (order == sioEND || order == sioENDIN) { /* if it's an End or End with Interrupt order */
954 end_channel (active_dib); /* then terminate the program */
955
956 tprintf (sel_dev, DEB_CSRW, "Channel program ended\n");
957 }
958
959 else /* otherwise the program continues */
960 sequencer = Fetch_Sequence; /* with the fetch state */
961 break;
962
963 case sioSBANK:
964 bank = IOAW_BANK (address_word); /* set the bank number register */
965 sequencer = Fetch_Sequence; /* the next state is Fetch */
966 break;
967
968 case sioINTRP:
969 sequencer = Fetch_Sequence; /* the next state is Fetch */
970 break;
971
972 case sioCNTL:
973 prefetch_control = FALSE; /* prefetching is not used */
974 prefetch_address = FALSE; /* for the Control order */
975
976 sim_activate (&sel_unit [0], sel_unit [0].wait); /* start the SR timer */
977 sequencer = Wait_Sequence; /* and check for a timeout */
978 break;
979
980 case sioWRITE:
981 case sioWRITEC:
982 prefetch_control = (order == sioWRITEC); /* enable prefetching */
983 prefetch_address = (order == sioWRITEC); /* if the order is chained */
984
985 sim_activate (&sel_unit [0], sel_unit [0].wait); /* start the SR timer */
986 sequencer = Wait_Sequence; /* and check for a timeout */
987 break;
988
989 case sioREAD:
990 case sioREADC:
991 prefetch_control = (order == sioREADC); /* enable prefetching */
992 prefetch_address = (order == sioREADC); /* if the order is chained */
993
994 if (prefetch_control) { /* if control word prefetching is enabled */
995 load_control (&control_buffer); /* then prefetch the next IOCW into the buffer */
996 cycles = cycles - CYCLES_PER_PREFETCH; /* and count the sequencer time */
997 prefetch_control = FALSE; /* mark the job done */
998 }
999
1000 sim_activate (&sel_unit [0], sel_unit [0].wait); /* start the SR timer */
1001 sequencer = Wait_Sequence; /* and check for a timeout */
1002 break;
1003 } /* end switch */
1004
1005 cycles = cycles - CYCLES_PER_EXECUTE; /* count the sequencer time */
1006 break;
1007
1008
1009 case Wait_Sequence:
1010 sim_cancel (&sel_unit [0]); /* cancel the SR timer */
1011
1012 sequencer = Transfer_Sequence; /* continue with the transfer sequence */
1013
1014 /* fall through into the Transfer_Sequence */
1015
1016
1017 case Transfer_Sequence:
1018 if (order == sioCNTL) { /* if this is a Control order */
1019 inbound_data = address_word; /* then supply the control word */
1020 inbound_signals = PCONTSTB | CHANSO; /* to the interface */
1021 sel_request = FALSE; /* wait until the interface confirms receipt */
1022 }
1023
1024 else if (order == sioREAD || order == sioREADC) { /* otherwise if this is a Read or Read Chained order */
1025 inbound_data = 0; /* then no value is needed */
1026 inbound_signals = PREADSTB | CHANSO; /* by the interface */
1027
1028 if (word_count == CNTR_MAX) /* if the word count is exhausted */
1029 if (order == sioREADC) /* then if the order is chained */
1030 inbound_signals |= EOT | READNEXTWD; /* then continue the transfer block */
1031 else /* otherwise */
1032 inbound_signals |= EOT | TOGGLEINXFER; /* end the transfer block */
1033
1034 else /* otherwise the transfer continues */
1035 inbound_signals |= READNEXTWD; /* with the next word */
1036
1037 sel_request = FALSE; /* wait until the interface confirms receipt */
1038 }
1039
1040 else { /* otherwise it's a Write or Write Chained order */
1041 if (port_read_memory (dma, /* if the memory read */
1042 TO_PA (bank, address_word), /* from the specified bank and offset */
1043 &input_buffer)) { /* succeeds */
1044 cycles = cycles - CYCLES_PER_READ; /* then count the access */
1045
1046 inbound_data = input_buffer; /* get the word to supply */
1047 inbound_signals = PWRITESTB | CHANSO; /* to the interface */
1048
1049 if (word_count == CNTR_MAX) /* if the word count is exhausted */
1050 if (order == sioWRITEC) /* then if the order is chained */
1051 inbound_signals |= EOT; /* then continue the transfer block */
1052 else /* otherwise */
1053 inbound_signals |= EOT | TOGGLEOUTXFER; /* end the transfer block */
1054
1055 sel_request = FALSE; /* wait until the interface confirms receipt */
1056 }
1057
1058 else { /* otherwise the memory read failed */
1059 outbound = abort_channel ("a memory read error"); /* so abort the transfer */
1060 break; /* and skip the interface call */
1061 }
1062 }
1063
1064 cycles = cycles - CYCLES_PER_EXECUTE; /* count the sequencer time */
1065
1066 outbound = active_dib->io_interface (active_dib, inbound_signals, inbound_data); /* call the interface */
1067
1068 if (sel_is_idle) /* if the interface aborted the transfer */
1069 break; /* then terminate processing now */
1070
1071 if ((outbound & CHANSR) == NO_SIGNALS) /* if the interface did not assert a service request */
1072 if (prefetch_control) { /* then if control word prefetching is enabled */
1073 load_control (&control_buffer); /* then prefetch the next IOCW into the buffer */
1074 cycles = cycles - CYCLES_PER_PREFETCH; /* and count the sequencer time */
1075 prefetch_control = FALSE; /* mark the job done */
1076 }
1077
1078 else if (prefetch_address) { /* otherwise if address word prefetching is enabled */
1079 load_address (&address_buffer); /* then prefetch the next IOAW into the buffer */
1080 cycles = cycles - CYCLES_PER_PREFETCH; /* and count the sequencer time */
1081 prefetch_address = FALSE; /* mark the job done */
1082 }
1083
1084 if (order == sioCNTL) { /* if this is a Control order */
1085 sim_activate (&sel_unit [0], sel_unit [0].wait); /* then start the SR timer */
1086 sequencer = Fetch_Sequence; /* and the next state is Fetch */
1087 }
1088
1089 else { /* otherwise it's a Write or Read (Chained) order */
1090 if (outbound & DEVEND) { /* if the device ended the transfer */
1091 if (word_count < CNTR_MAX) { /* then if the transfer is incomplete */
1092 inbound_signals = EOT | CHANSO; /* then assert EOT to end the transfer */
1093
1094 if (order == sioREAD) /* if the order is Read and not chained */
1095 inbound_signals |= TOGGLEINXFER; /* then terminate the input block */
1096
1097 else if (order == sioWRITE) /* otherwise if the order is Write and not chained */
1098 inbound_signals |= TOGGLEOUTXFER; /* then terminate the output block */
1099
1100 active_dib->io_interface (active_dib, inbound_signals, 0); /* tell the interface */
1101 }
1102
1103 sequencer = Reload_Sequence; /* the next state is Reload */
1104 }
1105
1106 else if (order == sioREAD /* otherwise the transfer was successful */
1107 || order == sioREADC) { /* and if this is a Read or Read Chained order */
1108 output_buffer = IODATA (outbound); /* then pick up the returned data word */
1109
1110 if (port_write_memory (dma, /* if the memory write */
1111 TO_PA (bank, address_word), /* to the specified bank and offset */
1112 output_buffer)) /* succeeds */
1113 cycles = cycles - CYCLES_PER_WRITE; /* then count the access */
1114
1115 else { /* otherwise the memory write failed */
1116 outbound = abort_channel ("a memory write error"); /* so abort the transfer */
1117 break; /* and skip the address and count update */
1118 }
1119 }
1120
1121 address_word = address_word + 1 & LA_MASK; /* increment the transfer address */
1122 word_count = word_count + 1 & CNTR_MASK; /* and the word count */
1123
1124 if (word_count == 0) { /* if the word count is exhausted */
1125 rollover = SET; /* then set the rollover flip-flop */
1126 sequencer = Reload_Sequence; /* and load the next I/O program word */
1127 }
1128 }
1129
1130 break;
1131
1132
1133 case Reload_Sequence:
1134 if (order == sioWRITEC || order == sioREADC) { /* if the current order is chained */
1135 if (prefetch_control) { /* and the IOCW has not been prefetched yet */
1136 load_control (&control_buffer); /* then load it now */
1137 cycles = cycles - CYCLES_PER_READ; /* and count the memory access */
1138 }
1139
1140 if (prefetch_address) { /* if the IOAW has not be prefetched yet */
1141 load_address (&address_buffer); /* then load it now */
1142 cycles = cycles - CYCLES_PER_READ; /* and count the memory access */
1143 }
1144
1145 if (prefetch_control || prefetch_address) /* if both words had not been prefetched */
1146 cycles = cycles - CYCLES_PER_FETCH; /* then count as a fetch sequence */
1147 else /* otherwise */
1148 cycles = cycles - CYCLES_PER_RELOAD; /* count as a reload sequence */
1149
1150 if ((control_word ^ control_buffer) & IOCW_SIO_MASK) /* if the next order isn't the same type */
1151 outbound = abort_channel ("an invalid chained order"); /* then an invalid order abort occurs */
1152
1153 else { /* otherwise the next order is OK */
1154 control_word = control_buffer; /* so copy the control and address values */
1155 address_word = address_buffer; /* from the buffers */
1156
1157 order = IOCW_ORDER (control_word); /* get the new order */
1158 word_count = IOCW_WCNT (control_word); /* and word count */
1159
1160 rollover = CLEAR; /* clear the word count rollover flip-flop */
1161
1162 prefetch_control = (control_word & IOCW_DC) != 0; /* enable prefetching */
1163 prefetch_address = (control_word & IOCW_DC) != 0; /* if the new order is chained */
1164
1165 sequencer = Transfer_Sequence; /* the next state is Transfer */
1166 }
1167 }
1168
1169 else /* otherwise an unchained order ends the transfer */
1170 sequencer = Fetch_Sequence; /* so proceed directly to Fetch */
1171
1172 break;
1173 } /* end switch */
1174
1175
1176 if (outbound & INTREQ) /* if an interrupt request was asserted */
1177 iop_assert_INTREQ (active_dib); /* then set it up */
1178
1179 if (sel_is_idle == FALSE) /* if the channel is still running */
1180 if (outbound & CHANSR) /* then if the interface requested service */
1181 sel_assert_CHANSR (active_dib); /* then set it up */
1182 else /* otherwise */
1183 active_dib->service_request = FALSE; /* clear the current service request */
1184
1185 else /* otherwise the channel has stopped */
1186 sim_cancel (&sel_unit [0]); /* so cancel the CHANSR timer */
1187
1188 } /* end while */
1189
1190
1191 if (cycles > 0) /* if we exited to wait for a service request */
1192 excess_cycles = 0; /* then do a full set of cycles next time */
1193 else /* otherwise we ran over our allotment */
1194 excess_cycles = - cycles; /* so reduce the next poll by the overage */
1195
1196 return;
1197 }
1198
1199
1200
1201 /* Channel local SCP support routines */
1202
1203
1204
1205 /* Service the channel service request timer.
1206
1207 The CHANSR timer is started whenever the channel is waiting for a service
1208 request from the participating interface. Because the selector channel is
1209 dedicated to a single interface until the end of the I/O program, if that
1210 interface were to malfunction and not respond, the channel would be tied up
1211 forever.
1212
1213 Normally, the timer is cancelled as soon as CHANSR is returned from the
1214 interface. If this service routine is entered, it means that CHANSR is
1215 taking too long, so the I/O program is aborted, and the channel is idled, so
1216 that it is available for other devices.
1217 */
1218
sel_timer(UNIT * uptr)1219 static t_stat sel_timer (UNIT *uptr)
1220 {
1221 SIGNALS_DATA outbound;
1222
1223 outbound = abort_channel ("a CHANSR timeout"); /* abort the transfer in progress */
1224
1225 if (outbound & INTREQ) /* if an interrupt request was asserted */
1226 iop_assert_INTREQ (active_dib); /* then set it up */
1227
1228 return SCPE_OK;
1229 }
1230
1231
1232 /* Device reset.
1233
1234 This routine is called for a RESET or RESET SEL command. It is the
1235 simulation equivalent of the IORESET signal, which is asserted by the front
1236 panel LOAD and DUMP switches.
1237
1238 For this interface, IORESET is identical to the internal Clear Logic signal.
1239
1240 A reset does not clear any of the registers.
1241 */
1242
sel_reset(DEVICE * dptr)1243 static t_stat sel_reset (DEVICE *dptr)
1244 {
1245 rollover = CLEAR; /* clear the word count rollover flip-flop */
1246
1247 sel_is_idle = TRUE; /* the channel is now inactive */
1248 sel_request = FALSE; /* clear the request flag */
1249
1250 sequencer = Idle_Sequence; /* stop the sequencer */
1251
1252 return SCPE_OK;
1253 }
1254
1255
1256
1257 /* Channel local utility routines */
1258
1259
1260
1261 /* End the channel I/O program.
1262
1263 The channel program ends, either normally via an sioEND or sioENDIN order, or
1264 abnormally via a REQ or timeout abort. The program counter is written back
1265 to the DRT, and the channel is idled by performing a Clear Logic operation.
1266
1267
1268 Implementation notes:
1269
1270 1. The memory write cycle time need not be counted, as the channel will be
1271 terminating unconditionally.
1272 */
1273
end_channel(DIB * dibptr)1274 static void end_channel (DIB *dibptr)
1275 {
1276 port_write_memory (absolute, device_number * 4, /* write the program counter back to the DRT */
1277 program_counter);
1278
1279 dibptr->service_request = FALSE; /* clear any outstanding device service request */
1280
1281 sel_reset (&sel_dev); /* perform a Clear Logic operation */
1282
1283 return;
1284 }
1285
1286
1287 /* Abort the transfer in progress.
1288
1289 If an internal channel error occurs (e.g., a memory read or write failure,
1290 due to an invalid address), the channel asserts the XFERERROR signal to the
1291 interface. The interface will clear its logic and assert REQ to the channel
1292 to complete the abort.
1293 */
1294
abort_channel(const char * reason)1295 static SIGNALS_DATA abort_channel (const char *reason)
1296 {
1297 tprintf (sel_dev, DEB_CSRW, "Channel asserted XFERERROR for %s\n",
1298 reason);
1299
1300 return active_dib->io_interface (active_dib, XFERERROR | CHANSO, 0); /* tell the interface that the channel has aborted */
1301 }
1302
1303
1304 /* Load the I/O Control Word.
1305
1306 The first of the two I/O program words is loaded into the channel register
1307 pointed to by "value". The program counter points at the location to read
1308 and is incremented after retrieving the value. This routine is called both
1309 for a normal fetch and for a prefetch.
1310 */
1311
load_control(HP_WORD * value)1312 static void load_control (HP_WORD *value)
1313 {
1314 port_read_memory (absolute, program_counter, value); /* read the IOCW from memory */
1315
1316 tprintf (sel_dev, DEB_PIO, "Channel %s IOCW %06o (%s) from address %06o\n",
1317 action_name [sequencer], *value,
1318 sio_order_name [IOCW_ORDER (*value)], program_counter);
1319
1320 program_counter = program_counter + 1 & LA_MASK; /* increment the program counter */
1321
1322 return;
1323 }
1324
1325
1326 /* Load the I/O Address Word.
1327
1328 The second of the two I/O program words is loaded into the channel register
1329 pointed to by "value". The program counter points at the location to read
1330 and is incremented after retrieving the value. This routine is called both
1331 for a normal fetch and for a prefetch.
1332 */
1333
load_address(HP_WORD * value)1334 static void load_address (HP_WORD *value)
1335 {
1336 port_read_memory (absolute, program_counter, value); /* read the IOAW from memory */
1337
1338 tprintf (sel_dev, DEB_PIO, "Channel %s IOAW %06o from address %06o\n",
1339 action_name [sequencer], *value, program_counter);
1340
1341 program_counter = program_counter + 1 & LA_MASK; /* increment the program counter */
1342
1343 return;
1344 }
1345