1 /*
2 * ARM virtual CPU header
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #ifndef CPU_ARM_H
20 #define CPU_ARM_H
21
22 #include "config.h"
23
24 #include "kvm-consts.h"
25
26 #if defined(TARGET_AARCH64)
27 /* AArch64 definitions */
28 # define TARGET_LONG_BITS 64
29 # define ELF_MACHINE EM_AARCH64
30 #else
31 # define TARGET_LONG_BITS 32
32 # define ELF_MACHINE EM_ARM
33 #endif
34
35 #define CPUArchState struct CPUARMState
36
37 #include "qemu-common.h"
38 #include "exec/cpu-defs.h"
39
40 #include "fpu/softfloat.h"
41
42 #define TARGET_HAS_ICE 1
43
44 #define EXCP_UDEF 1 /* undefined instruction */
45 #define EXCP_SWI 2 /* software interrupt */
46 #define EXCP_PREFETCH_ABORT 3
47 #define EXCP_DATA_ABORT 4
48 #define EXCP_IRQ 5
49 #define EXCP_FIQ 6
50 #define EXCP_BKPT 7
51 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */
52 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */
53 #define EXCP_STREX 10
54 #define EXCP_HVC 11 /* HyperVisor Call */
55 #define EXCP_HYP_TRAP 12
56 #define EXCP_SMC 13 /* Secure Monitor Call */
57 #define EXCP_VIRQ 14
58 #define EXCP_VFIQ 15
59
60 #define ARMV7M_EXCP_RESET 1
61 #define ARMV7M_EXCP_NMI 2
62 #define ARMV7M_EXCP_HARD 3
63 #define ARMV7M_EXCP_MEM 4
64 #define ARMV7M_EXCP_BUS 5
65 #define ARMV7M_EXCP_USAGE 6
66 #define ARMV7M_EXCP_SVC 11
67 #define ARMV7M_EXCP_DEBUG 12
68 #define ARMV7M_EXCP_PENDSV 14
69 #define ARMV7M_EXCP_SYSTICK 15
70
71 /* ARM-specific interrupt pending bits. */
72 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1
73 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2
74 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3
75
76 /* The usual mapping for an AArch64 system register to its AArch32
77 * counterpart is for the 32 bit world to have access to the lower
78 * half only (with writes leaving the upper half untouched). It's
79 * therefore useful to be able to pass TCG the offset of the least
80 * significant half of a uint64_t struct member.
81 */
82 #ifdef HOST_WORDS_BIGENDIAN
83 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t))
84 #define offsetofhigh32(S, M) offsetof(S, M)
85 #else
86 #define offsetoflow32(S, M) offsetof(S, M)
87 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t))
88 #endif
89
90 /* Meanings of the ARMCPU object's four inbound GPIO lines */
91 #define ARM_CPU_IRQ 0
92 #define ARM_CPU_FIQ 1
93 #define ARM_CPU_VIRQ 2
94 #define ARM_CPU_VFIQ 3
95
96 typedef void ARMWriteCPFunc(void *opaque, int cp_info,
97 int srcreg, int operand, uint32_t value);
98 typedef uint32_t ARMReadCPFunc(void *opaque, int cp_info,
99 int dstreg, int operand);
100
101 struct arm_boot_info;
102
103 #define NB_MMU_MODES 4
104
105 /* We currently assume float and double are IEEE single and double
106 precision respectively.
107 Doing runtime conversions is tricky because VFP registers may contain
108 integer values (eg. as the result of a FTOSI instruction).
109 s<2n> maps to the least significant half of d<n>
110 s<2n+1> maps to the most significant half of d<n>
111 */
112
113 /* CPU state for each instance of a generic timer (in cp15 c14) */
114 typedef struct ARMGenericTimer {
115 uint64_t cval; /* Timer CompareValue register */
116 uint64_t ctl; /* Timer Control register */
117 } ARMGenericTimer;
118
119 #define GTIMER_PHYS 0
120 #define GTIMER_VIRT 1
121 #define NUM_GTIMERS 2
122
123 typedef struct CPUARMState {
124 /* Regs for current mode. */
125 uint32_t regs[16];
126
127 /* 32/64 switch only happens when taking and returning from
128 * exceptions so the overlap semantics are taken care of then
129 * instead of having a complicated union.
130 */
131 /* Regs for A64 mode. */
132 uint64_t xregs[32];
133 uint64_t pc;
134 /* PSTATE isn't an architectural register for ARMv8. However, it is
135 * convenient for us to assemble the underlying state into a 32 bit format
136 * identical to the architectural format used for the SPSR. (This is also
137 * what the Linux kernel's 'pstate' field in signal handlers and KVM's
138 * 'pstate' register are.) Of the PSTATE bits:
139 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same
140 * semantics as for AArch32, as described in the comments on each field)
141 * nRW (also known as M[4]) is kept, inverted, in env->aarch64
142 * DAIF (exception masks) are kept in env->daif
143 * all other bits are stored in their correct places in env->pstate
144 */
145 uint32_t pstate;
146 uint32_t aarch64; /* 1 if CPU is in aarch64 state; inverse of PSTATE.nRW */
147
148 /* Frequently accessed CPSR bits are stored separately for efficiency.
149 This contains all the other bits. Use cpsr_{read,write} to access
150 the whole CPSR. */
151 uint32_t uncached_cpsr;
152 uint32_t spsr;
153
154 /* Banked registers. */
155 uint64_t banked_spsr[8];
156 uint32_t banked_r13[8];
157 uint32_t banked_r14[8];
158
159 /* These hold r8-r12. */
160 uint32_t usr_regs[5];
161 uint32_t fiq_regs[5];
162
163 /* cpsr flag cache for faster execution */
164 uint32_t CF; /* 0 or 1 */
165 uint32_t VF; /* V is the bit 31. All other bits are undefined */
166 uint32_t NF; /* N is bit 31. All other bits are undefined. */
167 uint32_t ZF; /* Z set if zero. */
168 uint32_t QF; /* 0 or 1 */
169 uint32_t GE; /* cpsr[19:16] */
170 uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */
171 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */
172 uint64_t daif; /* exception masks, in the bits they are in in PSTATE */
173
174 uint64_t elr_el[4]; /* AArch64 exception link regs */
175 uint64_t sp_el[4]; /* AArch64 banked stack pointers */
176
177 /* System control coprocessor (cp15) */
178 struct {
179 uint32_t c0_cpuid;
180 uint64_t c0_cssel; /* Cache size selection. */
181 uint64_t c1_sys; /* System control register. */
182 uint64_t c1_coproc; /* Coprocessor access register. */
183 uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */
184 uint64_t ttbr0_el1; /* MMU translation table base 0. */
185 uint64_t ttbr1_el1; /* MMU translation table base 1. */
186 uint64_t c2_control; /* MMU translation table base control. */
187 uint32_t c2_mask; /* MMU translation table base selection mask. */
188 uint32_t c2_base_mask; /* MMU translation table base 0 mask. */
189 uint32_t c2_data; /* MPU data cachable bits. */
190 uint32_t c2_insn; /* MPU instruction cachable bits. */
191 uint32_t c3; /* MMU domain access control register
192 MPU write buffer control. */
193 uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */
194 uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */
195 uint64_t hcr_el2; /* Hypervisor configuration register */
196 uint64_t scr_el3; /* Secure configuration register. */
197 uint32_t ifsr_el2; /* Fault status registers. */
198 uint64_t esr_el[4];
199 uint32_t c6_region[8]; /* MPU base/size registers. */
200 uint64_t far_el[4]; /* Fault address registers. */
201 uint64_t par_el1; /* Translation result. */
202 uint32_t c9_insn; /* Cache lockdown registers. */
203 uint32_t c9_data;
204 uint64_t c9_pmcr; /* performance monitor control register */
205 uint64_t c9_pmcnten; /* perf monitor counter enables */
206 uint32_t c9_pmovsr; /* perf monitor overflow status */
207 uint32_t c9_pmxevtyper; /* perf monitor event type */
208 uint32_t c9_pmuserenr; /* perf monitor user enable */
209 uint32_t c9_pminten; /* perf monitor interrupt enables */
210 uint64_t mair_el1;
211 uint64_t vbar_el[4]; /* vector base address register */
212 uint32_t c13_fcse; /* FCSE PID. */
213 uint64_t contextidr_el1; /* Context ID. */
214 uint64_t tpidr_el0; /* User RW Thread register. */
215 uint64_t tpidrro_el0; /* User RO Thread register. */
216 uint64_t tpidr_el1; /* Privileged Thread register. */
217 uint64_t c14_cntfrq; /* Counter Frequency register */
218 uint64_t c14_cntkctl; /* Timer Control register */
219 ARMGenericTimer c14_timer[NUM_GTIMERS];
220 uint32_t c15_cpar; /* XScale Coprocessor Access Register */
221 uint32_t c15_ticonfig; /* TI925T configuration byte. */
222 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */
223 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */
224 uint32_t c15_threadid; /* TI debugger thread-ID. */
225 uint32_t c15_config_base_address; /* SCU base address. */
226 uint32_t c15_diagnostic; /* diagnostic register */
227 uint32_t c15_power_diagnostic;
228 uint32_t c15_power_control; /* power control */
229 uint64_t dbgbvr[16]; /* breakpoint value registers */
230 uint64_t dbgbcr[16]; /* breakpoint control registers */
231 uint64_t dbgwvr[16]; /* watchpoint value registers */
232 uint64_t dbgwcr[16]; /* watchpoint control registers */
233 uint64_t mdscr_el1;
234 /* If the counter is enabled, this stores the last time the counter
235 * was reset. Otherwise it stores the counter value
236 */
237 uint64_t c15_ccnt;
238 uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */
239 } cp15;
240
241 struct {
242 uint32_t other_sp;
243 uint32_t vecbase;
244 uint32_t basepri;
245 uint32_t control;
246 int current_sp;
247 int exception;
248 int pending_exception;
249 } v7m;
250
251 /* Information associated with an exception about to be taken:
252 * code which raises an exception must set cs->exception_index and
253 * the relevant parts of this structure; the cpu_do_interrupt function
254 * will then set the guest-visible registers as part of the exception
255 * entry process.
256 */
257 struct {
258 uint32_t syndrome; /* AArch64 format syndrome register */
259 uint32_t fsr; /* AArch32 format fault status register info */
260 uint64_t vaddress; /* virtual addr associated with exception, if any */
261 /* If we implement EL2 we will also need to store information
262 * about the intermediate physical address for stage 2 faults.
263 */
264 } exception;
265
266 /* Thumb-2 EE state. */
267 uint32_t teecr;
268 uint32_t teehbr;
269
270 /* VFP coprocessor state. */
271 struct {
272 /* VFP/Neon register state. Note that the mapping between S, D and Q
273 * views of the register bank differs between AArch64 and AArch32:
274 * In AArch32:
275 * Qn = regs[2n+1]:regs[2n]
276 * Dn = regs[n]
277 * Sn = regs[n/2] bits 31..0 for even n, and bits 63..32 for odd n
278 * (and regs[32] to regs[63] are inaccessible)
279 * In AArch64:
280 * Qn = regs[2n+1]:regs[2n]
281 * Dn = regs[2n]
282 * Sn = regs[2n] bits 31..0
283 * This corresponds to the architecturally defined mapping between
284 * the two execution states, and means we do not need to explicitly
285 * map these registers when changing states.
286 */
287 float64 regs[64];
288
289 uint32_t xregs[16];
290 /* We store these fpcsr fields separately for convenience. */
291 int vec_len;
292 int vec_stride;
293
294 /* scratch space when Tn are not sufficient. */
295 uint32_t scratch[8];
296
297 /* fp_status is the "normal" fp status. standard_fp_status retains
298 * values corresponding to the ARM "Standard FPSCR Value", ie
299 * default-NaN, flush-to-zero, round-to-nearest and is used by
300 * any operations (generally Neon) which the architecture defines
301 * as controlled by the standard FPSCR value rather than the FPSCR.
302 *
303 * To avoid having to transfer exception bits around, we simply
304 * say that the FPSCR cumulative exception flags are the logical
305 * OR of the flags in the two fp statuses. This relies on the
306 * only thing which needs to read the exception flags being
307 * an explicit FPSCR read.
308 */
309 float_status fp_status;
310 float_status standard_fp_status;
311 } vfp;
312 uint64_t exclusive_addr;
313 uint64_t exclusive_val;
314 uint64_t exclusive_high;
315 #if defined(CONFIG_USER_ONLY)
316 uint64_t exclusive_test;
317 uint32_t exclusive_info;
318 #endif
319
320 /* iwMMXt coprocessor state. */
321 struct {
322 uint64_t regs[16];
323 uint64_t val;
324
325 uint32_t cregs[16];
326 } iwmmxt;
327
328 /* For mixed endian mode. */
329 bool bswap_code;
330
331 #if defined(CONFIG_USER_ONLY)
332 /* For usermode syscall translation. */
333 int eabi;
334 #endif
335
336 struct CPUBreakpoint *cpu_breakpoint[16];
337 struct CPUWatchpoint *cpu_watchpoint[16];
338
339 CPU_COMMON
340
341 /* These fields after the common ones so they are preserved on reset. */
342
343 /* Internal CPU feature flags. */
344 uint64_t features;
345
346 void *nvic;
347 const struct arm_boot_info *boot_info;
348
349 // Unicorn engine
350 struct uc_struct *uc;
351 } CPUARMState;
352
353 #include "cpu-qom.h"
354
355 ARMCPU *cpu_arm_init(struct uc_struct *uc, const char *cpu_model);
356 int cpu_arm_exec(struct uc_struct *uc, CPUARMState *s);
357 uint32_t do_arm_semihosting(CPUARMState *env);
358
is_a64(CPUARMState * env)359 static inline bool is_a64(CPUARMState *env)
360 {
361 return env->aarch64;
362 }
363
364 /* you can call this signal handler from your SIGBUS and SIGSEGV
365 signal handlers to inform the virtual CPU of exceptions. non zero
366 is returned if the signal was handled by the virtual CPU. */
367 int cpu_arm_signal_handler(int host_signum, void *pinfo,
368 void *puc);
369 int arm_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
370 int mmu_idx);
371
372 /**
373 * pmccntr_sync
374 * @env: CPUARMState
375 *
376 * Synchronises the counter in the PMCCNTR. This must always be called twice,
377 * once before any action that might affect the timer and again afterwards.
378 * The function is used to swap the state of the register if required.
379 * This only happens when not in user mode (!CONFIG_USER_ONLY)
380 */
381 void pmccntr_sync(CPUARMState *env);
382
383 /* SCTLR bit meanings. Several bits have been reused in newer
384 * versions of the architecture; in that case we define constants
385 * for both old and new bit meanings. Code which tests against those
386 * bits should probably check or otherwise arrange that the CPU
387 * is the architectural version it expects.
388 */
389 #define SCTLR_M (1U << 0)
390 #define SCTLR_A (1U << 1)
391 #define SCTLR_C (1U << 2)
392 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */
393 #define SCTLR_SA (1U << 3)
394 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */
395 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */
396 #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */
397 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */
398 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */
399 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */
400 #define SCTLR_ITD (1U << 7) /* v8 onward */
401 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */
402 #define SCTLR_SED (1U << 8) /* v8 onward */
403 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */
404 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */
405 #define SCTLR_F (1U << 10) /* up to v6 */
406 #define SCTLR_SW (1U << 10) /* v7 onward */
407 #define SCTLR_Z (1U << 11)
408 #define SCTLR_I (1U << 12)
409 #define SCTLR_V (1U << 13)
410 #define SCTLR_RR (1U << 14) /* up to v7 */
411 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */
412 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */
413 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */
414 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */
415 #define SCTLR_nTWI (1U << 16) /* v8 onward */
416 #define SCTLR_HA (1U << 17)
417 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */
418 #define SCTLR_nTWE (1U << 18) /* v8 onward */
419 #define SCTLR_WXN (1U << 19)
420 #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */
421 #define SCTLR_UWXN (1U << 20) /* v7 onward */
422 #define SCTLR_FI (1U << 21)
423 #define SCTLR_U (1U << 22)
424 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */
425 #define SCTLR_VE (1U << 24) /* up to v7 */
426 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */
427 #define SCTLR_EE (1U << 25)
428 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */
429 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */
430 #define SCTLR_NMFI (1U << 27)
431 #define SCTLR_TRE (1U << 28)
432 #define SCTLR_AFE (1U << 29)
433 #define SCTLR_TE (1U << 30)
434
435 #define CPSR_M (0x1fU)
436 #define CPSR_T (1U << 5)
437 #define CPSR_F (1U << 6)
438 #define CPSR_I (1U << 7)
439 #define CPSR_A (1U << 8)
440 #define CPSR_E (1U << 9)
441 #define CPSR_IT_2_7 (0xfc00U)
442 #define CPSR_GE (0xfU << 16)
443 #define CPSR_IL (1U << 20)
444 /* Note that the RESERVED bits include bit 21, which is PSTATE_SS in
445 * an AArch64 SPSR but RES0 in AArch32 SPSR and CPSR. In QEMU we use
446 * env->uncached_cpsr bit 21 to store PSTATE.SS when executing in AArch32,
447 * where it is live state but not accessible to the AArch32 code.
448 */
449 #define CPSR_RESERVED (0x7U << 21)
450 #define CPSR_J (1U << 24)
451 #define CPSR_IT_0_1 (3U << 25)
452 #define CPSR_Q (1U << 27)
453 #define CPSR_V (1U << 28)
454 #define CPSR_C (1U << 29)
455 #define CPSR_Z (1U << 30)
456 #define CPSR_N (1U << 31)
457 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
458 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F)
459
460 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
461 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \
462 | CPSR_NZCV)
463 /* Bits writable in user mode. */
464 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE)
465 /* Execution state bits. MRS read as zero, MSR writes ignored. */
466 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL)
467 /* Mask of bits which may be set by exception return copying them from SPSR */
468 #define CPSR_ERET_MASK (~CPSR_RESERVED)
469
470 #define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */
471 #define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */
472 #define TTBCR_PD0 (1U << 4)
473 #define TTBCR_PD1 (1U << 5)
474 #define TTBCR_EPD0 (1U << 7)
475 #define TTBCR_IRGN0 (3U << 8)
476 #define TTBCR_ORGN0 (3U << 10)
477 #define TTBCR_SH0 (3U << 12)
478 #define TTBCR_T1SZ (3U << 16)
479 #define TTBCR_A1 (1U << 22)
480 #define TTBCR_EPD1 (1U << 23)
481 #define TTBCR_IRGN1 (3U << 24)
482 #define TTBCR_ORGN1 (3U << 26)
483 #define TTBCR_SH1 (1U << 28)
484 #define TTBCR_EAE (1U << 31)
485
486 /* Bit definitions for ARMv8 SPSR (PSTATE) format.
487 * Only these are valid when in AArch64 mode; in
488 * AArch32 mode SPSRs are basically CPSR-format.
489 */
490 #define PSTATE_SP (1U)
491 #define PSTATE_M (0xFU)
492 #define PSTATE_nRW (1U << 4)
493 #define PSTATE_F (1U << 6)
494 #define PSTATE_I (1U << 7)
495 #define PSTATE_A (1U << 8)
496 #define PSTATE_D (1U << 9)
497 #define PSTATE_IL (1U << 20)
498 #define PSTATE_SS (1U << 21)
499 #define PSTATE_V (1U << 28)
500 #define PSTATE_C (1U << 29)
501 #define PSTATE_Z (1U << 30)
502 #define PSTATE_N (1U << 31)
503 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V)
504 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F)
505 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF)
506 /* Mode values for AArch64 */
507 #define PSTATE_MODE_EL3h 13
508 #define PSTATE_MODE_EL3t 12
509 #define PSTATE_MODE_EL2h 9
510 #define PSTATE_MODE_EL2t 8
511 #define PSTATE_MODE_EL1h 5
512 #define PSTATE_MODE_EL1t 4
513 #define PSTATE_MODE_EL0t 0
514
515 /* Map EL and handler into a PSTATE_MODE. */
aarch64_pstate_mode(unsigned int el,bool handler)516 static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler)
517 {
518 return (el << 2) | handler;
519 }
520
521 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit
522 * interprocessing, so we don't attempt to sync with the cpsr state used by
523 * the 32 bit decoder.
524 */
pstate_read(CPUARMState * env)525 static inline uint32_t pstate_read(CPUARMState *env)
526 {
527 int ZF;
528
529 ZF = (env->ZF == 0);
530 return (env->NF & 0x80000000) | (ZF << 30)
531 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3)
532 | env->pstate | env->daif;
533 }
534
pstate_write(CPUARMState * env,uint32_t val)535 static inline void pstate_write(CPUARMState *env, uint32_t val)
536 {
537 env->ZF = (~val) & PSTATE_Z;
538 env->NF = val;
539 env->CF = (val >> 29) & 1;
540 env->VF = (val << 3) & 0x80000000;
541 env->daif = val & PSTATE_DAIF;
542 env->pstate = val & ~CACHED_PSTATE_BITS;
543 }
544
545 /* Return the current CPSR value. */
546 uint32_t cpsr_read(CPUARMState *env);
547 /* Set the CPSR. Note that some bits of mask must be all-set or all-clear. */
548 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask);
549
550 /* Return the current xPSR value. */
xpsr_read(CPUARMState * env)551 static inline uint32_t xpsr_read(CPUARMState *env)
552 {
553 int ZF;
554 ZF = (env->ZF == 0);
555 return (env->NF & 0x80000000) | (ZF << 30)
556 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
557 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25)
558 | ((env->condexec_bits & 0xfc) << 8)
559 | env->v7m.exception;
560 }
561
562 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */
xpsr_write(CPUARMState * env,uint32_t val,uint32_t mask)563 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
564 {
565 if (mask & CPSR_NZCV) {
566 env->ZF = (~val) & CPSR_Z;
567 env->NF = val;
568 env->CF = (val >> 29) & 1;
569 env->VF = (val << 3) & 0x80000000;
570 }
571 if (mask & CPSR_Q)
572 env->QF = ((val & CPSR_Q) != 0);
573 if (mask & (1 << 24))
574 env->thumb = ((val & (1 << 24)) != 0);
575 if (mask & CPSR_IT_0_1) {
576 env->condexec_bits &= ~3;
577 env->condexec_bits |= (val >> 25) & 3;
578 }
579 if (mask & CPSR_IT_2_7) {
580 env->condexec_bits &= 3;
581 env->condexec_bits |= (val >> 8) & 0xfc;
582 }
583 if (mask & 0x1ff) {
584 env->v7m.exception = val & 0x1ff;
585 }
586 }
587
588 #define HCR_VM (1ULL << 0)
589 #define HCR_SWIO (1ULL << 1)
590 #define HCR_PTW (1ULL << 2)
591 #define HCR_FMO (1ULL << 3)
592 #define HCR_IMO (1ULL << 4)
593 #define HCR_AMO (1ULL << 5)
594 #define HCR_VF (1ULL << 6)
595 #define HCR_VI (1ULL << 7)
596 #define HCR_VSE (1ULL << 8)
597 #define HCR_FB (1ULL << 9)
598 #define HCR_BSU_MASK (3ULL << 10)
599 #define HCR_DC (1ULL << 12)
600 #define HCR_TWI (1ULL << 13)
601 #define HCR_TWE (1ULL << 14)
602 #define HCR_TID0 (1ULL << 15)
603 #define HCR_TID1 (1ULL << 16)
604 #define HCR_TID2 (1ULL << 17)
605 #define HCR_TID3 (1ULL << 18)
606 #define HCR_TSC (1ULL << 19)
607 #define HCR_TIDCP (1ULL << 20)
608 #define HCR_TACR (1ULL << 21)
609 #define HCR_TSW (1ULL << 22)
610 #define HCR_TPC (1ULL << 23)
611 #define HCR_TPU (1ULL << 24)
612 #define HCR_TTLB (1ULL << 25)
613 #define HCR_TVM (1ULL << 26)
614 #define HCR_TGE (1ULL << 27)
615 #define HCR_TDZ (1ULL << 28)
616 #define HCR_HCD (1ULL << 29)
617 #define HCR_TRVM (1ULL << 30)
618 #define HCR_RW (1ULL << 31)
619 #define HCR_CD (1ULL << 32)
620 #define HCR_ID (1ULL << 33)
621 #define HCR_MASK ((1ULL << 34) - 1)
622
623 #define SCR_NS (1U << 0)
624 #define SCR_IRQ (1U << 1)
625 #define SCR_FIQ (1U << 2)
626 #define SCR_EA (1U << 3)
627 #define SCR_FW (1U << 4)
628 #define SCR_AW (1U << 5)
629 #define SCR_NET (1U << 6)
630 #define SCR_SMD (1U << 7)
631 #define SCR_HCE (1U << 8)
632 #define SCR_SIF (1U << 9)
633 #define SCR_RW (1U << 10)
634 #define SCR_ST (1U << 11)
635 #define SCR_TWI (1U << 12)
636 #define SCR_TWE (1U << 13)
637 #define SCR_AARCH32_MASK (0x3fff & ~(SCR_RW | SCR_ST))
638 #define SCR_AARCH64_MASK (0x3fff & ~SCR_NET)
639
640 /* Return the current FPSCR value. */
641 uint32_t vfp_get_fpscr(CPUARMState *env);
642 void vfp_set_fpscr(CPUARMState *env, uint32_t val);
643
644 /* For A64 the FPSCR is split into two logically distinct registers,
645 * FPCR and FPSR. However since they still use non-overlapping bits
646 * we store the underlying state in fpscr and just mask on read/write.
647 */
648 #define FPSR_MASK 0xf800009f
649 #define FPCR_MASK 0x07f79f00
vfp_get_fpsr(CPUARMState * env)650 static inline uint32_t vfp_get_fpsr(CPUARMState *env)
651 {
652 return vfp_get_fpscr(env) & FPSR_MASK;
653 }
654
vfp_set_fpsr(CPUARMState * env,uint32_t val)655 static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val)
656 {
657 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK);
658 vfp_set_fpscr(env, new_fpscr);
659 }
660
vfp_get_fpcr(CPUARMState * env)661 static inline uint32_t vfp_get_fpcr(CPUARMState *env)
662 {
663 return vfp_get_fpscr(env) & FPCR_MASK;
664 }
665
vfp_set_fpcr(CPUARMState * env,uint32_t val)666 static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val)
667 {
668 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK);
669 vfp_set_fpscr(env, new_fpscr);
670 }
671
672 enum arm_cpu_mode {
673 ARM_CPU_MODE_USR = 0x10,
674 ARM_CPU_MODE_FIQ = 0x11,
675 ARM_CPU_MODE_IRQ = 0x12,
676 ARM_CPU_MODE_SVC = 0x13,
677 ARM_CPU_MODE_MON = 0x16,
678 ARM_CPU_MODE_ABT = 0x17,
679 ARM_CPU_MODE_HYP = 0x1a,
680 ARM_CPU_MODE_UND = 0x1b,
681 ARM_CPU_MODE_SYS = 0x1f
682 };
683
684 /* VFP system registers. */
685 #define ARM_VFP_FPSID 0
686 #define ARM_VFP_FPSCR 1
687 #define ARM_VFP_MVFR2 5
688 #define ARM_VFP_MVFR1 6
689 #define ARM_VFP_MVFR0 7
690 #define ARM_VFP_FPEXC 8
691 #define ARM_VFP_FPINST 9
692 #define ARM_VFP_FPINST2 10
693
694 /* iwMMXt coprocessor control registers. */
695 #define ARM_IWMMXT_wCID 0
696 #define ARM_IWMMXT_wCon 1
697 #define ARM_IWMMXT_wCSSF 2
698 #define ARM_IWMMXT_wCASF 3
699 #define ARM_IWMMXT_wCGR0 8
700 #define ARM_IWMMXT_wCGR1 9
701 #define ARM_IWMMXT_wCGR2 10
702 #define ARM_IWMMXT_wCGR3 11
703
704 /* If adding a feature bit which corresponds to a Linux ELF
705 * HWCAP bit, remember to update the feature-bit-to-hwcap
706 * mapping in linux-user/elfload.c:get_elf_hwcap().
707 */
708 enum arm_features {
709 ARM_FEATURE_VFP,
710 ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */
711 ARM_FEATURE_XSCALE, /* Intel XScale extensions. */
712 ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */
713 ARM_FEATURE_V6,
714 ARM_FEATURE_V6K,
715 ARM_FEATURE_V7,
716 ARM_FEATURE_THUMB2,
717 ARM_FEATURE_MPU, /* Only has Memory Protection Unit, not full MMU. */
718 ARM_FEATURE_VFP3,
719 ARM_FEATURE_VFP_FP16,
720 ARM_FEATURE_NEON,
721 ARM_FEATURE_THUMB_DIV, /* divide supported in Thumb encoding */
722 ARM_FEATURE_M, /* Microcontroller profile. */
723 ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */
724 ARM_FEATURE_THUMB2EE,
725 ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */
726 ARM_FEATURE_V4T,
727 ARM_FEATURE_V5,
728 ARM_FEATURE_STRONGARM,
729 ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */
730 ARM_FEATURE_ARM_DIV, /* divide supported in ARM encoding */
731 ARM_FEATURE_VFP4, /* VFPv4 (implies that NEON is v2) */
732 ARM_FEATURE_GENERIC_TIMER,
733 ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */
734 ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */
735 ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */
736 ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */
737 ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */
738 ARM_FEATURE_MPIDR, /* has cp15 MPIDR */
739 ARM_FEATURE_PXN, /* has Privileged Execute Never bit */
740 ARM_FEATURE_LPAE, /* has Large Physical Address Extension */
741 ARM_FEATURE_V8,
742 ARM_FEATURE_AARCH64, /* supports 64 bit mode */
743 ARM_FEATURE_V8_AES, /* implements AES part of v8 Crypto Extensions */
744 ARM_FEATURE_CBAR, /* has cp15 CBAR */
745 ARM_FEATURE_CRC, /* ARMv8 CRC instructions */
746 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */
747 ARM_FEATURE_EL2, /* has EL2 Virtualization support */
748 ARM_FEATURE_EL3, /* has EL3 Secure monitor support */
749 ARM_FEATURE_V8_SHA1, /* implements SHA1 part of v8 Crypto Extensions */
750 ARM_FEATURE_V8_SHA256, /* implements SHA256 part of v8 Crypto Extensions */
751 ARM_FEATURE_V8_PMULL, /* implements PMULL part of v8 Crypto Extensions */
752 };
753
arm_feature(CPUARMState * env,int feature)754 static inline int arm_feature(CPUARMState *env, int feature)
755 {
756 return (env->features & (1ULL << feature)) != 0;
757 }
758
759 #if !defined(CONFIG_USER_ONLY)
760 /* Return true if exception levels below EL3 are in secure state,
761 * or would be following an exception return to that level.
762 * Unlike arm_is_secure() (which is always a question about the
763 * _current_ state of the CPU) this doesn't care about the current
764 * EL or mode.
765 */
arm_is_secure_below_el3(CPUARMState * env)766 static inline bool arm_is_secure_below_el3(CPUARMState *env)
767 {
768 if (arm_feature(env, ARM_FEATURE_EL3)) {
769 return !(env->cp15.scr_el3 & SCR_NS);
770 } else {
771 /* If EL2 is not supported then the secure state is implementation
772 * defined, in which case QEMU defaults to non-secure.
773 */
774 return false;
775 }
776 }
777
778 /* Return true if the processor is in secure state */
arm_is_secure(CPUARMState * env)779 static inline bool arm_is_secure(CPUARMState *env)
780 {
781 if (arm_feature(env, ARM_FEATURE_EL3)) {
782 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) {
783 /* CPU currently in AArch64 state and EL3 */
784 return true;
785 } else if (!is_a64(env) &&
786 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) {
787 /* CPU currently in AArch32 state and monitor mode */
788 return true;
789 }
790 }
791 return arm_is_secure_below_el3(env);
792 }
793
794 #else
arm_is_secure_below_el3(CPUARMState * env)795 static inline bool arm_is_secure_below_el3(CPUARMState *env)
796 {
797 return false;
798 }
799
arm_is_secure(CPUARMState * env)800 static inline bool arm_is_secure(CPUARMState *env)
801 {
802 return false;
803 }
804 #endif
805
806 /* Return true if the specified exception level is running in AArch64 state. */
arm_el_is_aa64(CPUARMState * env,int el)807 static inline bool arm_el_is_aa64(CPUARMState *env, int el)
808 {
809 /* We don't currently support EL2, and this isn't valid for EL0
810 * (if we're in EL0, is_a64() is what you want, and if we're not in EL0
811 * then the state of EL0 isn't well defined.)
812 */
813 assert(el == 1 || el == 3);
814
815 /* AArch64-capable CPUs always run with EL1 in AArch64 mode. This
816 * is a QEMU-imposed simplification which we may wish to change later.
817 * If we in future support EL2 and/or EL3, then the state of lower
818 * exception levels is controlled by the HCR.RW and SCR.RW bits.
819 */
820 return arm_feature(env, ARM_FEATURE_AARCH64);
821 }
822
823 void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf);
824 unsigned int arm_excp_target_el(CPUState *cs, unsigned int excp_idx);
825
826 /* Interface between CPU and Interrupt controller. */
827 void armv7m_nvic_set_pending(void *opaque, int irq);
828 int armv7m_nvic_acknowledge_irq(void *opaque);
829 void armv7m_nvic_complete_irq(void *opaque, int irq);
830
831 /* Interface for defining coprocessor registers.
832 * Registers are defined in tables of arm_cp_reginfo structs
833 * which are passed to define_arm_cp_regs().
834 */
835
836 /* When looking up a coprocessor register we look for it
837 * via an integer which encodes all of:
838 * coprocessor number
839 * Crn, Crm, opc1, opc2 fields
840 * 32 or 64 bit register (ie is it accessed via MRC/MCR
841 * or via MRRC/MCRR?)
842 * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field.
843 * (In this case crn and opc2 should be zero.)
844 * For AArch64, there is no 32/64 bit size distinction;
845 * instead all registers have a 2 bit op0, 3 bit op1 and op2,
846 * and 4 bit CRn and CRm. The encoding patterns are chosen
847 * to be easy to convert to and from the KVM encodings, and also
848 * so that the hashtable can contain both AArch32 and AArch64
849 * registers (to allow for interprocessing where we might run
850 * 32 bit code on a 64 bit core).
851 */
852 /* This bit is private to our hashtable cpreg; in KVM register
853 * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64
854 * in the upper bits of the 64 bit ID.
855 */
856 #define CP_REG_AA64_SHIFT 28
857 #define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT)
858
859 #define ENCODE_CP_REG(cp, is64, crn, crm, opc1, opc2) \
860 (((cp) << 16) | ((is64) << 15) | ((crn) << 11) | \
861 ((crm) << 7) | ((opc1) << 3) | (opc2))
862
863 #define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \
864 (CP_REG_AA64_MASK | \
865 ((cp) << CP_REG_ARM_COPROC_SHIFT) | \
866 ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \
867 ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \
868 ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \
869 ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \
870 ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT))
871
872 /* Convert a full 64 bit KVM register ID to the truncated 32 bit
873 * version used as a key for the coprocessor register hashtable
874 */
kvm_to_cpreg_id(uint64_t kvmid)875 static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid)
876 {
877 uint32_t cpregid = kvmid;
878 if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) {
879 cpregid |= CP_REG_AA64_MASK;
880 } else if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) {
881 cpregid |= (1 << 15);
882 }
883 return cpregid;
884 }
885
886 /* Convert a truncated 32 bit hashtable key into the full
887 * 64 bit KVM register ID.
888 */
cpreg_to_kvm_id(uint32_t cpregid)889 static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid)
890 {
891 uint64_t kvmid;
892
893 if (cpregid & CP_REG_AA64_MASK) {
894 kvmid = cpregid & ~CP_REG_AA64_MASK;
895 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64;
896 } else {
897 kvmid = cpregid & ~(1 << 15);
898 if (cpregid & (1 << 15)) {
899 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM;
900 } else {
901 kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM;
902 }
903 }
904 return kvmid;
905 }
906
907 /* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a
908 * special-behaviour cp reg and bits [15..8] indicate what behaviour
909 * it has. Otherwise it is a simple cp reg, where CONST indicates that
910 * TCG can assume the value to be constant (ie load at translate time)
911 * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END
912 * indicates that the TB should not be ended after a write to this register
913 * (the default is that the TB ends after cp writes). OVERRIDE permits
914 * a register definition to override a previous definition for the
915 * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the
916 * old must have the OVERRIDE bit set.
917 * NO_MIGRATE indicates that this register should be ignored for migration;
918 * (eg because any state is accessed via some other coprocessor register).
919 * IO indicates that this register does I/O and therefore its accesses
920 * need to be surrounded by gen_io_start()/gen_io_end(). In particular,
921 * registers which implement clocks or timers require this.
922 */
923 #define ARM_CP_SPECIAL 1
924 #define ARM_CP_CONST 2
925 #define ARM_CP_64BIT 4
926 #define ARM_CP_SUPPRESS_TB_END 8
927 #define ARM_CP_OVERRIDE 16
928 #define ARM_CP_NO_MIGRATE 32
929 #define ARM_CP_IO 64
930 #define ARM_CP_NOP (ARM_CP_SPECIAL | (1 << 8))
931 #define ARM_CP_WFI (ARM_CP_SPECIAL | (2 << 8))
932 #define ARM_CP_NZCV (ARM_CP_SPECIAL | (3 << 8))
933 #define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | (4 << 8))
934 #define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | (5 << 8))
935 #define ARM_LAST_SPECIAL ARM_CP_DC_ZVA
936 /* Used only as a terminator for ARMCPRegInfo lists */
937 #define ARM_CP_SENTINEL 0xffff
938 /* Mask of only the flag bits in a type field */
939 #define ARM_CP_FLAG_MASK 0x7f
940
941 /* Valid values for ARMCPRegInfo state field, indicating which of
942 * the AArch32 and AArch64 execution states this register is visible in.
943 * If the reginfo doesn't explicitly specify then it is AArch32 only.
944 * If the reginfo is declared to be visible in both states then a second
945 * reginfo is synthesised for the AArch32 view of the AArch64 register,
946 * such that the AArch32 view is the lower 32 bits of the AArch64 one.
947 * Note that we rely on the values of these enums as we iterate through
948 * the various states in some places.
949 */
950 enum {
951 ARM_CP_STATE_AA32 = 0,
952 ARM_CP_STATE_AA64 = 1,
953 ARM_CP_STATE_BOTH = 2,
954 };
955
956 /* Return true if cptype is a valid type field. This is used to try to
957 * catch errors where the sentinel has been accidentally left off the end
958 * of a list of registers.
959 */
cptype_valid(int cptype)960 static inline bool cptype_valid(int cptype)
961 {
962 return ((cptype & ~ARM_CP_FLAG_MASK) == 0)
963 || ((cptype & ARM_CP_SPECIAL) &&
964 ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL));
965 }
966
967 /* Access rights:
968 * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM
969 * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and
970 * PL2 (hyp). The other level which has Read and Write bits is Secure PL1
971 * (ie any of the privileged modes in Secure state, or Monitor mode).
972 * If a register is accessible in one privilege level it's always accessible
973 * in higher privilege levels too. Since "Secure PL1" also follows this rule
974 * (ie anything visible in PL2 is visible in S-PL1, some things are only
975 * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the
976 * terminology a little and call this PL3.
977 * In AArch64 things are somewhat simpler as the PLx bits line up exactly
978 * with the ELx exception levels.
979 *
980 * If access permissions for a register are more complex than can be
981 * described with these bits, then use a laxer set of restrictions, and
982 * do the more restrictive/complex check inside a helper function.
983 */
984 #define PL3_R 0x80
985 #define PL3_W 0x40
986 #define PL2_R (0x20 | PL3_R)
987 #define PL2_W (0x10 | PL3_W)
988 #define PL1_R (0x08 | PL2_R)
989 #define PL1_W (0x04 | PL2_W)
990 #define PL0_R (0x02 | PL1_R)
991 #define PL0_W (0x01 | PL1_W)
992
993 #define PL3_RW (PL3_R | PL3_W)
994 #define PL2_RW (PL2_R | PL2_W)
995 #define PL1_RW (PL1_R | PL1_W)
996 #define PL0_RW (PL0_R | PL0_W)
997
998 /* Return the current Exception Level (as per ARMv8; note that this differs
999 * from the ARMv7 Privilege Level).
1000 */
arm_current_el(CPUARMState * env)1001 static inline int arm_current_el(CPUARMState *env)
1002 {
1003 if (is_a64(env)) {
1004 return extract32(env->pstate, 2, 2);
1005 }
1006
1007 switch (env->uncached_cpsr & 0x1f) {
1008 case ARM_CPU_MODE_USR:
1009 return 0;
1010 case ARM_CPU_MODE_HYP:
1011 return 2;
1012 case ARM_CPU_MODE_MON:
1013 return 3;
1014 default:
1015 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) {
1016 /* If EL3 is 32-bit then all secure privileged modes run in
1017 * EL3
1018 */
1019 return 3;
1020 }
1021
1022 return 1;
1023 }
1024 }
1025
1026 typedef struct ARMCPRegInfo ARMCPRegInfo;
1027
1028 typedef enum CPAccessResult {
1029 /* Access is permitted */
1030 CP_ACCESS_OK = 0,
1031 /* Access fails due to a configurable trap or enable which would
1032 * result in a categorized exception syndrome giving information about
1033 * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6,
1034 * 0xc or 0x18).
1035 */
1036 CP_ACCESS_TRAP = 1,
1037 /* Access fails and results in an exception syndrome 0x0 ("uncategorized").
1038 * Note that this is not a catch-all case -- the set of cases which may
1039 * result in this failure is specifically defined by the architecture.
1040 */
1041 CP_ACCESS_TRAP_UNCATEGORIZED = 2,
1042 } CPAccessResult;
1043
1044 /* Access functions for coprocessor registers. These cannot fail and
1045 * may not raise exceptions.
1046 */
1047 typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque);
1048 typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque,
1049 uint64_t value);
1050 /* Access permission check functions for coprocessor registers. */
1051 typedef CPAccessResult CPAccessFn(CPUARMState *env, const ARMCPRegInfo *opaque);
1052 /* Hook function for register reset */
1053 typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque);
1054
1055 #define CP_ANY 0xff
1056
1057 /* Definition of an ARM coprocessor register */
1058 struct ARMCPRegInfo {
1059 /* Name of register (useful mainly for debugging, need not be unique) */
1060 const char *name;
1061 /* Location of register: coprocessor number and (crn,crm,opc1,opc2)
1062 * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a
1063 * 'wildcard' field -- any value of that field in the MRC/MCR insn
1064 * will be decoded to this register. The register read and write
1065 * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2
1066 * used by the program, so it is possible to register a wildcard and
1067 * then behave differently on read/write if necessary.
1068 * For 64 bit registers, only crm and opc1 are relevant; crn and opc2
1069 * must both be zero.
1070 * For AArch64-visible registers, opc0 is also used.
1071 * Since there are no "coprocessors" in AArch64, cp is purely used as a
1072 * way to distinguish (for KVM's benefit) guest-visible system registers
1073 * from demuxed ones provided to preserve the "no side effects on
1074 * KVM register read/write from QEMU" semantics. cp==0x13 is guest
1075 * visible (to match KVM's encoding); cp==0 will be converted to
1076 * cp==0x13 when the ARMCPRegInfo is registered, for convenience.
1077 */
1078 uint8_t cp;
1079 uint8_t crn;
1080 uint8_t crm;
1081 uint8_t opc0;
1082 uint8_t opc1;
1083 uint8_t opc2;
1084 /* Execution state in which this register is visible: ARM_CP_STATE_* */
1085 int state;
1086 /* Register type: ARM_CP_* bits/values */
1087 int type;
1088 /* Access rights: PL*_[RW] */
1089 int access;
1090 /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when
1091 * this register was defined: can be used to hand data through to the
1092 * register read/write functions, since they are passed the ARMCPRegInfo*.
1093 */
1094 void *opaque;
1095 /* Value of this register, if it is ARM_CP_CONST. Otherwise, if
1096 * fieldoffset is non-zero, the reset value of the register.
1097 */
1098 uint64_t resetvalue;
1099 /* Offset of the field in CPUARMState for this register. This is not
1100 * needed if either:
1101 * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs
1102 * 2. both readfn and writefn are specified
1103 */
1104 ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */
1105 /* Function for making any access checks for this register in addition to
1106 * those specified by the 'access' permissions bits. If NULL, no extra
1107 * checks required. The access check is performed at runtime, not at
1108 * translate time.
1109 */
1110 CPAccessFn *accessfn;
1111 /* Function for handling reads of this register. If NULL, then reads
1112 * will be done by loading from the offset into CPUARMState specified
1113 * by fieldoffset.
1114 */
1115 CPReadFn *readfn;
1116 /* Function for handling writes of this register. If NULL, then writes
1117 * will be done by writing to the offset into CPUARMState specified
1118 * by fieldoffset.
1119 */
1120 CPWriteFn *writefn;
1121 /* Function for doing a "raw" read; used when we need to copy
1122 * coprocessor state to the kernel for KVM or out for
1123 * migration. This only needs to be provided if there is also a
1124 * readfn and it has side effects (for instance clear-on-read bits).
1125 */
1126 CPReadFn *raw_readfn;
1127 /* Function for doing a "raw" write; used when we need to copy KVM
1128 * kernel coprocessor state into userspace, or for inbound
1129 * migration. This only needs to be provided if there is also a
1130 * writefn and it masks out "unwritable" bits or has write-one-to-clear
1131 * or similar behaviour.
1132 */
1133 CPWriteFn *raw_writefn;
1134 /* Function for resetting the register. If NULL, then reset will be done
1135 * by writing resetvalue to the field specified in fieldoffset. If
1136 * fieldoffset is 0 then no reset will be done.
1137 */
1138 CPResetFn *resetfn;
1139 };
1140
1141 /* Macros which are lvalues for the field in CPUARMState for the
1142 * ARMCPRegInfo *ri.
1143 */
1144 #define CPREG_FIELD32(env, ri) \
1145 (*(uint32_t *)((char *)(env) + (ri)->fieldoffset))
1146 #define CPREG_FIELD64(env, ri) \
1147 (*(uint64_t *)((char *)(env) + (ri)->fieldoffset))
1148
1149 #define REGINFO_SENTINEL { NULL, 0,0,0,0,0,0, 0, ARM_CP_SENTINEL, 0, NULL, 0,0,0,0,0,0,0,0, }
1150
1151 void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
1152 const ARMCPRegInfo *regs, void *opaque);
1153 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
1154 const ARMCPRegInfo *regs, void *opaque);
define_arm_cp_regs(ARMCPU * cpu,const ARMCPRegInfo * regs)1155 static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs)
1156 {
1157 define_arm_cp_regs_with_opaque(cpu, regs, 0);
1158 }
define_one_arm_cp_reg(ARMCPU * cpu,const ARMCPRegInfo * regs)1159 static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs)
1160 {
1161 define_one_arm_cp_reg_with_opaque(cpu, regs, 0);
1162 }
1163 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp);
1164
1165 /* CPWriteFn that can be used to implement writes-ignored behaviour */
1166 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
1167 uint64_t value);
1168 /* CPReadFn that can be used for read-as-zero behaviour */
1169 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri);
1170
1171 /* CPResetFn that does nothing, for use if no reset is required even
1172 * if fieldoffset is non zero.
1173 */
1174 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque);
1175
1176 /* Return true if this reginfo struct's field in the cpu state struct
1177 * is 64 bits wide.
1178 */
cpreg_field_is_64bit(const ARMCPRegInfo * ri)1179 static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri)
1180 {
1181 return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT);
1182 }
1183
cp_access_ok(int current_el,const ARMCPRegInfo * ri,int isread)1184 static inline bool cp_access_ok(int current_el,
1185 const ARMCPRegInfo *ri, int isread)
1186 {
1187 return (ri->access >> ((current_el * 2) + isread)) & 1;
1188 }
1189
1190 /**
1191 * write_list_to_cpustate
1192 * @cpu: ARMCPU
1193 *
1194 * For each register listed in the ARMCPU cpreg_indexes list, write
1195 * its value from the cpreg_values list into the ARMCPUState structure.
1196 * This updates TCG's working data structures from KVM data or
1197 * from incoming migration state.
1198 *
1199 * Returns: true if all register values were updated correctly,
1200 * false if some register was unknown or could not be written.
1201 * Note that we do not stop early on failure -- we will attempt
1202 * writing all registers in the list.
1203 */
1204 bool write_list_to_cpustate(ARMCPU *cpu);
1205
1206 /**
1207 * write_cpustate_to_list:
1208 * @cpu: ARMCPU
1209 *
1210 * For each register listed in the ARMCPU cpreg_indexes list, write
1211 * its value from the ARMCPUState structure into the cpreg_values list.
1212 * This is used to copy info from TCG's working data structures into
1213 * KVM or for outbound migration.
1214 *
1215 * Returns: true if all register values were read correctly,
1216 * false if some register was unknown or could not be read.
1217 * Note that we do not stop early on failure -- we will attempt
1218 * reading all registers in the list.
1219 */
1220 bool write_cpustate_to_list(ARMCPU *cpu);
1221
1222 /* Does the core conform to the the "MicroController" profile. e.g. Cortex-M3.
1223 Note the M in older cores (eg. ARM7TDMI) stands for Multiply. These are
1224 conventional cores (ie. Application or Realtime profile). */
1225
1226 #define IS_M(env) arm_feature(env, ARM_FEATURE_M)
1227
1228 #define ARM_CPUID_TI915T 0x54029152
1229 #define ARM_CPUID_TI925T 0x54029252
1230
1231 #if defined(CONFIG_USER_ONLY)
1232 #define TARGET_PAGE_BITS 12
1233 #else
1234 /* The ARM MMU allows 1k pages. */
1235 /* ??? Linux doesn't actually use these, and they're deprecated in recent
1236 architecture revisions. Maybe a configure option to disable them. */
1237 #define TARGET_PAGE_BITS 10
1238 #endif
1239
1240 #if defined(TARGET_AARCH64)
1241 # define TARGET_PHYS_ADDR_SPACE_BITS 48
1242 # define TARGET_VIRT_ADDR_SPACE_BITS 64
1243 #else
1244 # define TARGET_PHYS_ADDR_SPACE_BITS 40
1245 # define TARGET_VIRT_ADDR_SPACE_BITS 32
1246 #endif
1247
arm_excp_unmasked(CPUState * cs,unsigned int excp_idx)1248 static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx)
1249 {
1250 CPUARMState *env = cs->env_ptr;
1251 unsigned int cur_el = arm_current_el(env);
1252 unsigned int target_el = arm_excp_target_el(cs, excp_idx);
1253 /* FIXME: Use actual secure state. */
1254 bool secure = false;
1255 /* If in EL1/0, Physical IRQ routing to EL2 only happens from NS state. */
1256 bool irq_can_hyp = !secure && cur_el < 2 && target_el == 2;
1257
1258 /* Don't take exceptions if they target a lower EL. */
1259 if (cur_el > target_el) {
1260 return false;
1261 }
1262
1263 switch (excp_idx) {
1264 case EXCP_FIQ:
1265 if (irq_can_hyp && (env->cp15.hcr_el2 & HCR_FMO)) {
1266 return true;
1267 }
1268 return !(env->daif & PSTATE_F);
1269 case EXCP_IRQ:
1270 if (irq_can_hyp && (env->cp15.hcr_el2 & HCR_IMO)) {
1271 return true;
1272 }
1273 return !(env->daif & PSTATE_I);
1274 case EXCP_VFIQ:
1275 if (secure || !(env->cp15.hcr_el2 & HCR_FMO)) {
1276 /* VFIQs are only taken when hypervized and non-secure. */
1277 return false;
1278 }
1279 return !(env->daif & PSTATE_F);
1280 case EXCP_VIRQ:
1281 if (secure || !(env->cp15.hcr_el2 & HCR_IMO)) {
1282 /* VIRQs are only taken when hypervized and non-secure. */
1283 return false;
1284 }
1285 return !(env->daif & PSTATE_I);
1286 default:
1287 g_assert_not_reached();
1288 return false;
1289 }
1290 }
1291
cpu_init(struct uc_struct * uc,const char * cpu_model)1292 static inline CPUARMState *cpu_init(struct uc_struct *uc, const char *cpu_model)
1293 {
1294 ARMCPU *cpu = cpu_arm_init(uc, cpu_model);
1295 if (cpu) {
1296 return &cpu->env;
1297 }
1298 return NULL;
1299 }
1300
1301 #ifdef TARGET_ARM
1302 #define cpu_exec cpu_arm_exec
1303 #define cpu_gen_code cpu_arm_gen_code
1304 #define cpu_signal_handler cpu_arm_signal_handler
1305 #define cpu_list arm_cpu_list
1306 #endif
1307
1308 /* MMU modes definitions */
1309 #define MMU_MODE0_SUFFIX _user
1310 #define MMU_MODE1_SUFFIX _kernel
1311 #define MMU_USER_IDX 0
cpu_mmu_index(CPUARMState * env)1312 static inline int cpu_mmu_index (CPUARMState *env)
1313 {
1314 return arm_current_el(env);
1315 }
1316
1317 /* Return the Exception Level targeted by debug exceptions;
1318 * currently always EL1 since we don't implement EL2 or EL3.
1319 */
arm_debug_target_el(CPUARMState * env)1320 static inline int arm_debug_target_el(CPUARMState *env)
1321 {
1322 return 1;
1323 }
1324
aa64_generate_debug_exceptions(CPUARMState * env)1325 static inline bool aa64_generate_debug_exceptions(CPUARMState *env)
1326 {
1327 if (arm_current_el(env) == arm_debug_target_el(env)) {
1328 if ((extract32(env->cp15.mdscr_el1, 13, 1) == 0)
1329 || (env->daif & PSTATE_D)) {
1330 return false;
1331 }
1332 }
1333 return true;
1334 }
1335
aa32_generate_debug_exceptions(CPUARMState * env)1336 static inline bool aa32_generate_debug_exceptions(CPUARMState *env)
1337 {
1338 if (arm_current_el(env) == 0 && arm_el_is_aa64(env, 1)) {
1339 return aa64_generate_debug_exceptions(env);
1340 }
1341 return arm_current_el(env) != 2;
1342 }
1343
1344 /* Return true if debugging exceptions are currently enabled.
1345 * This corresponds to what in ARM ARM pseudocode would be
1346 * if UsingAArch32() then
1347 * return AArch32.GenerateDebugExceptions()
1348 * else
1349 * return AArch64.GenerateDebugExceptions()
1350 * We choose to push the if() down into this function for clarity,
1351 * since the pseudocode has it at all callsites except for the one in
1352 * CheckSoftwareStep(), where it is elided because both branches would
1353 * always return the same value.
1354 *
1355 * Parts of the pseudocode relating to EL2 and EL3 are omitted because we
1356 * don't yet implement those exception levels or their associated trap bits.
1357 */
arm_generate_debug_exceptions(CPUARMState * env)1358 static inline bool arm_generate_debug_exceptions(CPUARMState *env)
1359 {
1360 if (env->aarch64) {
1361 return aa64_generate_debug_exceptions(env);
1362 } else {
1363 return aa32_generate_debug_exceptions(env);
1364 }
1365 }
1366
1367 /* Is single-stepping active? (Note that the "is EL_D AArch64?" check
1368 * implicitly means this always returns false in pre-v8 CPUs.)
1369 */
arm_singlestep_active(CPUARMState * env)1370 static inline bool arm_singlestep_active(CPUARMState *env)
1371 {
1372 return extract32(env->cp15.mdscr_el1, 0, 1)
1373 && arm_el_is_aa64(env, arm_debug_target_el(env))
1374 && arm_generate_debug_exceptions(env);
1375 }
1376
1377 #include "exec/cpu-all.h"
1378
1379 /* Bit usage in the TB flags field: bit 31 indicates whether we are
1380 * in 32 or 64 bit mode. The meaning of the other bits depends on that.
1381 */
1382 #define ARM_TBFLAG_AARCH64_STATE_SHIFT 31
1383 #define ARM_TBFLAG_AARCH64_STATE_MASK (1U << ARM_TBFLAG_AARCH64_STATE_SHIFT)
1384
1385 /* Bit usage when in AArch32 state: */
1386 #define ARM_TBFLAG_THUMB_SHIFT 0
1387 #define ARM_TBFLAG_THUMB_MASK (1 << ARM_TBFLAG_THUMB_SHIFT)
1388 #define ARM_TBFLAG_VECLEN_SHIFT 1
1389 #define ARM_TBFLAG_VECLEN_MASK (0x7 << ARM_TBFLAG_VECLEN_SHIFT)
1390 #define ARM_TBFLAG_VECSTRIDE_SHIFT 4
1391 #define ARM_TBFLAG_VECSTRIDE_MASK (0x3 << ARM_TBFLAG_VECSTRIDE_SHIFT)
1392 #define ARM_TBFLAG_PRIV_SHIFT 6
1393 #define ARM_TBFLAG_PRIV_MASK (1 << ARM_TBFLAG_PRIV_SHIFT)
1394 #define ARM_TBFLAG_VFPEN_SHIFT 7
1395 #define ARM_TBFLAG_VFPEN_MASK (1 << ARM_TBFLAG_VFPEN_SHIFT)
1396 #define ARM_TBFLAG_CONDEXEC_SHIFT 8
1397 #define ARM_TBFLAG_CONDEXEC_MASK (0xff << ARM_TBFLAG_CONDEXEC_SHIFT)
1398 #define ARM_TBFLAG_BSWAP_CODE_SHIFT 16
1399 #define ARM_TBFLAG_BSWAP_CODE_MASK (1 << ARM_TBFLAG_BSWAP_CODE_SHIFT)
1400 #define ARM_TBFLAG_CPACR_FPEN_SHIFT 17
1401 #define ARM_TBFLAG_CPACR_FPEN_MASK (1 << ARM_TBFLAG_CPACR_FPEN_SHIFT)
1402 #define ARM_TBFLAG_SS_ACTIVE_SHIFT 18
1403 #define ARM_TBFLAG_SS_ACTIVE_MASK (1 << ARM_TBFLAG_SS_ACTIVE_SHIFT)
1404 #define ARM_TBFLAG_PSTATE_SS_SHIFT 19
1405 #define ARM_TBFLAG_PSTATE_SS_MASK (1 << ARM_TBFLAG_PSTATE_SS_SHIFT)
1406 /* We store the bottom two bits of the CPAR as TB flags and handle
1407 * checks on the other bits at runtime
1408 */
1409 #define ARM_TBFLAG_XSCALE_CPAR_SHIFT 20
1410 #define ARM_TBFLAG_XSCALE_CPAR_MASK (3 << ARM_TBFLAG_XSCALE_CPAR_SHIFT)
1411
1412 /* Bit usage when in AArch64 state */
1413 #define ARM_TBFLAG_AA64_EL_SHIFT 0
1414 #define ARM_TBFLAG_AA64_EL_MASK (0x3 << ARM_TBFLAG_AA64_EL_SHIFT)
1415 #define ARM_TBFLAG_AA64_FPEN_SHIFT 2
1416 #define ARM_TBFLAG_AA64_FPEN_MASK (1 << ARM_TBFLAG_AA64_FPEN_SHIFT)
1417 #define ARM_TBFLAG_AA64_SS_ACTIVE_SHIFT 3
1418 #define ARM_TBFLAG_AA64_SS_ACTIVE_MASK (1 << ARM_TBFLAG_AA64_SS_ACTIVE_SHIFT)
1419 #define ARM_TBFLAG_AA64_PSTATE_SS_SHIFT 4
1420 #define ARM_TBFLAG_AA64_PSTATE_SS_MASK (1 << ARM_TBFLAG_AA64_PSTATE_SS_SHIFT)
1421
1422 /* some convenience accessor macros */
1423 #define ARM_TBFLAG_AARCH64_STATE(F) \
1424 (((F) & ARM_TBFLAG_AARCH64_STATE_MASK) >> ARM_TBFLAG_AARCH64_STATE_SHIFT)
1425 #define ARM_TBFLAG_THUMB(F) \
1426 (((F) & ARM_TBFLAG_THUMB_MASK) >> ARM_TBFLAG_THUMB_SHIFT)
1427 #define ARM_TBFLAG_VECLEN(F) \
1428 (((F) & ARM_TBFLAG_VECLEN_MASK) >> ARM_TBFLAG_VECLEN_SHIFT)
1429 #define ARM_TBFLAG_VECSTRIDE(F) \
1430 (((F) & ARM_TBFLAG_VECSTRIDE_MASK) >> ARM_TBFLAG_VECSTRIDE_SHIFT)
1431 #define ARM_TBFLAG_PRIV(F) \
1432 (((F) & ARM_TBFLAG_PRIV_MASK) >> ARM_TBFLAG_PRIV_SHIFT)
1433 #define ARM_TBFLAG_VFPEN(F) \
1434 (((F) & ARM_TBFLAG_VFPEN_MASK) >> ARM_TBFLAG_VFPEN_SHIFT)
1435 #define ARM_TBFLAG_CONDEXEC(F) \
1436 (((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT)
1437 #define ARM_TBFLAG_BSWAP_CODE(F) \
1438 (((F) & ARM_TBFLAG_BSWAP_CODE_MASK) >> ARM_TBFLAG_BSWAP_CODE_SHIFT)
1439 #define ARM_TBFLAG_CPACR_FPEN(F) \
1440 (((F) & ARM_TBFLAG_CPACR_FPEN_MASK) >> ARM_TBFLAG_CPACR_FPEN_SHIFT)
1441 #define ARM_TBFLAG_SS_ACTIVE(F) \
1442 (((F) & ARM_TBFLAG_SS_ACTIVE_MASK) >> ARM_TBFLAG_SS_ACTIVE_SHIFT)
1443 #define ARM_TBFLAG_PSTATE_SS(F) \
1444 (((F) & ARM_TBFLAG_PSTATE_SS_MASK) >> ARM_TBFLAG_PSTATE_SS_SHIFT)
1445 #define ARM_TBFLAG_XSCALE_CPAR(F) \
1446 (((F) & ARM_TBFLAG_XSCALE_CPAR_MASK) >> ARM_TBFLAG_XSCALE_CPAR_SHIFT)
1447 #define ARM_TBFLAG_AA64_EL(F) \
1448 (((F) & ARM_TBFLAG_AA64_EL_MASK) >> ARM_TBFLAG_AA64_EL_SHIFT)
1449 #define ARM_TBFLAG_AA64_FPEN(F) \
1450 (((F) & ARM_TBFLAG_AA64_FPEN_MASK) >> ARM_TBFLAG_AA64_FPEN_SHIFT)
1451 #define ARM_TBFLAG_AA64_SS_ACTIVE(F) \
1452 (((F) & ARM_TBFLAG_AA64_SS_ACTIVE_MASK) >> ARM_TBFLAG_AA64_SS_ACTIVE_SHIFT)
1453 #define ARM_TBFLAG_AA64_PSTATE_SS(F) \
1454 (((F) & ARM_TBFLAG_AA64_PSTATE_SS_MASK) >> ARM_TBFLAG_AA64_PSTATE_SS_SHIFT)
1455
cpu_get_tb_cpu_state(CPUARMState * env,target_ulong * pc,target_ulong * cs_base,int * flags)1456 static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
1457 target_ulong *cs_base, int *flags)
1458 {
1459 int fpen;
1460
1461 if (arm_feature(env, ARM_FEATURE_V6)) {
1462 fpen = extract32(env->cp15.c1_coproc, 20, 2);
1463 } else {
1464 /* CPACR doesn't exist before v6, so VFP is always accessible */
1465 fpen = 3;
1466 }
1467
1468 if (is_a64(env)) {
1469 *pc = env->pc;
1470 *flags = ARM_TBFLAG_AARCH64_STATE_MASK
1471 | (arm_current_el(env) << ARM_TBFLAG_AA64_EL_SHIFT);
1472 if (fpen == 3 || (fpen == 1 && arm_current_el(env) != 0)) {
1473 *flags |= ARM_TBFLAG_AA64_FPEN_MASK;
1474 }
1475 /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine
1476 * states defined in the ARM ARM for software singlestep:
1477 * SS_ACTIVE PSTATE.SS State
1478 * 0 x Inactive (the TB flag for SS is always 0)
1479 * 1 0 Active-pending
1480 * 1 1 Active-not-pending
1481 */
1482 if (arm_singlestep_active(env)) {
1483 *flags |= ARM_TBFLAG_AA64_SS_ACTIVE_MASK;
1484 if (env->pstate & PSTATE_SS) {
1485 *flags |= ARM_TBFLAG_AA64_PSTATE_SS_MASK;
1486 }
1487 }
1488 } else {
1489 int privmode;
1490 *pc = env->regs[15];
1491 *flags = (env->thumb << ARM_TBFLAG_THUMB_SHIFT)
1492 | (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT)
1493 | (env->vfp.vec_stride << ARM_TBFLAG_VECSTRIDE_SHIFT)
1494 | (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT)
1495 | (env->bswap_code << ARM_TBFLAG_BSWAP_CODE_SHIFT);
1496 if (arm_feature(env, ARM_FEATURE_M)) {
1497 privmode = !((env->v7m.exception == 0) && (env->v7m.control & 1));
1498 } else {
1499 privmode = (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR;
1500 }
1501 if (privmode) {
1502 *flags |= ARM_TBFLAG_PRIV_MASK;
1503 }
1504 if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)
1505 || arm_el_is_aa64(env, 1)) {
1506 *flags |= ARM_TBFLAG_VFPEN_MASK;
1507 }
1508 if (fpen == 3 || (fpen == 1 && arm_current_el(env) != 0)) {
1509 *flags |= ARM_TBFLAG_CPACR_FPEN_MASK;
1510 }
1511 /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine
1512 * states defined in the ARM ARM for software singlestep:
1513 * SS_ACTIVE PSTATE.SS State
1514 * 0 x Inactive (the TB flag for SS is always 0)
1515 * 1 0 Active-pending
1516 * 1 1 Active-not-pending
1517 */
1518 if (arm_singlestep_active(env)) {
1519 *flags |= ARM_TBFLAG_SS_ACTIVE_MASK;
1520 if (env->uncached_cpsr & PSTATE_SS) {
1521 *flags |= ARM_TBFLAG_PSTATE_SS_MASK;
1522 }
1523 }
1524 *flags |= (extract32(env->cp15.c15_cpar, 0, 2)
1525 << ARM_TBFLAG_XSCALE_CPAR_SHIFT);
1526 }
1527
1528 *cs_base = 0;
1529 }
1530
1531 #include "exec/exec-all.h"
1532
cpu_pc_from_tb(CPUARMState * env,TranslationBlock * tb)1533 static inline void cpu_pc_from_tb(CPUARMState *env, TranslationBlock *tb)
1534 {
1535 if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) {
1536 env->pc = tb->pc;
1537 } else {
1538 env->regs[15] = tb->pc;
1539 }
1540 }
1541
1542 enum {
1543 QEMU_PSCI_CONDUIT_DISABLED = 0,
1544 QEMU_PSCI_CONDUIT_SMC = 1,
1545 QEMU_PSCI_CONDUIT_HVC = 2,
1546 };
1547
1548 #endif
1549