1 /* Constants and bitmasks for DEC Control/Status Register emulation. 2 Copyright 2003 Brian R. Gaeke. 3 4 This file is part of VMIPS. 5 6 VMIPS is free software; you can redistribute it and/or modify it 7 under the terms of the GNU General Public License as published by the 8 Free Software Foundation; either version 2 of the License, or (at your 9 option) any later version. 10 11 VMIPS is distributed in the hope that it will be useful, but 12 WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14 for more details. 15 16 You should have received a copy of the GNU General Public License along 17 with VMIPS; if not, write to the Free Software Foundation, Inc., 18 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. */ 19 20 #ifndef _DECCSRREG_H_ 21 #define _DECCSRREG_H_ 22 23 /* Default physical address for the DEC CSR */ 24 #define DECCSR_BASE 0x1ff00000 25 26 /* Fields marked (read-only) should be written as zero. */ 27 #define CSR_RSRVD 0xf0000000 /* Reserved (r/o) */ 28 #define CSR_PSWARN 0x08000000 /* Overheat sensor warning (0=normal) (r/o) */ 29 #define CSR_PRSVNVR 0x04000000 /* 0=reinitialize NVRAM, 1=normal (r/o) */ 30 #define CSR_REFEVEN 0x02000000 /* Which DRAM bank to refresh next cycle (r/o) */ 31 #define CSR_NRMMOD 0x01000000 /* 1=normal POST tests, 0=mfr tests (r/o) */ 32 33 #define CSR_IOINTEN 0x00ff0000 /* I/O slot interrupt enables (r/w) */ 34 #define CSR_ECCMD 0x0000c000 /* ECC logic operation mode (r/w) */ 35 #define CSR_CORRECT 0x00002000 /* 0=ECC off, 1=ECC on (r/w) */ 36 #define CSR_LEDIAG 0x00001000 /* ECC diagnostic data latch (r/w) */ 37 #define CSR_TXDIS 0x00000800 /* Disable serial line EIA drivers (r/w) */ 38 #define CSR_BNK32M 0x00000400 /* Memory bank stride: 0=8MB, 1=32MB (r/w) */ 39 #define CSR_DIAGDN 0x00000200 /* Diagnostics done (r/w) */ 40 #define CSR_BAUD38 0x00000100 /* 0=19.2Kbps, 1=38.4Kbps on DZ serial (r/w) */ 41 #define CSR_RW_BITS 0x00ffff00 /* (all of the above r/w fields.) */ 42 43 #define CSR_IOINT 0x000000ff /* I/O slot interrupt signals (r/o) */ 44 #define CSR_LEDS 0x000000ff /* State of diagnostic LEDs (w/o) */ 45 46 #endif /* _DECCSRREG_H_ */ 47