1 /* Constants, registers & bitmasks for DZ11 DEC 5000/200 serial chip emulation. 2 Copyright 2003 Brian R. Gaeke. 3 4 This file is part of VMIPS. 5 6 VMIPS is free software; you can redistribute it and/or modify it 7 under the terms of the GNU General Public License as published by the 8 Free Software Foundation; either version 2 of the License, or (at your 9 option) any later version. 10 11 VMIPS is distributed in the hope that it will be useful, but 12 WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14 for more details. 15 16 You should have received a copy of the GNU General Public License along 17 with VMIPS; if not, write to the Free Software Foundation, Inc., 18 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. */ 19 20 #ifndef _DECSERIALREG_H_ 21 #define _DECSERIALREG_H_ 22 23 #define DECSERIAL_BASE 0x1fe00000 24 #define DECSERIAL_ADDR 0xbfe00000 25 #define DZ_CSR 0x00 /* R/W; Control and status register */ 26 #define DZ_CSR_TRDY 0x8000 /* Transmitter ready */ 27 #define DZ_CSR_TIE 0x4000 /* Transmitter interrupt enable */ 28 #define DZ_CSR_TLINE 0x0300 /* Transmitter line select (0...3) */ 29 #define DZ_CSR_RDONE 0x0080 /* Receiver done (ready) */ 30 #define DZ_CSR_RIE 0x0040 /* Receiver Interrupt Enable */ 31 #define DZ_CSR_MSE 0x0020 /* Master Scan Enable */ 32 #define DZ_CSR_CLR 0x0010 /* Master Clear */ 33 #define DZ_CSR_MAINT 0x0008 /* Maintenance mode - loopback output->input. */ 34 35 #define DZ_RBUF 0x08 /* R; Receiver buffer */ 36 #define DZ_RBUF_DVAL 0x8000 /* Data valid */ 37 #define DZ_RBUF_OERR 0x4000 /* Overrun error */ 38 #define DZ_RBUF_FERR 0x2000 /* Framing error */ 39 #define DZ_RBUF_PERR 0x1000 /* Parity error */ 40 #define DZ_RBUF_RLINE 0x0300 /* Received line number */ 41 #define DZ_RBUF_RBUF 0x00ff /* Received character */ 42 43 #define DZ_LPR 0x08 /* W; Line parameters */ 44 #define DZ_LPR_RXENAB 0x1000 45 #define DZ_LPR_SC 0x0f00 46 #define DZ_LPR_ODDPAR 0x0080 47 #define DZ_LPR_PARENB 0x0040 48 #define DZ_LPR_STOP 0x0020 49 #define DZ_LPR_CHAR 0x0018 50 #define DZ_LPR_LINE 0x0003 51 52 #define DZ_TCR 0x10 /* R/W; Transmitter control */ 53 #define DZ_TCR_RTS2 0x0800 54 #define DZ_TCR_DTR2 0x0400 55 #define DZ_TCR_RTS3 0x0200 56 #define DZ_TCR_DTR3 0x0100 57 #define DZ_TCR_LNENB3 0x0008 58 #define DZ_TCR_LNENB2 0x0004 59 #define DZ_TCR_LNENB1 0x0002 60 #define DZ_TCR_LNENB0 0x0001 61 62 #define DZ_MSR 0x18 /* R; Modem status */ 63 #define DZ_MSR_RI2 0x0800 64 #define DZ_MSR_CD2 0x0400 65 #define DZ_MSR_DSR2 0x0200 66 #define DZ_MSR_CTS2 0x0100 67 #define DZ_MSR_RI3 0x0008 68 #define DZ_MSR_CD3 0x0004 69 #define DZ_MSR_DSR3 0x0002 70 #define DZ_MSR_CTS3 0x0001 71 72 #define DZ_TDR 0x18 /* W; Transmit data */ 73 #define DZ_TDR_BRK 0x0f00 /* break on line 3 ... 0 */ 74 #define DZ_TDR_TBUF 0x00ff /* Transmitter buffer */ 75 76 #endif /* _DECSERIALREG_H_ */ 77