1 /* pdp11_defs.h: PDP-11 simulator definitions 2 3 Copyright (c) 1993-1997, 4 Robert M Supnik, Digital Equipment Corporation 5 Commercial use prohibited 6 7 The author gratefully acknowledges the help of Max Burnet, Megan Gentry, 8 and John Wilson in resolving questions about the PDP-11 9 */ 10 11 #include "sim_defs.h" /* simulator defns */ 12 #include <setjmp.h> 13 #ifdef PRO 14 #include "pro_defs.h" 15 #endif 16 17 /* Constants */ 18 19 #define STKLIM 0400 /* stack limit */ 20 #define VASIZE 0200000 /* 2**16 */ 21 #define VAMASK (VASIZE - 1) /* 2**16 - 1 */ 22 #ifdef PRO 23 #if (PRO_BASE_1M == 0) 24 #define INIMEMSIZE 001000000 /* 256K */ 25 #else 26 #define INIMEMSIZE 004000000 /* 1M */ 27 #endif 28 #else 29 #define INIMEMSIZE 001000000 /* 2**18 */ 30 #endif 31 32 /* XXX IOPAGEBASE changed for PRO */ 33 #ifdef PRO 34 #define IOPAGEBASE 014000000 /* XXX kludge for video */ 35 /* 36 #define IOPAGEBASE 017730000 37 */ 38 #else 39 #define IOPAGEBASE 017760000 /* 2**22 - 2**13 */ 40 #endif 41 42 #define MAXMEMSIZE 020000000 /* 2**22 */ 43 #define MEMSIZE (cpu_unit.capac) 44 45 /* Protection modes */ 46 47 #define KERNEL 0 48 #define SUPER 1 49 #define UNUSED 2 50 #define USER 3 51 52 /* I/O access modes */ 53 54 #define READ 0 55 #define READC 1 /* read console */ 56 #define WRITE 2 57 #define WRITEC 3 /* write console */ 58 #define WRITEB 4 59 60 /* PSW */ 61 62 #define PSW_V_C 0 /* condition codes */ 63 #define PSW_V_V 1 64 #define PSW_V_Z 2 65 #define PSW_V_N 3 66 #define PSW_V_TBIT 4 /* trace trap */ 67 #define PSW_V_IPL 5 /* int priority */ 68 #define PSW_V_RS 11 /* register set */ 69 #define PSW_V_PM 12 /* previous mode */ 70 #define PSW_V_CM 14 /* current mode */ 71 #define PSW_RW 0174357 /* read/write bits */ 72 73 /* FPS */ 74 75 #define FPS_V_C 0 /* condition codes */ 76 #define FPS_V_V 1 77 #define FPS_V_Z 2 78 #define FPS_V_N 3 79 #define FPS_V_T 5 /* truncate */ 80 #define FPS_V_L 6 /* long */ 81 #define FPS_V_D 7 /* double */ 82 #define FPS_V_IC 8 /* ic err int */ 83 #define FPS_V_IV 9 /* overflo err int */ 84 #define FPS_V_IU 10 /* underflo err int */ 85 #define FPS_V_IUV 11 /* undef var err int */ 86 #define FPS_V_ID 14 /* int disable */ 87 #define FPS_V_ER 15 /* error */ 88 89 /* PIRQ */ 90 91 #define PIRQ_PIR1 0001000 92 #define PIRQ_PIR2 0002000 93 #define PIRQ_PIR3 0004000 94 #define PIRQ_PIR4 0010000 95 #define PIRQ_PIR5 0020000 96 #define PIRQ_PIR6 0040000 97 #define PIRQ_PIR7 0100000 98 #define PIRQ_IMP 0177356 /* implemented bits */ 99 #define PIRQ_RW 0177000 /* read/write bits */ 100 101 /* MMR0 */ 102 103 #define MMR0_MME 0000001 /* mem mgt enable */ 104 #define MMR0_V_PAGE 1 /* offset to pageno */ 105 #define MMR0_RO 0020000 /* read only error */ 106 #define MMR0_PL 0040000 /* page lnt error */ 107 #define MMR0_NR 0100000 /* no access error */ 108 #define MMR0_FREEZE 0160000 /* if set, no update */ 109 #define MMR0_IMP 0160177 /* implemented bits */ 110 #define MMR0_RW 0160001 /* read/write bits */ 111 112 /* MMR3 */ 113 114 #define MMR3_UDS 001 /* user dspace enbl */ 115 #define MMR3_SDS 002 /* super dspace enbl */ 116 #define MMR3_KDS 004 /* krnl dspace enbl */ 117 #define MMR3_CSM 010 /* CSM enable */ 118 #define MMR3_M22E 020 /* 22b mem mgt enbl */ 119 #define MMR3_BME 040 /* DMA bus map enbl */ 120 #define MMR3_IMP 077 /* implemented bits */ 121 #ifdef PRO 122 /* The 350's F11 does not implement the 3 LSBs */ 123 #define MMR3_RW 070 /* read/write bits */ 124 #else 125 #define MMR3_RW 077 /* read/write bits */ 126 #endif 127 128 /* PDR */ 129 130 #define PDR_NR 0000002 /* non-resident ACF */ 131 #define PDR_WE 0000004 /* XXX write-enable ACF */ 132 #define PDR_ED 0000010 /* expansion dir */ 133 #define PDR_W 0000100 /* written flag */ 134 #define PDR_PLF 0077400 /* page lnt field */ 135 #define PDR_IMP 0177516 /* implemented bits */ 136 #define PDR_RW 0177416 /* read/write bits */ 137 138 /* Virtual address */ 139 140 #define VA_DF 0017777 /* displacement */ 141 #define VA_BN 0017700 /* block number */ 142 #define VA_V_APF 13 /* offset to APF */ 143 #define VA_V_DS 16 /* offset to space */ 144 #define VA_V_MODE 17 /* offset to mode */ 145 #define VA_DS (1u << VA_V_DS) /* data space flag */ 146 147 /* CPUERR */ 148 149 #define CPUE_RED 0004 /* red stack */ 150 #define CPUE_YEL 0010 /* yellow stack */ 151 #define CPUE_TMO 0020 /* IO page nxm */ 152 #define CPUE_NXM 0040 /* memory nxm */ 153 #define CPUE_ODD 0100 /* odd address */ 154 #define CPUE_HALT 0200 /* HALT not kernel */ 155 #define CPUE_IMP 0374 /* implemented bits */ 156 157 /* Floating point accumulators */ 158 159 struct fpac { 160 unsigned int32 l; /* low 32b */ 161 unsigned int32 h; /* high 32b */ 162 }; 163 typedef struct fpac fpac_t; 164 165 /* Device CSRs */ 166 167 #define CSR_V_GO 0 /* go */ 168 #define CSR_V_IE 6 /* interrupt enable */ 169 #define CSR_V_DONE 7 /* done */ 170 #define CSR_V_BUSY 11 /* busy */ 171 #define CSR_V_ERR 15 /* error */ 172 #define CSR_GO (1u << CSR_V_GO) 173 #define CSR_IE (1u << CSR_V_IE) 174 #define CSR_DONE (1u << CSR_V_DONE) 175 #define CSR_BUSY (1u << CSR_V_BUSY) 176 #define CSR_ERR (1u << CSR_V_ERR) 177 178 /* Simulator stop codes; codes 1:TRAP_V_MAX correspond to traps 0:TRAPMAX-1 */ 179 180 #define STOP_HALT TRAP_V_MAX + 1 /* HALT instruction */ 181 #define STOP_IBKPT TRAP_V_MAX + 2 /* instruction bkpt */ 182 #define STOP_WAIT TRAP_V_MAX + 3 /* wait, no events */ 183 #define STOP_VECABORT TRAP_V_MAX + 4 /* abort vector read */ 184 #define STOP_SPABORT TRAP_V_MAX + 5 /* abort trap push */ 185 #define IORETURN(f,v) ((f)? (v): SCPE_OK) /* cond error return */ 186 187 /* Trap masks, descending priority order, following J-11 188 An interrupt summary bit is kept with traps, to minimize overhead 189 */ 190 191 #define TRAP_V_RED 0 /* red stk abort 4 */ 192 #define TRAP_V_ODD 1 /* odd address 4 */ 193 #define TRAP_V_MME 2 /* mem mgt 250 */ 194 #define TRAP_V_NXM 3 /* nx memory 4 */ 195 #define TRAP_V_PAR 4 /* parity err 114 */ 196 #define TRAP_V_PRV 5 /* priv inst 4 */ 197 #define TRAP_V_ILL 6 /* illegal inst 10 */ 198 #define TRAP_V_BPT 7 /* BPT 14 */ 199 #define TRAP_V_IOT 8 /* IOT 20 */ 200 #define TRAP_V_EMT 9 /* EMT 30 */ 201 #define TRAP_V_TRAP 10 /* TRAP 34 */ 202 #define TRAP_V_TRC 11 /* T bit 14 */ 203 #define TRAP_V_YEL 12 /* stack 4 */ 204 #define TRAP_V_PWRFL 13 /* power fail 24 */ 205 #define TRAP_V_FPE 14 /* fpe 244 */ 206 #define TRAP_V_MAX 15 /* intr = max trp # */ 207 #define TRAP_RED (1u << TRAP_V_RED) 208 #define TRAP_ODD (1u << TRAP_V_ODD) 209 #define TRAP_MME (1u << TRAP_V_MME) 210 #define TRAP_NXM (1u << TRAP_V_NXM) 211 #define TRAP_PAR (1u << TRAP_V_PAR) 212 #define TRAP_PRV (1u << TRAP_V_PRV) 213 #define TRAP_ILL (1u << TRAP_V_ILL) 214 #define TRAP_BPT (1u << TRAP_V_BPT) 215 #define TRAP_IOT (1u << TRAP_V_IOT) 216 #define TRAP_EMT (1u << TRAP_V_EMT) 217 #define TRAP_TRAP (1u << TRAP_V_TRAP) 218 #define TRAP_TRC (1u << TRAP_V_TRC) 219 #define TRAP_YEL (1u << TRAP_V_YEL) 220 #define TRAP_PWRFL (1u << TRAP_V_PWRFL) 221 #define TRAP_FPE (1u << TRAP_V_FPE) 222 #define TRAP_INT (1u << TRAP_V_MAX) 223 #define TRAP_ALL ((1u << TRAP_V_MAX) - 1) /* all traps */ 224 225 #define VEC_RED 0004 /* trap vectors */ 226 #define VEC_ODD 0004 227 #define VEC_MME 0250 228 #define VEC_NXM 0004 229 #define VEC_PAR 0114 230 #define VEC_PRV 0004 231 #define VEC_ILL 0010 232 #define VEC_BPT 0014 233 #define VEC_IOT 0020 234 #define VEC_EMT 0030 235 #define VEC_TRAP 0034 236 #define VEC_TRC 0014 237 #define VEC_YEL 0004 238 #define VEC_PWRFL 0024 239 #define VEC_FPE 0244 240 241 /* Interrupt assignments, priority is right to left 242 243 <3:0> = BR7, <3> = PIR7 244 <7:4> = BR6, <7> = PIR6 245 <15:8> = BR5, <15> = PIR5 246 <28:16> = BR4, <28> = PIR4 247 <29> = PIR3 248 <30> = PIR2 249 <31> = PIR1 250 */ 251 252 #define INT_V_PIR7 3 253 #define INT_V_CLK 4 254 #define INT_V_PIR6 7 255 #define INT_V_RK 8 256 #define INT_V_RL 9 257 #define INT_V_RX 10 258 #define INT_V_TM 11 259 #define INT_V_RP 12 260 #define INT_V_PIR5 15 261 #define INT_V_TTI 16 262 #define INT_V_TTO 17 263 #define INT_V_PTR 18 264 #define INT_V_PTP 19 265 #define INT_V_LPT 20 266 #define INT_V_PIR4 28 267 #define INT_V_PIR3 29 268 #define INT_V_PIR2 30 269 #define INT_V_PIR1 31 270 271 #define INT_PIR7 (1u << INT_V_PIR7) 272 #define INT_CLK (1u << INT_V_CLK) 273 #define INT_PIR6 (1u << INT_V_PIR6) 274 #define INT_RK (1u << INT_V_RK) 275 #define INT_RL (1u << INT_V_RL) 276 #define INT_RX (1u << INT_V_RX) 277 #define INT_TM (1u << INT_V_TM) 278 #define INT_RP (1u << INT_V_RP) 279 #define INT_PIR5 (1u << INT_V_PIR5) 280 #define INT_PTR (1u << INT_V_PTR) 281 #define INT_PTP (1u << INT_V_PTP) 282 #define INT_TTI (1u << INT_V_TTI) 283 #define INT_TTO (1u << INT_V_TTO) 284 #define INT_LPT (1u << INT_V_LPT) 285 #define INT_PIR4 (1u << INT_V_PIR4) 286 #define INT_PIR3 (1u << INT_V_PIR3) 287 #define INT_PIR2 (1u << INT_V_PIR2) 288 #define INT_PIR1 (1u << INT_V_PIR1) 289 290 #define INT_IPL7 0x00000000 /* int level masks */ 291 #define INT_IPL6 0x0000000F 292 #define INT_IPL5 0x000000FF 293 #define INT_IPL4 0x0000FFFF 294 #define INT_IPL3 0x1FFFFFFF 295 #define INT_IPL2 0x3FFFFFFF 296 #define INT_IPL1 0x7FFFFFFF 297 #define INT_IPL0 0xFFFFFFFF 298 299 #define VEC_PIRQ 0240 /* interrupt vectors */ 300 #define VEC_TTI 0060 301 #define VEC_TTO 0064 302 #define VEC_PTR 0070 303 #define VEC_PTP 0074 304 #define VEC_CLK 0100 305 #define VEC_LPT 0200 306 #define VEC_RK 0220 307 #define VEC_RL 0160 308 #define VEC_RX 0264 309 #define VEC_TM 0224 310 #define VEC_RP 0254 311 312 /* CPU and FPU macros */ 313 314 #define update_MM ((MMR0 & (MMR0_FREEZE + MMR0_MME)) == MMR0_MME) 315 #define setTRAP(name) trap_req = trap_req | (name) 316 #define setCPUERR(name) CPUERR = CPUERR | (name) 317 #define ABORT(val) longjmp (save_env, (val)) 318 #define SP R[6] 319 #define PC R[7] 320