1 /*
2 **
3 ** File: fmopl.c - software implementation of FM sound generator
4 ** types OPL and OPL2
5 **
6 ** Copyright (C) 2002,2003 Jarek Burczynski (bujar at mame dot net)
7 ** Copyright (C) 1999,2000 Tatsuyuki Satoh , MultiArcadeMachineEmulator development
8 **
9 ** Version 0.72
10 **
11
12 Revision History:
13
14 04-08-2003 Jarek Burczynski:
15 - removed BFRDY hack. BFRDY is busy flag, and it should be 0 only when the chip
16 handles memory read/write or during the adpcm synthesis when the chip
17 requests another byte of ADPCM data.
18
19 24-07-2003 Jarek Burczynski:
20 - added a small hack for Y8950 status BFRDY flag (bit 3 should be set after
21 some (unknown) delay). Right now it's always set.
22
23 14-06-2003 Jarek Burczynski:
24 - implemented all of the status register flags in Y8950 emulation
25 - renamed Y8950SetDeltaTMemory() parameters from _rom_ to _mem_ since
26 they can be either RAM or ROM
27
28 08-10-2002 Jarek Burczynski (thanks to Dox for the YM3526 chip)
29 - corrected YM3526Read() to always set bit 2 and bit 1
30 to HIGH state - identical to YM3812Read (verified on real YM3526)
31
32 04-28-2002 Jarek Burczynski:
33 - binary exact Envelope Generator (verified on real YM3812);
34 compared to YM2151: the EG clock is equal to internal_clock,
35 rates are 2 times slower and volume resolution is one bit less
36 - modified interface functions (they no longer return pointer -
37 that's internal to the emulator now):
38 - new wrapper functions for OPLCreate: YM3526Init(), YM3812Init() and Y8950Init()
39 - corrected 'off by one' error in feedback calculations (when feedback is off)
40 - enabled waveform usage (credit goes to Vlad Romascanu and zazzal22)
41 - speeded up noise generator calculations (Nicola Salmoria)
42
43 03-24-2002 Jarek Burczynski (thanks to Dox for the YM3812 chip)
44 Complete rewrite (all verified on real YM3812):
45 - corrected sin_tab and tl_tab data
46 - corrected operator output calculations
47 - corrected waveform_select_enable register;
48 simply: ignore all writes to waveform_select register when
49 waveform_select_enable == 0 and do not change the waveform previously selected.
50 - corrected KSR handling
51 - corrected Envelope Generator: attack shape, Sustain mode and
52 Percussive/Non-percussive modes handling
53 - Envelope Generator rates are two times slower now
54 - LFO amplitude (tremolo) and phase modulation (vibrato)
55 - rhythm sounds phase generation
56 - white noise generator (big thanks to Olivier Galibert for mentioning Berlekamp-Massey algorithm)
57 - corrected key on/off handling (the 'key' signal is ORed from three sources: FM, rhythm and CSM)
58 - funky details (like ignoring output of operator 1 in BD rhythm sound when connect == 1)
59
60 12-28-2001 Acho A. Tang
61 - reflected Delta-T EOS status on Y8950 status port.
62 - fixed subscription range of attack/decay tables
63
64
65 To do:
66 add delay before key off in CSM mode (see CSMKeyControll)
67 verify volume of the FM part on the Y8950
68 */
69
70 #include <stdio.h>
71 #include <stdlib.h>
72 #include <math.h>
73
74 #include "driver.h" /* use M.A.M.E. */
75 #include "state.h"
76
77 #include "ymdeltat.h"
78
79 #include "fmopl.h"
80
81 #ifndef PI
82 #define PI 3.14159265358979323846
83 #endif
84
85
86
87 /* output final shift */
88 #if (OPL_SAMPLE_BITS==16)
89 #define FINAL_SH (0)
90 #define MAXOUT (+32767)
91 #define MINOUT (-32768)
92 #else
93 #define FINAL_SH (8)
94 #define MAXOUT (+127)
95 #define MINOUT (-128)
96 #endif
97
98
99 #define FREQ_SH 16 /* 16.16 fixed point (frequency calculations) */
100 #define EG_SH 16 /* 16.16 fixed point (EG timing) */
101 #define LFO_SH 24 /* 8.24 fixed point (LFO calculations) */
102 #define TIMER_SH 16 /* 16.16 fixed point (timers calculations) */
103
104 #define FREQ_MASK ((1<<FREQ_SH)-1)
105
106 /* envelope output entries */
107 #define ENV_BITS 10
108 #define ENV_LEN (1<<ENV_BITS)
109 #define ENV_STEP (128.0/ENV_LEN)
110
111 #define MAX_ATT_INDEX ((1<<(ENV_BITS-1))-1) /*511*/
112 #define MIN_ATT_INDEX (0)
113
114 /* sinwave entries */
115 #define SIN_BITS 10
116 #define SIN_LEN (1<<SIN_BITS)
117 #define SIN_MASK (SIN_LEN-1)
118
119 #define TL_RES_LEN (256) /* 8 bits addressing (real chip) */
120
121
122
123 /* register number to channel number , slot offset */
124 #define SLOT1 0
125 #define SLOT2 1
126
127 /* Envelope Generator phases */
128
129 #define EG_ATT 4
130 #define EG_DEC 3
131 #define EG_SUS 2
132 #define EG_REL 1
133 #define EG_OFF 0
134
135
136 /* save output as raw 16-bit sample */
137
138 /*#define SAVE_SAMPLE*/
139
140 #ifdef SAVE_SAMPLE
acc_calc(signed int value)141 INLINE signed int acc_calc(signed int value)
142 {
143 if (value>=0)
144 {
145 if (value < 0x0200)
146 return (value & ~0);
147 if (value < 0x0400)
148 return (value & ~1);
149 if (value < 0x0800)
150 return (value & ~3);
151 if (value < 0x1000)
152 return (value & ~7);
153 if (value < 0x2000)
154 return (value & ~15);
155 if (value < 0x4000)
156 return (value & ~31);
157 return (value & ~63);
158 }
159 /*else value < 0*/
160 if (value > -0x0200)
161 return (~abs(value) & ~0);
162 if (value > -0x0400)
163 return (~abs(value) & ~1);
164 if (value > -0x0800)
165 return (~abs(value) & ~3);
166 if (value > -0x1000)
167 return (~abs(value) & ~7);
168 if (value > -0x2000)
169 return (~abs(value) & ~15);
170 if (value > -0x4000)
171 return (~abs(value) & ~31);
172 return (~abs(value) & ~63);
173 }
174
175
176 static FILE *sample[1];
177 #if 1 /*save to MONO file */
178 #define SAVE_ALL_CHANNELS \
179 { signed int pom = acc_calc(lt); \
180 fputc((unsigned short)pom&0xff,sample[0]); \
181 fputc(((unsigned short)pom>>8)&0xff,sample[0]); \
182 }
183 #else /*save to STEREO file */
184 #define SAVE_ALL_CHANNELS \
185 { signed int pom = lt; \
186 fputc((unsigned short)pom&0xff,sample[0]); \
187 fputc(((unsigned short)pom>>8)&0xff,sample[0]); \
188 pom = rt; \
189 fputc((unsigned short)pom&0xff,sample[0]); \
190 fputc(((unsigned short)pom>>8)&0xff,sample[0]); \
191 }
192 #endif
193 #endif
194
195 /* #define LOG_CYM_FILE */
196 #ifdef LOG_CYM_FILE
197 FILE * cymfile = NULL;
198 #endif
199
200
201
202 #define OPL_TYPE_WAVESEL 0x01 /* waveform select */
203 #define OPL_TYPE_ADPCM 0x02 /* DELTA-T ADPCM unit */
204 #define OPL_TYPE_KEYBOARD 0x04 /* keyboard interface */
205 #define OPL_TYPE_IO 0x08 /* I/O port */
206
207 /* ---------- Generic interface section ---------- */
208 #define OPL_TYPE_YM3526 (0)
209 #define OPL_TYPE_YM3812 (OPL_TYPE_WAVESEL)
210 #define OPL_TYPE_Y8950 (OPL_TYPE_ADPCM|OPL_TYPE_KEYBOARD|OPL_TYPE_IO)
211
212
213
214 typedef struct{
215 UINT32 ar; /* attack rate: AR<<2 */
216 UINT32 dr; /* decay rate: DR<<2 */
217 UINT32 rr; /* release rate:RR<<2 */
218 UINT8 KSR; /* key scale rate */
219 UINT8 ksl; /* keyscale level */
220 UINT8 ksr; /* key scale rate: kcode>>KSR */
221 UINT8 mul; /* multiple: mul_tab[ML] */
222
223 /* Phase Generator */
224 UINT32 Cnt; /* frequency counter */
225 UINT32 Incr; /* frequency counter step */
226 UINT8 FB; /* feedback shift value */
227 INT32 *connect1; /* slot1 output pointer */
228 INT32 op1_out[2]; /* slot1 output for feedback */
229 UINT8 CON; /* connection (algorithm) type */
230
231 /* Envelope Generator */
232 UINT8 eg_type; /* percussive/non-percussive mode */
233 UINT8 state; /* phase type */
234 UINT32 TL; /* total level: TL << 2 */
235 INT32 TLL; /* adjusted now TL */
236 INT32 volume; /* envelope counter */
237 UINT32 sl; /* sustain level: sl_tab[SL] */
238 UINT8 eg_sh_ar; /* (attack state) */
239 UINT8 eg_sel_ar; /* (attack state) */
240 UINT8 eg_sh_dr; /* (decay state) */
241 UINT8 eg_sel_dr; /* (decay state) */
242 UINT8 eg_sh_rr; /* (release state) */
243 UINT8 eg_sel_rr; /* (release state) */
244 UINT32 key; /* 0 = KEY OFF, >0 = KEY ON */
245
246 /* LFO */
247 UINT32 AMmask; /* LFO Amplitude Modulation enable mask */
248 UINT8 vib; /* LFO Phase Modulation enable flag (active high)*/
249
250 /* waveform select */
251 UINT32 wavetable;
252 } OPL_SLOT;
253
254 typedef struct{
255 OPL_SLOT SLOT[2];
256 /* phase generator state */
257 UINT32 block_fnum; /* block+fnum */
258 UINT32 fc; /* Freq. Increment base */
259 UINT32 ksl_base; /* KeyScaleLevel Base step */
260 UINT8 kcode; /* key code (for key scaling) */
261 } OPL_CH;
262
263 /* OPL state */
264 typedef struct fm_opl_f {
265 /* FM channel slots */
266 OPL_CH P_CH[9]; /* OPL/OPL2 chips have 9 channels*/
267
268 UINT32 eg_cnt; /* global envelope generator counter */
269 UINT32 eg_timer; /* global envelope generator counter works at frequency = chipclock/72 */
270 UINT32 eg_timer_add; /* step of eg_timer */
271 UINT32 eg_timer_overflow; /* envelope generator timer overlfows every 1 sample (on real chip) */
272
273 UINT8 rhythm; /* Rhythm mode */
274
275 UINT32 fn_tab[1024]; /* fnumber->increment counter */
276
277 /* LFO */
278 UINT32 LFO_AM;
279 INT32 LFO_PM;
280
281 UINT8 lfo_am_depth;
282 UINT8 lfo_pm_depth_range;
283 UINT32 lfo_am_cnt;
284 UINT32 lfo_am_inc;
285 UINT32 lfo_pm_cnt;
286 UINT32 lfo_pm_inc;
287
288 UINT32 noise_rng; /* 23 bit noise shift register */
289 UINT32 noise_p; /* current noise 'phase' */
290 UINT32 noise_f; /* current noise period */
291
292 UINT8 wavesel; /* waveform select enable flag */
293
294 INT32 T[2]; /* timer counters */
295 UINT8 st[2]; /* timer enable */
296
297 #if BUILD_Y8950
298 /* Delta-T ADPCM unit (Y8950) */
299
300 YM_DELTAT *deltat;
301
302 /* Keyboard and I/O ports interface */
303 UINT8 portDirection;
304 UINT8 portLatch;
305 OPL_PORTHANDLER_R porthandler_r;
306 OPL_PORTHANDLER_W porthandler_w;
307 INT32 port_param;
308 OPL_PORTHANDLER_R keyboardhandler_r;
309 OPL_PORTHANDLER_W keyboardhandler_w;
310 INT32 keyboard_param;
311 #endif
312
313 /* external event callback handlers */
314 OPL_TIMERHANDLER TimerHandler; /* TIMER handler */
315 INT32 TimerParam; /* TIMER parameter */
316 OPL_IRQHANDLER IRQHandler; /* IRQ handler */
317 INT32 IRQParam; /* IRQ parameter */
318 OPL_UPDATEHANDLER UpdateHandler;/* stream update handler */
319 INT32 UpdateParam; /* stream update parameter */
320
321 UINT8 type; /* chip type */
322 UINT8 address; /* address register */
323 UINT8 status; /* status flag */
324 UINT8 statusmask; /* status mask */
325 UINT8 mode; /* Reg.08 : CSM,notesel,etc. */
326
327 INT32 clock; /* master clock (Hz) */
328 INT32 rate; /* sampling rate (Hz) */
329 double freqbase; /* frequency base */
330 double TimerBase; /* Timer base time (==sampling time)*/
331
332 INT32 phase_modulation; /* phase modulation input (SLOT 2) */
333 INT32 output[1];
334
335 #if BUILD_Y8950
336 INT32 output_deltat[4]; /* for Y8950 DELTA-T, chip is mono, that 4 here is just for safety */
337 #endif
338 } FM_OPL;
339
340
341
342 /* mapping of register number (offset) to slot number used by the emulator */
343 static const int slot_array[32]=
344 {
345 0, 2, 4, 1, 3, 5,-1,-1,
346 6, 8,10, 7, 9,11,-1,-1,
347 12,14,16,13,15,17,-1,-1,
348 -1,-1,-1,-1,-1,-1,-1,-1
349 };
350
351 /* key scale level */
352 /* table is 3dB/octave , DV converts this into 6dB/octave */
353 /* 0.1875 is bit 0 weight of the envelope counter (volume) expressed in the 'decibel' scale */
354 #define DV (0.1875/2.0)
355 static const UINT32 ksl_tab[8*16]=
356 {
357 /* OCT 0 */
358 0.000/DV, 0.000/DV, 0.000/DV, 0.000/DV,
359 0.000/DV, 0.000/DV, 0.000/DV, 0.000/DV,
360 0.000/DV, 0.000/DV, 0.000/DV, 0.000/DV,
361 0.000/DV, 0.000/DV, 0.000/DV, 0.000/DV,
362 /* OCT 1 */
363 0.000/DV, 0.000/DV, 0.000/DV, 0.000/DV,
364 0.000/DV, 0.000/DV, 0.000/DV, 0.000/DV,
365 0.000/DV, 0.750/DV, 1.125/DV, 1.500/DV,
366 1.875/DV, 2.250/DV, 2.625/DV, 3.000/DV,
367 /* OCT 2 */
368 0.000/DV, 0.000/DV, 0.000/DV, 0.000/DV,
369 0.000/DV, 1.125/DV, 1.875/DV, 2.625/DV,
370 3.000/DV, 3.750/DV, 4.125/DV, 4.500/DV,
371 4.875/DV, 5.250/DV, 5.625/DV, 6.000/DV,
372 /* OCT 3 */
373 0.000/DV, 0.000/DV, 0.000/DV, 1.875/DV,
374 3.000/DV, 4.125/DV, 4.875/DV, 5.625/DV,
375 6.000/DV, 6.750/DV, 7.125/DV, 7.500/DV,
376 7.875/DV, 8.250/DV, 8.625/DV, 9.000/DV,
377 /* OCT 4 */
378 0.000/DV, 0.000/DV, 3.000/DV, 4.875/DV,
379 6.000/DV, 7.125/DV, 7.875/DV, 8.625/DV,
380 9.000/DV, 9.750/DV,10.125/DV,10.500/DV,
381 10.875/DV,11.250/DV,11.625/DV,12.000/DV,
382 /* OCT 5 */
383 0.000/DV, 3.000/DV, 6.000/DV, 7.875/DV,
384 9.000/DV,10.125/DV,10.875/DV,11.625/DV,
385 12.000/DV,12.750/DV,13.125/DV,13.500/DV,
386 13.875/DV,14.250/DV,14.625/DV,15.000/DV,
387 /* OCT 6 */
388 0.000/DV, 6.000/DV, 9.000/DV,10.875/DV,
389 12.000/DV,13.125/DV,13.875/DV,14.625/DV,
390 15.000/DV,15.750/DV,16.125/DV,16.500/DV,
391 16.875/DV,17.250/DV,17.625/DV,18.000/DV,
392 /* OCT 7 */
393 0.000/DV, 9.000/DV,12.000/DV,13.875/DV,
394 15.000/DV,16.125/DV,16.875/DV,17.625/DV,
395 18.000/DV,18.750/DV,19.125/DV,19.500/DV,
396 19.875/DV,20.250/DV,20.625/DV,21.000/DV
397 };
398 #undef DV
399
400 /* sustain level table (3dB per step) */
401 /* 0 - 15: 0, 3, 6, 9,12,15,18,21,24,27,30,33,36,39,42,93 (dB)*/
402 #define SC(db) (UINT32) ( db * (2.0/ENV_STEP) )
403 static const UINT32 sl_tab[16]={
404 SC( 0),SC( 1),SC( 2),SC(3 ),SC(4 ),SC(5 ),SC(6 ),SC( 7),
405 SC( 8),SC( 9),SC(10),SC(11),SC(12),SC(13),SC(14),SC(31)
406 };
407 #undef SC
408
409
410 #define RATE_STEPS (8)
411 static const unsigned char eg_inc[15*RATE_STEPS]={
412
413 /*cycle:0 1 2 3 4 5 6 7*/
414
415 /* 0 */ 0,1, 0,1, 0,1, 0,1, /* rates 00..12 0 (increment by 0 or 1) */
416 /* 1 */ 0,1, 0,1, 1,1, 0,1, /* rates 00..12 1 */
417 /* 2 */ 0,1, 1,1, 0,1, 1,1, /* rates 00..12 2 */
418 /* 3 */ 0,1, 1,1, 1,1, 1,1, /* rates 00..12 3 */
419
420 /* 4 */ 1,1, 1,1, 1,1, 1,1, /* rate 13 0 (increment by 1) */
421 /* 5 */ 1,1, 1,2, 1,1, 1,2, /* rate 13 1 */
422 /* 6 */ 1,2, 1,2, 1,2, 1,2, /* rate 13 2 */
423 /* 7 */ 1,2, 2,2, 1,2, 2,2, /* rate 13 3 */
424
425 /* 8 */ 2,2, 2,2, 2,2, 2,2, /* rate 14 0 (increment by 2) */
426 /* 9 */ 2,2, 2,4, 2,2, 2,4, /* rate 14 1 */
427 /*10 */ 2,4, 2,4, 2,4, 2,4, /* rate 14 2 */
428 /*11 */ 2,4, 4,4, 2,4, 4,4, /* rate 14 3 */
429
430 /*12 */ 4,4, 4,4, 4,4, 4,4, /* rates 15 0, 15 1, 15 2, 15 3 (increment by 4) */
431 /*13 */ 8,8, 8,8, 8,8, 8,8, /* rates 15 2, 15 3 for attack */
432 /*14 */ 0,0, 0,0, 0,0, 0,0, /* infinity rates for attack and decay(s) */
433 };
434
435
436 #define O(a) (a*RATE_STEPS)
437
438 /*note that there is no O(13) in this table - it's directly in the code */
439 static const unsigned char eg_rate_select[16+64+16]={ /* Envelope Generator rates (16 + 64 rates + 16 RKS) */
440 /* 16 infinite time rates */
441 O(14),O(14),O(14),O(14),O(14),O(14),O(14),O(14),
442 O(14),O(14),O(14),O(14),O(14),O(14),O(14),O(14),
443
444 /* rates 00-12 */
445 O( 0),O( 1),O( 2),O( 3),
446 O( 0),O( 1),O( 2),O( 3),
447 O( 0),O( 1),O( 2),O( 3),
448 O( 0),O( 1),O( 2),O( 3),
449 O( 0),O( 1),O( 2),O( 3),
450 O( 0),O( 1),O( 2),O( 3),
451 O( 0),O( 1),O( 2),O( 3),
452 O( 0),O( 1),O( 2),O( 3),
453 O( 0),O( 1),O( 2),O( 3),
454 O( 0),O( 1),O( 2),O( 3),
455 O( 0),O( 1),O( 2),O( 3),
456 O( 0),O( 1),O( 2),O( 3),
457 O( 0),O( 1),O( 2),O( 3),
458
459 /* rate 13 */
460 O( 4),O( 5),O( 6),O( 7),
461
462 /* rate 14 */
463 O( 8),O( 9),O(10),O(11),
464
465 /* rate 15 */
466 O(12),O(12),O(12),O(12),
467
468 /* 16 dummy rates (same as 15 3) */
469 O(12),O(12),O(12),O(12),O(12),O(12),O(12),O(12),
470 O(12),O(12),O(12),O(12),O(12),O(12),O(12),O(12),
471
472 };
473 #undef O
474
475 /*rate 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 */
476 /*shift 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0, 0, 0, 0 */
477 /*mask 4095, 2047, 1023, 511, 255, 127, 63, 31, 15, 7, 3, 1, 0, 0, 0, 0 */
478
479 #define O(a) (a*1)
480 static const unsigned char eg_rate_shift[16+64+16]={ /* Envelope Generator counter shifts (16 + 64 rates + 16 RKS) */
481 /* 16 infinite time rates */
482 O(0),O(0),O(0),O(0),O(0),O(0),O(0),O(0),
483 O(0),O(0),O(0),O(0),O(0),O(0),O(0),O(0),
484
485 /* rates 00-12 */
486 O(12),O(12),O(12),O(12),
487 O(11),O(11),O(11),O(11),
488 O(10),O(10),O(10),O(10),
489 O( 9),O( 9),O( 9),O( 9),
490 O( 8),O( 8),O( 8),O( 8),
491 O( 7),O( 7),O( 7),O( 7),
492 O( 6),O( 6),O( 6),O( 6),
493 O( 5),O( 5),O( 5),O( 5),
494 O( 4),O( 4),O( 4),O( 4),
495 O( 3),O( 3),O( 3),O( 3),
496 O( 2),O( 2),O( 2),O( 2),
497 O( 1),O( 1),O( 1),O( 1),
498 O( 0),O( 0),O( 0),O( 0),
499
500 /* rate 13 */
501 O( 0),O( 0),O( 0),O( 0),
502
503 /* rate 14 */
504 O( 0),O( 0),O( 0),O( 0),
505
506 /* rate 15 */
507 O( 0),O( 0),O( 0),O( 0),
508
509 /* 16 dummy rates (same as 15 3) */
510 O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),
511 O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),
512
513 };
514 #undef O
515
516
517 /* multiple table */
518 #define ML 2
519 static const UINT8 mul_tab[16]= {
520 /* 1/2, 1, 2, 3, 4, 5, 6, 7, 8, 9,10,10,12,12,15,15 */
521 0.50*ML, 1.00*ML, 2.00*ML, 3.00*ML, 4.00*ML, 5.00*ML, 6.00*ML, 7.00*ML,
522 8.00*ML, 9.00*ML,10.00*ML,10.00*ML,12.00*ML,12.00*ML,15.00*ML,15.00*ML
523 };
524 #undef ML
525
526 /* TL_TAB_LEN is calculated as:
527 * 12 - sinus amplitude bits (Y axis)
528 * 2 - sinus sign bit (Y axis)
529 * TL_RES_LEN - sinus resolution (X axis)
530 */
531 #define TL_TAB_LEN (12*2*TL_RES_LEN)
532 static signed int tl_tab[TL_TAB_LEN];
533
534 #define ENV_QUIET (TL_TAB_LEN>>4)
535
536 /* sin waveform table in 'decibel' scale */
537 /* four waveforms on OPL2 type chips */
538 static unsigned int sin_tab[SIN_LEN * 4];
539
540
541 /* LFO Amplitude Modulation table (verified on real YM3812)
542 27 output levels (triangle waveform); 1 level takes one of: 192, 256 or 448 samples
543
544 Length: 210 elements.
545
546 Each of the elements has to be repeated
547 exactly 64 times (on 64 consecutive samples).
548 The whole table takes: 64 * 210 = 13440 samples.
549
550 When AM = 1 data is used directly
551 When AM = 0 data is divided by 4 before being used (loosing precision is important)
552 */
553
554 #define LFO_AM_TAB_ELEMENTS 210
555
556 static const UINT8 lfo_am_table[LFO_AM_TAB_ELEMENTS] = {
557 0,0,0,0,0,0,0,
558 1,1,1,1,
559 2,2,2,2,
560 3,3,3,3,
561 4,4,4,4,
562 5,5,5,5,
563 6,6,6,6,
564 7,7,7,7,
565 8,8,8,8,
566 9,9,9,9,
567 10,10,10,10,
568 11,11,11,11,
569 12,12,12,12,
570 13,13,13,13,
571 14,14,14,14,
572 15,15,15,15,
573 16,16,16,16,
574 17,17,17,17,
575 18,18,18,18,
576 19,19,19,19,
577 20,20,20,20,
578 21,21,21,21,
579 22,22,22,22,
580 23,23,23,23,
581 24,24,24,24,
582 25,25,25,25,
583 26,26,26,
584 25,25,25,25,
585 24,24,24,24,
586 23,23,23,23,
587 22,22,22,22,
588 21,21,21,21,
589 20,20,20,20,
590 19,19,19,19,
591 18,18,18,18,
592 17,17,17,17,
593 16,16,16,16,
594 15,15,15,15,
595 14,14,14,14,
596 13,13,13,13,
597 12,12,12,12,
598 11,11,11,11,
599 10,10,10,10,
600 9,9,9,9,
601 8,8,8,8,
602 7,7,7,7,
603 6,6,6,6,
604 5,5,5,5,
605 4,4,4,4,
606 3,3,3,3,
607 2,2,2,2,
608 1,1,1,1
609 };
610
611 /* LFO Phase Modulation table (verified on real YM3812) */
612 static const INT8 lfo_pm_table[8*8*2] = {
613
614 /* FNUM2/FNUM = 00 0xxxxxxx (0x0000) */
615 0, 0, 0, 0, 0, 0, 0, 0, /*LFO PM depth = 0*/
616 0, 0, 0, 0, 0, 0, 0, 0, /*LFO PM depth = 1*/
617
618 /* FNUM2/FNUM = 00 1xxxxxxx (0x0080) */
619 0, 0, 0, 0, 0, 0, 0, 0, /*LFO PM depth = 0*/
620 1, 0, 0, 0,-1, 0, 0, 0, /*LFO PM depth = 1*/
621
622 /* FNUM2/FNUM = 01 0xxxxxxx (0x0100) */
623 1, 0, 0, 0,-1, 0, 0, 0, /*LFO PM depth = 0*/
624 2, 1, 0,-1,-2,-1, 0, 1, /*LFO PM depth = 1*/
625
626 /* FNUM2/FNUM = 01 1xxxxxxx (0x0180) */
627 1, 0, 0, 0,-1, 0, 0, 0, /*LFO PM depth = 0*/
628 3, 1, 0,-1,-3,-1, 0, 1, /*LFO PM depth = 1*/
629
630 /* FNUM2/FNUM = 10 0xxxxxxx (0x0200) */
631 2, 1, 0,-1,-2,-1, 0, 1, /*LFO PM depth = 0*/
632 4, 2, 0,-2,-4,-2, 0, 2, /*LFO PM depth = 1*/
633
634 /* FNUM2/FNUM = 10 1xxxxxxx (0x0280) */
635 2, 1, 0,-1,-2,-1, 0, 1, /*LFO PM depth = 0*/
636 5, 2, 0,-2,-5,-2, 0, 2, /*LFO PM depth = 1*/
637
638 /* FNUM2/FNUM = 11 0xxxxxxx (0x0300) */
639 3, 1, 0,-1,-3,-1, 0, 1, /*LFO PM depth = 0*/
640 6, 3, 0,-3,-6,-3, 0, 3, /*LFO PM depth = 1*/
641
642 /* FNUM2/FNUM = 11 1xxxxxxx (0x0380) */
643 3, 1, 0,-1,-3,-1, 0, 1, /*LFO PM depth = 0*/
644 7, 3, 0,-3,-7,-3, 0, 3 /*LFO PM depth = 1*/
645 };
646
647
648 /* lock level of common table */
649 static int num_lock = 0;
650
651
652 static void *cur_chip = NULL; /* current chip pointer */
653 static OPL_SLOT *SLOT7_1, *SLOT7_2, *SLOT8_1, *SLOT8_2;
654
655
limit(int val,int max,int min)656 INLINE int limit( int val, int max, int min ) {
657 if ( val > max )
658 val = max;
659 else if ( val < min )
660 val = min;
661
662 return val;
663 }
664
665
666 /* status set and IRQ handling */
OPL_STATUS_SET(FM_OPL * OPL,int flag)667 INLINE void OPL_STATUS_SET(FM_OPL *OPL,int flag)
668 {
669 /* set status flag */
670 OPL->status |= flag;
671 if(!(OPL->status & 0x80))
672 {
673 if(OPL->status & OPL->statusmask)
674 { /* IRQ on */
675 OPL->status |= 0x80;
676 /* callback user interrupt handler (IRQ is OFF to ON) */
677 if(OPL->IRQHandler) (OPL->IRQHandler)(OPL->IRQParam,1);
678 }
679 }
680 }
681
682 /* status reset and IRQ handling */
OPL_STATUS_RESET(FM_OPL * OPL,int flag)683 INLINE void OPL_STATUS_RESET(FM_OPL *OPL,int flag)
684 {
685 /* reset status flag */
686 OPL->status &=~flag;
687 if((OPL->status & 0x80))
688 {
689 if (!(OPL->status & OPL->statusmask) )
690 {
691 OPL->status &= 0x7f;
692 /* callback user interrupt handler (IRQ is ON to OFF) */
693 if(OPL->IRQHandler) (OPL->IRQHandler)(OPL->IRQParam,0);
694 }
695 }
696 }
697
698 /* IRQ mask set */
OPL_STATUSMASK_SET(FM_OPL * OPL,int flag)699 INLINE void OPL_STATUSMASK_SET(FM_OPL *OPL,int flag)
700 {
701 OPL->statusmask = flag;
702 /* IRQ handling check */
703 OPL_STATUS_SET(OPL,0);
704 OPL_STATUS_RESET(OPL,0);
705 }
706
707
708 /* advance LFO to next sample */
advance_lfo(FM_OPL * OPL)709 INLINE void advance_lfo(FM_OPL *OPL)
710 {
711 UINT8 tmp;
712
713 /* LFO */
714 OPL->lfo_am_cnt += OPL->lfo_am_inc;
715 if (OPL->lfo_am_cnt >= (LFO_AM_TAB_ELEMENTS<<LFO_SH) ) /* lfo_am_table is 210 elements long */
716 OPL->lfo_am_cnt -= (LFO_AM_TAB_ELEMENTS<<LFO_SH);
717
718 tmp = lfo_am_table[ OPL->lfo_am_cnt >> LFO_SH ];
719
720 if (OPL->lfo_am_depth)
721 OPL->LFO_AM = tmp;
722 else
723 OPL->LFO_AM = tmp>>2;
724
725 OPL->lfo_pm_cnt += OPL->lfo_pm_inc;
726 OPL->LFO_PM = ((OPL->lfo_pm_cnt>>LFO_SH) & 7) | OPL->lfo_pm_depth_range;
727 }
728
729 /* advance to next sample */
advance(FM_OPL * OPL)730 INLINE void advance(FM_OPL *OPL)
731 {
732 OPL_CH *CH;
733 OPL_SLOT *op;
734 int i;
735
736 OPL->eg_timer += OPL->eg_timer_add;
737
738 while (OPL->eg_timer >= OPL->eg_timer_overflow)
739 {
740 OPL->eg_timer -= OPL->eg_timer_overflow;
741
742 OPL->eg_cnt++;
743
744 for (i=0; i<9*2; i++)
745 {
746 CH = &OPL->P_CH[i/2];
747 op = &CH->SLOT[i&1];
748
749 /* Envelope Generator */
750 switch(op->state)
751 {
752 case EG_ATT: /* attack phase */
753 if ( !(OPL->eg_cnt & ((1<<op->eg_sh_ar)-1) ) )
754 {
755 op->volume += (~op->volume *
756 (eg_inc[op->eg_sel_ar + ((OPL->eg_cnt>>op->eg_sh_ar)&7)])
757 ) >>3;
758
759 if (op->volume <= MIN_ATT_INDEX)
760 {
761 op->volume = MIN_ATT_INDEX;
762 op->state = EG_DEC;
763 }
764
765 }
766 break;
767
768 case EG_DEC: /* decay phase */
769 if ( !(OPL->eg_cnt & ((1<<op->eg_sh_dr)-1) ) )
770 {
771 op->volume += eg_inc[op->eg_sel_dr + ((OPL->eg_cnt>>op->eg_sh_dr)&7)];
772
773 if ( op->volume >= op->sl )
774 op->state = EG_SUS;
775
776 }
777 break;
778
779 case EG_SUS: /* sustain phase */
780
781 /* this is important behaviour:
782 one can change percusive/non-percussive modes on the fly and
783 the chip will remain in sustain phase - verified on real YM3812 */
784
785 if(op->eg_type) /* non-percussive mode */
786 {
787 /* do nothing */
788 }
789 else /* percussive mode */
790 {
791 /* during sustain phase chip adds Release Rate (in percussive mode) */
792 if ( !(OPL->eg_cnt & ((1<<op->eg_sh_rr)-1) ) )
793 {
794 op->volume += eg_inc[op->eg_sel_rr + ((OPL->eg_cnt>>op->eg_sh_rr)&7)];
795
796 if ( op->volume >= MAX_ATT_INDEX )
797 op->volume = MAX_ATT_INDEX;
798 }
799 /* else do nothing in sustain phase */
800 }
801 break;
802
803 case EG_REL: /* release phase */
804 if ( !(OPL->eg_cnt & ((1<<op->eg_sh_rr)-1) ) )
805 {
806 op->volume += eg_inc[op->eg_sel_rr + ((OPL->eg_cnt>>op->eg_sh_rr)&7)];
807
808 if ( op->volume >= MAX_ATT_INDEX )
809 {
810 op->volume = MAX_ATT_INDEX;
811 op->state = EG_OFF;
812 }
813
814 }
815 break;
816
817 default:
818 break;
819 }
820 }
821 }
822
823 for (i=0; i<9*2; i++)
824 {
825 CH = &OPL->P_CH[i/2];
826 op = &CH->SLOT[i&1];
827
828 /* Phase Generator */
829 if(op->vib)
830 {
831 UINT8 block;
832 unsigned int block_fnum = CH->block_fnum;
833
834 unsigned int fnum_lfo = (block_fnum&0x0380) >> 7;
835
836 signed int lfo_fn_table_index_offset = lfo_pm_table[OPL->LFO_PM + 16*fnum_lfo ];
837
838 if (lfo_fn_table_index_offset) /* LFO phase modulation active */
839 {
840 block_fnum += lfo_fn_table_index_offset;
841 block = (block_fnum&0x1c00) >> 10;
842 op->Cnt += (OPL->fn_tab[block_fnum&0x03ff] >> (7-block)) * op->mul;
843 }
844 else /* LFO phase modulation = zero */
845 {
846 op->Cnt += op->Incr;
847 }
848 }
849 else /* LFO phase modulation disabled for this operator */
850 {
851 op->Cnt += op->Incr;
852 }
853 }
854
855 /* The Noise Generator of the YM3812 is 23-bit shift register.
856 * Period is equal to 2^23-2 samples.
857 * Register works at sampling frequency of the chip, so output
858 * can change on every sample.
859 *
860 * Output of the register and input to the bit 22 is:
861 * bit0 XOR bit14 XOR bit15 XOR bit22
862 *
863 * Simply use bit 22 as the noise output.
864 */
865
866 OPL->noise_p += OPL->noise_f;
867 i = OPL->noise_p >> FREQ_SH; /* number of events (shifts of the shift register) */
868 OPL->noise_p &= FREQ_MASK;
869 while (i)
870 {
871 /*
872 UINT32 j;
873 j = ( (OPL->noise_rng) ^ (OPL->noise_rng>>14) ^ (OPL->noise_rng>>15) ^ (OPL->noise_rng>>22) ) & 1;
874 OPL->noise_rng = (j<<22) | (OPL->noise_rng>>1);
875 */
876
877 /*
878 Instead of doing all the logic operations above, we
879 use a trick here (and use bit 0 as the noise output).
880 The difference is only that the noise bit changes one
881 step ahead. This doesn't matter since we don't know
882 what is real state of the noise_rng after the reset.
883 */
884
885 if (OPL->noise_rng & 1) OPL->noise_rng ^= 0x800302;
886 OPL->noise_rng >>= 1;
887
888 i--;
889 }
890 }
891
892
op_calc(UINT32 phase,unsigned int env,signed int pm,unsigned int wave_tab)893 INLINE signed int op_calc(UINT32 phase, unsigned int env, signed int pm, unsigned int wave_tab)
894 {
895 UINT32 p;
896
897 p = (env<<4) + sin_tab[wave_tab + ((((signed int)((phase & ~FREQ_MASK) + (pm<<16))) >> FREQ_SH ) & SIN_MASK) ];
898
899 if (p >= TL_TAB_LEN)
900 return 0;
901 return tl_tab[p];
902 }
903
op_calc1(UINT32 phase,unsigned int env,signed int pm,unsigned int wave_tab)904 INLINE signed int op_calc1(UINT32 phase, unsigned int env, signed int pm, unsigned int wave_tab)
905 {
906 UINT32 p;
907
908 p = (env<<4) + sin_tab[wave_tab + ((((signed int)((phase & ~FREQ_MASK) + pm )) >> FREQ_SH ) & SIN_MASK) ];
909
910 if (p >= TL_TAB_LEN)
911 return 0;
912 return tl_tab[p];
913 }
914
915
916 #define volume_calc(OP) ((OP)->TLL + ((UINT32)(OP)->volume) + (OPL->LFO_AM & (OP)->AMmask))
917
918 /* calculate output */
OPL_CALC_CH(FM_OPL * OPL,OPL_CH * CH)919 INLINE void OPL_CALC_CH( FM_OPL *OPL, OPL_CH *CH )
920 {
921 OPL_SLOT *SLOT;
922 unsigned int env;
923 signed int out;
924
925 OPL->phase_modulation = 0;
926
927 /* SLOT 1 */
928 SLOT = &CH->SLOT[SLOT1];
929 env = volume_calc(SLOT);
930 out = SLOT->op1_out[0] + SLOT->op1_out[1];
931 SLOT->op1_out[0] = SLOT->op1_out[1];
932 *SLOT->connect1 += SLOT->op1_out[0];
933 SLOT->op1_out[1] = 0;
934 if( env < ENV_QUIET )
935 {
936 if (!SLOT->FB)
937 out = 0;
938 SLOT->op1_out[1] = op_calc1(SLOT->Cnt, env, (out<<SLOT->FB), SLOT->wavetable );
939 }
940
941 /* SLOT 2 */
942 SLOT++;
943 env = volume_calc(SLOT);
944 if( env < ENV_QUIET )
945 OPL->output[0] += op_calc(SLOT->Cnt, env, OPL->phase_modulation, SLOT->wavetable);
946 }
947
948 /*
949 operators used in the rhythm sounds generation process:
950
951 Envelope Generator:
952
953 channel operator register number Bass High Snare Tom Top
954 / slot number TL ARDR SLRR Wave Drum Hat Drum Tom Cymbal
955 6 / 0 12 50 70 90 f0 +
956 6 / 1 15 53 73 93 f3 +
957 7 / 0 13 51 71 91 f1 +
958 7 / 1 16 54 74 94 f4 +
959 8 / 0 14 52 72 92 f2 +
960 8 / 1 17 55 75 95 f5 +
961
962 Phase Generator:
963
964 channel operator register number Bass High Snare Tom Top
965 / slot number MULTIPLE Drum Hat Drum Tom Cymbal
966 6 / 0 12 30 +
967 6 / 1 15 33 +
968 7 / 0 13 31 + + +
969 7 / 1 16 34 ----- n o t u s e d -----
970 8 / 0 14 32 +
971 8 / 1 17 35 + +
972
973 channel operator register number Bass High Snare Tom Top
974 number number BLK/FNUM2 FNUM Drum Hat Drum Tom Cymbal
975 6 12,15 B6 A6 +
976
977 7 13,16 B7 A7 + + +
978
979 8 14,17 B8 A8 + + +
980
981 */
982
983 /* calculate rhythm */
984
OPL_CALC_RH(FM_OPL * OPL,OPL_CH * CH,unsigned int noise)985 INLINE void OPL_CALC_RH( FM_OPL *OPL, OPL_CH *CH, unsigned int noise )
986 {
987 OPL_SLOT *SLOT;
988 signed int out;
989 unsigned int env;
990
991
992 /* Bass Drum (verified on real YM3812):
993 - depends on the channel 6 'connect' register:
994 when connect = 0 it works the same as in normal (non-rhythm) mode (op1->op2->out)
995 when connect = 1 _only_ operator 2 is present on output (op2->out), operator 1 is ignored
996 - output sample always is multiplied by 2
997 */
998
999 OPL->phase_modulation = 0;
1000 /* SLOT 1 */
1001 SLOT = &CH[6].SLOT[SLOT1];
1002 env = volume_calc(SLOT);
1003
1004 out = SLOT->op1_out[0] + SLOT->op1_out[1];
1005 SLOT->op1_out[0] = SLOT->op1_out[1];
1006
1007 if (!SLOT->CON)
1008 OPL->phase_modulation = SLOT->op1_out[0];
1009 /* else ignore output of operator 1 */
1010
1011 SLOT->op1_out[1] = 0;
1012 if( env < ENV_QUIET )
1013 {
1014 if (!SLOT->FB)
1015 out = 0;
1016 SLOT->op1_out[1] = op_calc1(SLOT->Cnt, env, (out<<SLOT->FB), SLOT->wavetable );
1017 }
1018
1019 /* SLOT 2 */
1020 SLOT++;
1021 env = volume_calc(SLOT);
1022 if( env < ENV_QUIET )
1023 OPL->output[0] += op_calc(SLOT->Cnt, env, OPL->phase_modulation, SLOT->wavetable) * 2;
1024
1025
1026 /* Phase generation is based on: */
1027 /* HH (13) channel 7->slot 1 combined with channel 8->slot 2 (same combination as TOP CYMBAL but different output phases) */
1028 /* SD (16) channel 7->slot 1 */
1029 /* TOM (14) channel 8->slot 1 */
1030 /* TOP (17) channel 7->slot 1 combined with channel 8->slot 2 (same combination as HIGH HAT but different output phases) */
1031
1032 /* Envelope generation based on: */
1033 /* HH channel 7->slot1 */
1034 /* SD channel 7->slot2 */
1035 /* TOM channel 8->slot1 */
1036 /* TOP channel 8->slot2 */
1037
1038
1039 /* The following formulas can be well optimized.
1040 I leave them in direct form for now (in case I've missed something).
1041 */
1042
1043 /* High Hat (verified on real YM3812) */
1044 env = volume_calc(SLOT7_1);
1045 if( env < ENV_QUIET )
1046 {
1047
1048 /* high hat phase generation:
1049 phase = d0 or 234 (based on frequency only)
1050 phase = 34 or 2d0 (based on noise)
1051 */
1052
1053 /* base frequency derived from operator 1 in channel 7 */
1054 unsigned char bit7 = ((SLOT7_1->Cnt>>FREQ_SH)>>7)&1;
1055 unsigned char bit3 = ((SLOT7_1->Cnt>>FREQ_SH)>>3)&1;
1056 unsigned char bit2 = ((SLOT7_1->Cnt>>FREQ_SH)>>2)&1;
1057
1058 unsigned char res1 = (bit2 ^ bit7) | bit3;
1059
1060 /* when res1 = 0 phase = 0x000 | 0xd0; */
1061 /* when res1 = 1 phase = 0x200 | (0xd0>>2); */
1062 UINT32 phase = res1 ? (0x200|(0xd0>>2)) : 0xd0;
1063
1064 /* enable gate based on frequency of operator 2 in channel 8 */
1065 unsigned char bit5e= ((SLOT8_2->Cnt>>FREQ_SH)>>5)&1;
1066 unsigned char bit3e= ((SLOT8_2->Cnt>>FREQ_SH)>>3)&1;
1067
1068 unsigned char res2 = (bit3e ^ bit5e);
1069
1070 /* when res2 = 0 pass the phase from calculation above (res1); */
1071 /* when res2 = 1 phase = 0x200 | (0xd0>>2); */
1072 if (res2)
1073 phase = (0x200|(0xd0>>2));
1074
1075
1076 /* when phase & 0x200 is set and noise=1 then phase = 0x200|0xd0 */
1077 /* when phase & 0x200 is set and noise=0 then phase = 0x200|(0xd0>>2), ie no change */
1078 if (phase&0x200)
1079 {
1080 if (noise)
1081 phase = 0x200|0xd0;
1082 }
1083 else
1084 /* when phase & 0x200 is clear and noise=1 then phase = 0xd0>>2 */
1085 /* when phase & 0x200 is clear and noise=0 then phase = 0xd0, ie no change */
1086 {
1087 if (noise)
1088 phase = 0xd0>>2;
1089 }
1090
1091 OPL->output[0] += op_calc(phase<<FREQ_SH, env, 0, SLOT7_1->wavetable) * 2;
1092 }
1093
1094 /* Snare Drum (verified on real YM3812) */
1095 env = volume_calc(SLOT7_2);
1096 if( env < ENV_QUIET )
1097 {
1098 /* base frequency derived from operator 1 in channel 7 */
1099 unsigned char bit8 = ((SLOT7_1->Cnt>>FREQ_SH)>>8)&1;
1100
1101 /* when bit8 = 0 phase = 0x100; */
1102 /* when bit8 = 1 phase = 0x200; */
1103 UINT32 phase = bit8 ? 0x200 : 0x100;
1104
1105 /* Noise bit XOR'es phase by 0x100 */
1106 /* when noisebit = 0 pass the phase from calculation above */
1107 /* when noisebit = 1 phase ^= 0x100; */
1108 /* in other words: phase ^= (noisebit<<8); */
1109 if (noise)
1110 phase ^= 0x100;
1111
1112 OPL->output[0] += op_calc(phase<<FREQ_SH, env, 0, SLOT7_2->wavetable) * 2;
1113 }
1114
1115 /* Tom Tom (verified on real YM3812) */
1116 env = volume_calc(SLOT8_1);
1117 if( env < ENV_QUIET )
1118 OPL->output[0] += op_calc(SLOT8_1->Cnt, env, 0, SLOT8_1->wavetable) * 2;
1119
1120 /* Top Cymbal (verified on real YM3812) */
1121 env = volume_calc(SLOT8_2);
1122 if( env < ENV_QUIET )
1123 {
1124 /* base frequency derived from operator 1 in channel 7 */
1125 unsigned char bit7 = ((SLOT7_1->Cnt>>FREQ_SH)>>7)&1;
1126 unsigned char bit3 = ((SLOT7_1->Cnt>>FREQ_SH)>>3)&1;
1127 unsigned char bit2 = ((SLOT7_1->Cnt>>FREQ_SH)>>2)&1;
1128
1129 unsigned char res1 = (bit2 ^ bit7) | bit3;
1130
1131 /* when res1 = 0 phase = 0x000 | 0x100; */
1132 /* when res1 = 1 phase = 0x200 | 0x100; */
1133 UINT32 phase = res1 ? 0x300 : 0x100;
1134
1135 /* enable gate based on frequency of operator 2 in channel 8 */
1136 unsigned char bit5e= ((SLOT8_2->Cnt>>FREQ_SH)>>5)&1;
1137 unsigned char bit3e= ((SLOT8_2->Cnt>>FREQ_SH)>>3)&1;
1138
1139 unsigned char res2 = (bit3e ^ bit5e);
1140 /* when res2 = 0 pass the phase from calculation above (res1); */
1141 /* when res2 = 1 phase = 0x200 | 0x100; */
1142 if (res2)
1143 phase = 0x300;
1144
1145 OPL->output[0] += op_calc(phase<<FREQ_SH, env, 0, SLOT8_2->wavetable) * 2;
1146 }
1147
1148 }
1149
1150
1151 /* generic table initialize */
init_tables(void)1152 static int init_tables(void)
1153 {
1154 signed int i,x;
1155 signed int n;
1156 double o,m;
1157
1158
1159 for (x=0; x<TL_RES_LEN; x++)
1160 {
1161 m = (1<<16) / pow(2, (x+1) * (ENV_STEP/4.0) / 8.0);
1162 m = floor(m);
1163
1164 /* we never reach (1<<16) here due to the (x+1) */
1165 /* result fits within 16 bits at maximum */
1166
1167 n = (int)m; /* 16 bits here */
1168 n >>= 4; /* 12 bits here */
1169 if (n&1) /* round to nearest */
1170 n = (n>>1)+1;
1171 else
1172 n = n>>1;
1173 /* 11 bits here (rounded) */
1174 n <<= 1; /* 12 bits here (as in real chip) */
1175 tl_tab[ x*2 + 0 ] = n;
1176 tl_tab[ x*2 + 1 ] = -tl_tab[ x*2 + 0 ];
1177
1178 for (i=1; i<12; i++)
1179 {
1180 tl_tab[ x*2+0 + i*2*TL_RES_LEN ] = tl_tab[ x*2+0 ]>>i;
1181 tl_tab[ x*2+1 + i*2*TL_RES_LEN ] = -tl_tab[ x*2+0 + i*2*TL_RES_LEN ];
1182 }
1183 #if 0
1184 logerror("tl %04i", x*2);
1185 for (i=0; i<12; i++)
1186 logerror(", [%02i] %5i", i*2, tl_tab[ x*2 /*+1*/ + i*2*TL_RES_LEN ] );
1187 logerror("\n");
1188 #endif
1189 }
1190 /*logerror("FMOPL.C: TL_TAB_LEN = %i elements (%i bytes)\n",TL_TAB_LEN, (int)sizeof(tl_tab));*/
1191
1192
1193 for (i=0; i<SIN_LEN; i++)
1194 {
1195 /* non-standard sinus */
1196 m = sin( ((i*2)+1) * PI / SIN_LEN ); /* checked against the real chip */
1197
1198 /* we never reach zero here due to ((i*2)+1) */
1199
1200 if (m>0.0)
1201 o = 8*log(1.0/m)/log(2); /* convert to 'decibels' */
1202 else
1203 o = 8*log(-1.0/m)/log(2); /* convert to 'decibels' */
1204
1205 o = o / (ENV_STEP/4);
1206
1207 n = (int)(2.0*o);
1208 if (n&1) /* round to nearest */
1209 n = (n>>1)+1;
1210 else
1211 n = n>>1;
1212
1213 sin_tab[ i ] = n*2 + (m>=0.0? 0: 1 );
1214
1215 /*logerror("FMOPL.C: sin [%4i (hex=%03x)]= %4i (tl_tab value=%5i)\n", i, i, sin_tab[i], tl_tab[sin_tab[i]] );*/
1216 }
1217
1218 for (i=0; i<SIN_LEN; i++)
1219 {
1220 /* waveform 1: __ __ */
1221 /* / \____/ \____*/
1222 /* output only first half of the sinus waveform (positive one) */
1223
1224 if (i & (1<<(SIN_BITS-1)) )
1225 sin_tab[1*SIN_LEN+i] = TL_TAB_LEN;
1226 else
1227 sin_tab[1*SIN_LEN+i] = sin_tab[i];
1228
1229 /* waveform 2: __ __ __ __ */
1230 /* / \/ \/ \/ \*/
1231 /* abs(sin) */
1232
1233 sin_tab[2*SIN_LEN+i] = sin_tab[i & (SIN_MASK>>1) ];
1234
1235 /* waveform 3: _ _ _ _ */
1236 /* / |_/ |_/ |_/ |_*/
1237 /* abs(output only first quarter of the sinus waveform) */
1238
1239 if (i & (1<<(SIN_BITS-2)) )
1240 sin_tab[3*SIN_LEN+i] = TL_TAB_LEN;
1241 else
1242 sin_tab[3*SIN_LEN+i] = sin_tab[i & (SIN_MASK>>2)];
1243
1244 /*logerror("FMOPL.C: sin1[%4i]= %4i (tl_tab value=%5i)\n", i, sin_tab[1*SIN_LEN+i], tl_tab[sin_tab[1*SIN_LEN+i]] );
1245 logerror("FMOPL.C: sin2[%4i]= %4i (tl_tab value=%5i)\n", i, sin_tab[2*SIN_LEN+i], tl_tab[sin_tab[2*SIN_LEN+i]] );
1246 logerror("FMOPL.C: sin3[%4i]= %4i (tl_tab value=%5i)\n", i, sin_tab[3*SIN_LEN+i], tl_tab[sin_tab[3*SIN_LEN+i]] );*/
1247 }
1248 /*logerror("FMOPL.C: ENV_QUIET= %08x (dec*8=%i)\n", ENV_QUIET, ENV_QUIET*8 );*/
1249
1250
1251 #ifdef SAVE_SAMPLE
1252 sample[0]=fopen("sampsum.pcm","wb");
1253 #endif
1254
1255 return 1;
1256 }
1257
OPLCloseTable(void)1258 static void OPLCloseTable( void )
1259 {
1260 #ifdef SAVE_SAMPLE
1261 fclose(sample[0]);
1262 #endif
1263 }
1264
1265
1266
OPL_initalize(FM_OPL * OPL)1267 static void OPL_initalize(FM_OPL *OPL)
1268 {
1269 int i;
1270
1271 /* frequency base */
1272 OPL->freqbase = (OPL->rate) ? ((double)OPL->clock / 72.0) / OPL->rate : 0;
1273 #if 0
1274 OPL->rate = (double)OPL->clock / 72.0;
1275 OPL->freqbase = 1.0;
1276 #endif
1277
1278 /*logerror("freqbase=%f\n", OPL->freqbase);*/
1279
1280 /* Timer base time */
1281 OPL->TimerBase = 1.0 / ((double)OPL->clock / 72.0 );
1282
1283 /* make fnumber -> increment counter table */
1284 for( i=0 ; i < 1024 ; i++ )
1285 {
1286 /* opn phase increment counter = 20bit */
1287 OPL->fn_tab[i] = (UINT32)( (double)i * 64 * OPL->freqbase * (1<<(FREQ_SH-10)) ); /* -10 because chip works with 10.10 fixed point, while we use 16.16 */
1288 #if 0
1289 logerror("FMOPL.C: fn_tab[%4i] = %08x (dec=%8i)\n",
1290 i, OPL->fn_tab[i]>>6, OPL->fn_tab[i]>>6 );
1291 #endif
1292 }
1293
1294 #if 0
1295 for( i=0 ; i < 16 ; i++ )
1296 {
1297 logerror("FMOPL.C: sl_tab[%i] = %08x\n",
1298 i, sl_tab[i] );
1299 }
1300 for( i=0 ; i < 8 ; i++ )
1301 {
1302 int j;
1303 logerror("FMOPL.C: ksl_tab[oct=%2i] =",i);
1304 for (j=0; j<16; j++)
1305 {
1306 logerror("%08x ", ksl_tab[i*16+j] );
1307 }
1308 logerror("\n");
1309 }
1310 #endif
1311
1312
1313 /* Amplitude modulation: 27 output levels (triangle waveform); 1 level takes one of: 192, 256 or 448 samples */
1314 /* One entry from LFO_AM_TABLE lasts for 64 samples */
1315 OPL->lfo_am_inc = (1.0 / 64.0 ) * (1<<LFO_SH) * OPL->freqbase;
1316
1317 /* Vibrato: 8 output levels (triangle waveform); 1 level takes 1024 samples */
1318 OPL->lfo_pm_inc = (1.0 / 1024.0) * (1<<LFO_SH) * OPL->freqbase;
1319
1320 /*logerror ("OPL->lfo_am_inc = %8x ; OPL->lfo_pm_inc = %8x\n", OPL->lfo_am_inc, OPL->lfo_pm_inc);*/
1321
1322 /* Noise generator: a step takes 1 sample */
1323 OPL->noise_f = (1.0 / 1.0) * (1<<FREQ_SH) * OPL->freqbase;
1324
1325 OPL->eg_timer_add = (1<<EG_SH) * OPL->freqbase;
1326 OPL->eg_timer_overflow = ( 1 ) * (1<<EG_SH);
1327 /*logerror("OPLinit eg_timer_add=%8x eg_timer_overflow=%8x\n", OPL->eg_timer_add, OPL->eg_timer_overflow);*/
1328
1329 }
1330
FM_KEYON(OPL_SLOT * SLOT,UINT32 key_set)1331 INLINE void FM_KEYON(OPL_SLOT *SLOT, UINT32 key_set)
1332 {
1333 if( !SLOT->key )
1334 {
1335 /* restart Phase Generator */
1336 SLOT->Cnt = 0;
1337 /* phase -> Attack */
1338 SLOT->state = EG_ATT;
1339 }
1340 SLOT->key |= key_set;
1341 }
1342
FM_KEYOFF(OPL_SLOT * SLOT,UINT32 key_clr)1343 INLINE void FM_KEYOFF(OPL_SLOT *SLOT, UINT32 key_clr)
1344 {
1345 if( SLOT->key )
1346 {
1347 SLOT->key &= key_clr;
1348
1349 if( !SLOT->key )
1350 {
1351 /* phase -> Release */
1352 if (SLOT->state>EG_REL)
1353 SLOT->state = EG_REL;
1354 }
1355 }
1356 }
1357
1358 /* update phase increment counter of operator (also update the EG rates if necessary) */
CALC_FCSLOT(OPL_CH * CH,OPL_SLOT * SLOT)1359 INLINE void CALC_FCSLOT(OPL_CH *CH,OPL_SLOT *SLOT)
1360 {
1361 int ksr;
1362
1363 /* (frequency) phase increment counter */
1364 SLOT->Incr = CH->fc * SLOT->mul;
1365 ksr = CH->kcode >> SLOT->KSR;
1366
1367 if( SLOT->ksr != ksr )
1368 {
1369 SLOT->ksr = ksr;
1370
1371 /* calculate envelope generator rates */
1372 if ((SLOT->ar + SLOT->ksr) < 16+62)
1373 {
1374 SLOT->eg_sh_ar = eg_rate_shift [SLOT->ar + SLOT->ksr ];
1375 SLOT->eg_sel_ar = eg_rate_select[SLOT->ar + SLOT->ksr ];
1376 }
1377 else
1378 {
1379 SLOT->eg_sh_ar = 0;
1380 SLOT->eg_sel_ar = 13*RATE_STEPS;
1381 }
1382 SLOT->eg_sh_dr = eg_rate_shift [SLOT->dr + SLOT->ksr ];
1383 SLOT->eg_sel_dr = eg_rate_select[SLOT->dr + SLOT->ksr ];
1384 SLOT->eg_sh_rr = eg_rate_shift [SLOT->rr + SLOT->ksr ];
1385 SLOT->eg_sel_rr = eg_rate_select[SLOT->rr + SLOT->ksr ];
1386 }
1387 }
1388
1389 /* set multi,am,vib,EG-TYP,KSR,mul */
set_mul(FM_OPL * OPL,int slot,int v)1390 INLINE void set_mul(FM_OPL *OPL,int slot,int v)
1391 {
1392 OPL_CH *CH = &OPL->P_CH[slot/2];
1393 OPL_SLOT *SLOT = &CH->SLOT[slot&1];
1394
1395 SLOT->mul = mul_tab[v&0x0f];
1396 SLOT->KSR = (v&0x10) ? 0 : 2;
1397 SLOT->eg_type = (v&0x20);
1398 SLOT->vib = (v&0x40);
1399 SLOT->AMmask = (v&0x80) ? ~0 : 0;
1400 CALC_FCSLOT(CH,SLOT);
1401 }
1402
1403 /* set ksl & tl */
set_ksl_tl(FM_OPL * OPL,int slot,int v)1404 INLINE void set_ksl_tl(FM_OPL *OPL,int slot,int v)
1405 {
1406 OPL_CH *CH = &OPL->P_CH[slot/2];
1407 OPL_SLOT *SLOT = &CH->SLOT[slot&1];
1408 int ksl = v>>6; /* 0 / 1.5 / 3.0 / 6.0 dB/OCT */
1409
1410 SLOT->ksl = ksl ? 3-ksl : 31;
1411 SLOT->TL = (v&0x3f)<<(ENV_BITS-1-7); /* 7 bits TL (bit 6 = always 0) */
1412
1413 SLOT->TLL = SLOT->TL + (CH->ksl_base>>SLOT->ksl);
1414 }
1415
1416 /* set attack rate & decay rate */
set_ar_dr(FM_OPL * OPL,int slot,int v)1417 INLINE void set_ar_dr(FM_OPL *OPL,int slot,int v)
1418 {
1419 OPL_CH *CH = &OPL->P_CH[slot/2];
1420 OPL_SLOT *SLOT = &CH->SLOT[slot&1];
1421
1422 SLOT->ar = (v>>4) ? 16 + ((v>>4) <<2) : 0;
1423
1424 if ((SLOT->ar + SLOT->ksr) < 16+62)
1425 {
1426 SLOT->eg_sh_ar = eg_rate_shift [SLOT->ar + SLOT->ksr ];
1427 SLOT->eg_sel_ar = eg_rate_select[SLOT->ar + SLOT->ksr ];
1428 }
1429 else
1430 {
1431 SLOT->eg_sh_ar = 0;
1432 SLOT->eg_sel_ar = 13*RATE_STEPS;
1433 }
1434
1435 SLOT->dr = (v&0x0f)? 16 + ((v&0x0f)<<2) : 0;
1436 SLOT->eg_sh_dr = eg_rate_shift [SLOT->dr + SLOT->ksr ];
1437 SLOT->eg_sel_dr = eg_rate_select[SLOT->dr + SLOT->ksr ];
1438 }
1439
1440 /* set sustain level & release rate */
set_sl_rr(FM_OPL * OPL,int slot,int v)1441 INLINE void set_sl_rr(FM_OPL *OPL,int slot,int v)
1442 {
1443 OPL_CH *CH = &OPL->P_CH[slot/2];
1444 OPL_SLOT *SLOT = &CH->SLOT[slot&1];
1445
1446 SLOT->sl = sl_tab[ v>>4 ];
1447
1448 SLOT->rr = (v&0x0f)? 16 + ((v&0x0f)<<2) : 0;
1449 SLOT->eg_sh_rr = eg_rate_shift [SLOT->rr + SLOT->ksr ];
1450 SLOT->eg_sel_rr = eg_rate_select[SLOT->rr + SLOT->ksr ];
1451 }
1452
1453
1454 /* write a value v to register r on OPL chip */
OPLWriteReg(FM_OPL * OPL,int r,int v)1455 static void OPLWriteReg(FM_OPL *OPL, int r, int v)
1456 {
1457 OPL_CH *CH;
1458 int slot;
1459 int block_fnum;
1460
1461
1462 /* adjust bus to 8 bits */
1463 r &= 0xff;
1464 v &= 0xff;
1465
1466 #ifdef LOG_CYM_FILE
1467 if ((cymfile) && (r!=0) )
1468 {
1469 fputc( (unsigned char)r, cymfile );
1470 fputc( (unsigned char)v, cymfile );
1471 }
1472 #endif
1473
1474
1475 switch(r&0xe0)
1476 {
1477 case 0x00: /* 00-1f:control */
1478 switch(r&0x1f)
1479 {
1480 case 0x01: /* waveform select enable */
1481 if(OPL->type&OPL_TYPE_WAVESEL)
1482 {
1483 OPL->wavesel = v&0x20;
1484 /* do not change the waveform previously selected */
1485 }
1486 break;
1487 case 0x02: /* Timer 1 */
1488 OPL->T[0] = (256-v)*4;
1489 break;
1490 case 0x03: /* Timer 2 */
1491 OPL->T[1] = (256-v)*16;
1492 break;
1493 case 0x04: /* IRQ clear / mask and Timer enable */
1494 if(v&0x80)
1495 { /* IRQ flag clear */
1496 OPL_STATUS_RESET(OPL,0x7f-0x08); /* don't reset BFRDY flag or we will have to call deltat module to set the flag */
1497 }
1498 else
1499 { /* set IRQ mask ,timer enable*/
1500 UINT8 st1 = v&1;
1501 UINT8 st2 = (v>>1)&1;
1502
1503 /* IRQRST,T1MSK,t2MSK,EOSMSK,BRMSK,x,ST2,ST1 */
1504 OPL_STATUS_RESET(OPL, v & (0x78-0x08) );
1505 OPL_STATUSMASK_SET(OPL, (~v) & 0x78 );
1506
1507 /* timer 2 */
1508 if(OPL->st[1] != st2)
1509 {
1510 double interval = st2 ? (double)OPL->T[1]*OPL->TimerBase : 0.0;
1511 OPL->st[1] = st2;
1512 if (OPL->TimerHandler) (OPL->TimerHandler)(OPL->TimerParam+1,interval);
1513 }
1514 /* timer 1 */
1515 if(OPL->st[0] != st1)
1516 {
1517 double interval = st1 ? (double)OPL->T[0]*OPL->TimerBase : 0.0;
1518 OPL->st[0] = st1;
1519 if (OPL->TimerHandler) (OPL->TimerHandler)(OPL->TimerParam+0,interval);
1520 }
1521 }
1522 break;
1523 #if BUILD_Y8950
1524 case 0x06: /* Key Board OUT */
1525 if(OPL->type&OPL_TYPE_KEYBOARD)
1526 {
1527 if(OPL->keyboardhandler_w)
1528 OPL->keyboardhandler_w(OPL->keyboard_param,v);
1529 else
1530 logerror("Y8950: write unmapped KEYBOARD port\n");
1531 }
1532 break;
1533 case 0x07: /* DELTA-T control 1 : START,REC,MEMDATA,REPT,SPOFF,x,x,RST */
1534 if(OPL->type&OPL_TYPE_ADPCM)
1535 YM_DELTAT_ADPCM_Write(OPL->deltat,r-0x07,v);
1536 break;
1537 #endif
1538 case 0x08: /* MODE,DELTA-T control 2 : CSM,NOTESEL,x,x,smpl,da/ad,64k,rom */
1539 OPL->mode = v;
1540 #if BUILD_Y8950
1541 if(OPL->type&OPL_TYPE_ADPCM)
1542 YM_DELTAT_ADPCM_Write(OPL->deltat,r-0x07,v&0x0f); /* mask 4 LSBs in register 08 for DELTA-T unit */
1543 #endif
1544 break;
1545
1546 #if BUILD_Y8950
1547 case 0x09: /* START ADD */
1548 case 0x0a:
1549 case 0x0b: /* STOP ADD */
1550 case 0x0c:
1551 case 0x0d: /* PRESCALE */
1552 case 0x0e:
1553 case 0x0f: /* ADPCM data write */
1554 case 0x10: /* DELTA-N */
1555 case 0x11: /* DELTA-N */
1556 case 0x12: /* ADPCM volume */
1557 if(OPL->type&OPL_TYPE_ADPCM)
1558 YM_DELTAT_ADPCM_Write(OPL->deltat,r-0x07,v);
1559 break;
1560
1561 case 0x15: /* DAC data high 8 bits (F7,F6...F2) */
1562 case 0x16: /* DAC data low 2 bits (F1, F0 in bits 7,6) */
1563 case 0x17: /* DAC data shift (S2,S1,S0 in bits 2,1,0) */
1564 logerror("FMOPL.C: DAC data register written, but not implemented reg=%02x val=%02x\n",r,v);
1565 break;
1566
1567 case 0x18: /* I/O CTRL (Direction) */
1568 if(OPL->type&OPL_TYPE_IO)
1569 OPL->portDirection = v&0x0f;
1570 break;
1571 case 0x19: /* I/O DATA */
1572 if(OPL->type&OPL_TYPE_IO)
1573 {
1574 OPL->portLatch = v;
1575 if(OPL->porthandler_w)
1576 OPL->porthandler_w(OPL->port_param,v&OPL->portDirection);
1577 }
1578 break;
1579 #endif
1580 default:
1581 logerror("FMOPL.C: write to unknown register: %02x\n",r);
1582 break;
1583 }
1584 break;
1585 case 0x20: /* am ON, vib ON, ksr, eg_type, mul */
1586 slot = slot_array[r&0x1f];
1587 if(slot < 0) return;
1588 set_mul(OPL,slot,v);
1589 break;
1590 case 0x40:
1591 slot = slot_array[r&0x1f];
1592 if(slot < 0) return;
1593 set_ksl_tl(OPL,slot,v);
1594 break;
1595 case 0x60:
1596 slot = slot_array[r&0x1f];
1597 if(slot < 0) return;
1598 set_ar_dr(OPL,slot,v);
1599 break;
1600 case 0x80:
1601 slot = slot_array[r&0x1f];
1602 if(slot < 0) return;
1603 set_sl_rr(OPL,slot,v);
1604 break;
1605 case 0xa0:
1606 if (r == 0xbd) /* am depth, vibrato depth, r,bd,sd,tom,tc,hh */
1607 {
1608 OPL->lfo_am_depth = v & 0x80;
1609 OPL->lfo_pm_depth_range = (v&0x40) ? 8 : 0;
1610
1611 OPL->rhythm = v&0x3f;
1612
1613 if(OPL->rhythm&0x20)
1614 {
1615 /* BD key on/off */
1616 if(v&0x10)
1617 {
1618 FM_KEYON (&OPL->P_CH[6].SLOT[SLOT1], 2);
1619 FM_KEYON (&OPL->P_CH[6].SLOT[SLOT2], 2);
1620 }
1621 else
1622 {
1623 FM_KEYOFF(&OPL->P_CH[6].SLOT[SLOT1],~2);
1624 FM_KEYOFF(&OPL->P_CH[6].SLOT[SLOT2],~2);
1625 }
1626 /* HH key on/off */
1627 if(v&0x01) FM_KEYON (&OPL->P_CH[7].SLOT[SLOT1], 2);
1628 else FM_KEYOFF(&OPL->P_CH[7].SLOT[SLOT1],~2);
1629 /* SD key on/off */
1630 if(v&0x08) FM_KEYON (&OPL->P_CH[7].SLOT[SLOT2], 2);
1631 else FM_KEYOFF(&OPL->P_CH[7].SLOT[SLOT2],~2);
1632 /* TOM key on/off */
1633 if(v&0x04) FM_KEYON (&OPL->P_CH[8].SLOT[SLOT1], 2);
1634 else FM_KEYOFF(&OPL->P_CH[8].SLOT[SLOT1],~2);
1635 /* TOP-CY key on/off */
1636 if(v&0x02) FM_KEYON (&OPL->P_CH[8].SLOT[SLOT2], 2);
1637 else FM_KEYOFF(&OPL->P_CH[8].SLOT[SLOT2],~2);
1638 }
1639 else
1640 {
1641 /* BD key off */
1642 FM_KEYOFF(&OPL->P_CH[6].SLOT[SLOT1],~2);
1643 FM_KEYOFF(&OPL->P_CH[6].SLOT[SLOT2],~2);
1644 /* HH key off */
1645 FM_KEYOFF(&OPL->P_CH[7].SLOT[SLOT1],~2);
1646 /* SD key off */
1647 FM_KEYOFF(&OPL->P_CH[7].SLOT[SLOT2],~2);
1648 /* TOM key off */
1649 FM_KEYOFF(&OPL->P_CH[8].SLOT[SLOT1],~2);
1650 /* TOP-CY off */
1651 FM_KEYOFF(&OPL->P_CH[8].SLOT[SLOT2],~2);
1652 }
1653 return;
1654 }
1655 /* keyon,block,fnum */
1656 if( (r&0x0f) > 8) return;
1657 CH = &OPL->P_CH[r&0x0f];
1658 if(!(r&0x10))
1659 { /* a0-a8 */
1660 block_fnum = (CH->block_fnum&0x1f00) | v;
1661 }
1662 else
1663 { /* b0-b8 */
1664 block_fnum = ((v&0x1f)<<8) | (CH->block_fnum&0xff);
1665
1666 if(v&0x20)
1667 {
1668 FM_KEYON (&CH->SLOT[SLOT1], 1);
1669 FM_KEYON (&CH->SLOT[SLOT2], 1);
1670 }
1671 else
1672 {
1673 FM_KEYOFF(&CH->SLOT[SLOT1],~1);
1674 FM_KEYOFF(&CH->SLOT[SLOT2],~1);
1675 }
1676 }
1677 /* update */
1678 if(CH->block_fnum != block_fnum)
1679 {
1680 UINT8 block = block_fnum >> 10;
1681
1682 CH->block_fnum = block_fnum;
1683
1684 CH->ksl_base = ksl_tab[block_fnum>>6];
1685 CH->fc = OPL->fn_tab[block_fnum&0x03ff] >> (7-block);
1686
1687 /* BLK 2,1,0 bits -> bits 3,2,1 of kcode */
1688 CH->kcode = (CH->block_fnum&0x1c00)>>9;
1689
1690 /* the info below is actually opposite to what is stated in the Manuals (verifed on real YM3812) */
1691 /* if notesel == 0 -> lsb of kcode is bit 10 (MSB) of fnum */
1692 /* if notesel == 1 -> lsb of kcode is bit 9 (MSB-1) of fnum */
1693 if (OPL->mode&0x40)
1694 CH->kcode |= (CH->block_fnum&0x100)>>8; /* notesel == 1 */
1695 else
1696 CH->kcode |= (CH->block_fnum&0x200)>>9; /* notesel == 0 */
1697
1698 /* refresh Total Level in both SLOTs of this channel */
1699 CH->SLOT[SLOT1].TLL = CH->SLOT[SLOT1].TL + (CH->ksl_base>>CH->SLOT[SLOT1].ksl);
1700 CH->SLOT[SLOT2].TLL = CH->SLOT[SLOT2].TL + (CH->ksl_base>>CH->SLOT[SLOT2].ksl);
1701
1702 /* refresh frequency counter in both SLOTs of this channel */
1703 CALC_FCSLOT(CH,&CH->SLOT[SLOT1]);
1704 CALC_FCSLOT(CH,&CH->SLOT[SLOT2]);
1705 }
1706 break;
1707 case 0xc0:
1708 /* FB,C */
1709 if( (r&0x0f) > 8) return;
1710 CH = &OPL->P_CH[r&0x0f];
1711 CH->SLOT[SLOT1].FB = (v>>1)&7 ? ((v>>1)&7) + 7 : 0;
1712 CH->SLOT[SLOT1].CON = v&1;
1713 CH->SLOT[SLOT1].connect1 = CH->SLOT[SLOT1].CON ? &OPL->output[0] : &OPL->phase_modulation;
1714 break;
1715 case 0xe0: /* waveform select */
1716 /* simply ignore write to the waveform select register if selecting not enabled in test register */
1717 if(OPL->wavesel)
1718 {
1719 slot = slot_array[r&0x1f];
1720 if(slot < 0) return;
1721 CH = &OPL->P_CH[slot/2];
1722
1723 CH->SLOT[slot&1].wavetable = (v&0x03)*SIN_LEN;
1724 }
1725 break;
1726 }
1727 }
1728
1729 #ifdef LOG_CYM_FILE
cymfile_callback(int n)1730 static void cymfile_callback (int n)
1731 {
1732 if (cymfile)
1733 {
1734 fputc( (unsigned char)0, cymfile );
1735 }
1736 }
1737 #endif
1738
1739 /* lock/unlock for common table */
OPL_LockTable(void)1740 static int OPL_LockTable(void)
1741 {
1742 num_lock++;
1743 if(num_lock>1) return 0;
1744
1745 /* first time */
1746
1747 cur_chip = NULL;
1748 /* allocate total level table (128kb space) */
1749 if( !init_tables() )
1750 {
1751 num_lock--;
1752 return -1;
1753 }
1754
1755 #ifdef LOG_CYM_FILE
1756 cymfile = fopen("3812_.cym","wb");
1757 if (cymfile)
1758 timer_pulse ( TIME_IN_HZ(110), 0, cymfile_callback); /*110 Hz pulse timer*/
1759 else
1760 logerror("Could not create file 3812_.cym\n");
1761 #endif
1762
1763 return 0;
1764 }
1765
OPL_UnLockTable(void)1766 static void OPL_UnLockTable(void)
1767 {
1768 if(num_lock) num_lock--;
1769 if(num_lock) return;
1770
1771 /* last time */
1772
1773 cur_chip = NULL;
1774 OPLCloseTable();
1775
1776 #ifdef LOG_CYM_FILE
1777 fclose (cymfile);
1778 cymfile = NULL;
1779 #endif
1780
1781 }
1782
OPLResetChip(FM_OPL * OPL)1783 static void OPLResetChip(FM_OPL *OPL)
1784 {
1785 int c,s;
1786 int i;
1787
1788 OPL->eg_timer = 0;
1789 OPL->eg_cnt = 0;
1790
1791 OPL->noise_rng = 1; /* noise shift register */
1792 OPL->mode = 0; /* normal mode */
1793 OPL_STATUS_RESET(OPL,0x7f);
1794
1795 /* reset with register write */
1796 OPLWriteReg(OPL,0x01,0); /* wavesel disable */
1797 OPLWriteReg(OPL,0x02,0); /* Timer1 */
1798 OPLWriteReg(OPL,0x03,0); /* Timer2 */
1799 OPLWriteReg(OPL,0x04,0); /* IRQ mask clear */
1800 for(i = 0xff ; i >= 0x20 ; i-- ) OPLWriteReg(OPL,i,0);
1801
1802 /* reset operator parameters */
1803 for( c = 0 ; c < 9 ; c++ )
1804 {
1805 OPL_CH *CH = &OPL->P_CH[c];
1806 for(s = 0 ; s < 2 ; s++ )
1807 {
1808 /* wave table */
1809 CH->SLOT[s].wavetable = 0;
1810 CH->SLOT[s].state = EG_OFF;
1811 CH->SLOT[s].volume = MAX_ATT_INDEX;
1812 }
1813 }
1814 #if BUILD_Y8950
1815 if(OPL->type&OPL_TYPE_ADPCM)
1816 {
1817 YM_DELTAT *DELTAT = OPL->deltat;
1818
1819 DELTAT->freqbase = OPL->freqbase;
1820 DELTAT->output_pointer = &OPL->output_deltat[0];
1821 DELTAT->portshift = 5;
1822 DELTAT->output_range = 1<<23;
1823 YM_DELTAT_ADPCM_Reset(DELTAT,0,YM_DELTAT_EMULATION_MODE_NORMAL);
1824 }
1825 #endif
1826 }
1827
1828 /* Create one of virtual YM3812/YM3526/Y8950 */
1829 /* 'clock' is chip clock in Hz */
1830 /* 'rate' is sampling rate */
OPLCreate(int type,int clock,int rate)1831 static FM_OPL *OPLCreate(int type, int clock, int rate)
1832 {
1833 char *ptr;
1834 FM_OPL *OPL;
1835 int state_size;
1836
1837 if (OPL_LockTable() ==-1) return NULL;
1838
1839 /* calculate OPL state size */
1840 state_size = sizeof(FM_OPL);
1841
1842 #if BUILD_Y8950
1843 if (type&OPL_TYPE_ADPCM) state_size+= sizeof(YM_DELTAT);
1844 #endif
1845
1846 /* allocate memory block */
1847 ptr = malloc(state_size);
1848
1849 if (ptr==NULL)
1850 return NULL;
1851
1852 /* clear */
1853 memset(ptr,0,state_size);
1854
1855 OPL = (FM_OPL *)ptr;
1856
1857 ptr += sizeof(FM_OPL);
1858
1859 #if BUILD_Y8950
1860 if (type&OPL_TYPE_ADPCM)
1861 {
1862 OPL->deltat = (YM_DELTAT *)ptr;
1863 }
1864 ptr += sizeof(YM_DELTAT);
1865 #endif
1866
1867 OPL->type = type;
1868 OPL->clock = clock;
1869 OPL->rate = rate;
1870
1871 /* init global tables */
1872 OPL_initalize(OPL);
1873
1874 return OPL;
1875 }
1876
1877 /* Destroy one of virtual YM3812 */
OPLDestroy(FM_OPL * OPL)1878 static void OPLDestroy(FM_OPL *OPL)
1879 {
1880 OPL_UnLockTable();
1881 if (OPL) {
1882 free(OPL);
1883 OPL = NULL;
1884 }
1885 }
1886
1887 /* Optional handlers */
1888
OPLSetTimerHandler(FM_OPL * OPL,OPL_TIMERHANDLER TimerHandler,int channelOffset)1889 static void OPLSetTimerHandler(FM_OPL *OPL,OPL_TIMERHANDLER TimerHandler,int channelOffset)
1890 {
1891 OPL->TimerHandler = TimerHandler;
1892 OPL->TimerParam = channelOffset;
1893 }
OPLSetIRQHandler(FM_OPL * OPL,OPL_IRQHANDLER IRQHandler,int param)1894 static void OPLSetIRQHandler(FM_OPL *OPL,OPL_IRQHANDLER IRQHandler,int param)
1895 {
1896 OPL->IRQHandler = IRQHandler;
1897 OPL->IRQParam = param;
1898 }
OPLSetUpdateHandler(FM_OPL * OPL,OPL_UPDATEHANDLER UpdateHandler,int param)1899 static void OPLSetUpdateHandler(FM_OPL *OPL,OPL_UPDATEHANDLER UpdateHandler,int param)
1900 {
1901 OPL->UpdateHandler = UpdateHandler;
1902 OPL->UpdateParam = param;
1903 }
1904
OPLWrite(FM_OPL * OPL,int a,int v)1905 static int OPLWrite(FM_OPL *OPL,int a,int v)
1906 {
1907 if( !(a&1) )
1908 { /* address port */
1909 OPL->address = v & 0xff;
1910 }
1911 else
1912 { /* data port */
1913 if(OPL->UpdateHandler) OPL->UpdateHandler(OPL->UpdateParam,0);
1914 OPLWriteReg(OPL,OPL->address,v);
1915 }
1916 return OPL->status>>7;
1917 }
1918
OPLRead(FM_OPL * OPL,int a)1919 static unsigned char OPLRead(FM_OPL *OPL,int a)
1920 {
1921 if( !(a&1) )
1922 {
1923 /* status port */
1924
1925 #if BUILD_Y8950
1926
1927 if(OPL->type&OPL_TYPE_ADPCM) /* Y8950 */
1928 {
1929 return (OPL->status & (OPL->statusmask|0x80)) | (OPL->deltat->PCM_BSY&1);
1930 }
1931
1932 #endif
1933
1934 /* OPL and OPL2 */
1935 return OPL->status & (OPL->statusmask|0x80);
1936 }
1937
1938 #if BUILD_Y8950
1939 /* data port */
1940 switch(OPL->address)
1941 {
1942 case 0x05: /* KeyBoard IN */
1943 if(OPL->type&OPL_TYPE_KEYBOARD)
1944 {
1945 if(OPL->keyboardhandler_r)
1946 return OPL->keyboardhandler_r(OPL->keyboard_param);
1947 else
1948 logerror("Y8950: read unmapped KEYBOARD port\n");
1949 }
1950 return 0;
1951
1952 case 0x0f: /* ADPCM-DATA */
1953 if(OPL->type&OPL_TYPE_ADPCM)
1954 {
1955 UINT8 val;
1956
1957 val = YM_DELTAT_ADPCM_Read(OPL->deltat);
1958 /*logerror("Y8950: read ADPCM value read=%02x\n",val);*/
1959 return val;
1960 }
1961 return 0;
1962
1963 case 0x19: /* I/O DATA */
1964 if(OPL->type&OPL_TYPE_IO)
1965 {
1966 if(OPL->porthandler_r)
1967 return OPL->porthandler_r(OPL->port_param);
1968 else
1969 logerror("Y8950:read unmapped I/O port\n");
1970 }
1971 return 0;
1972 case 0x1a: /* PCM-DATA */
1973 if(OPL->type&OPL_TYPE_ADPCM)
1974 {
1975 logerror("Y8950 A/D convertion is accessed but not implemented !\n");
1976 return 0x80; /* 2's complement PCM data - result from A/D convertion */
1977 }
1978 return 0;
1979 }
1980 #endif
1981
1982 return 0xff;
1983 }
1984
1985 /* CSM Key Controll */
CSMKeyControll(OPL_CH * CH)1986 INLINE void CSMKeyControll(OPL_CH *CH)
1987 {
1988 FM_KEYON (&CH->SLOT[SLOT1], 4);
1989 FM_KEYON (&CH->SLOT[SLOT2], 4);
1990
1991 /* The key off should happen exactly one sample later - not implemented correctly yet */
1992
1993 FM_KEYOFF(&CH->SLOT[SLOT1], ~4);
1994 FM_KEYOFF(&CH->SLOT[SLOT2], ~4);
1995 }
1996
1997
OPLTimerOver(FM_OPL * OPL,int c)1998 static int OPLTimerOver(FM_OPL *OPL,int c)
1999 {
2000 if( c )
2001 { /* Timer B */
2002 OPL_STATUS_SET(OPL,0x20);
2003 }
2004 else
2005 { /* Timer A */
2006 OPL_STATUS_SET(OPL,0x40);
2007 /* CSM mode key,TL controll */
2008 if( OPL->mode & 0x80 )
2009 { /* CSM mode total level latch and auto key on */
2010 int ch;
2011 if(OPL->UpdateHandler) OPL->UpdateHandler(OPL->UpdateParam,0);
2012 for(ch=0; ch<9; ch++)
2013 CSMKeyControll( &OPL->P_CH[ch] );
2014 }
2015 }
2016 /* reload timer */
2017 if (OPL->TimerHandler) (OPL->TimerHandler)(OPL->TimerParam+c,(double)OPL->T[c]*OPL->TimerBase);
2018 return OPL->status>>7;
2019 }
2020
2021
2022 #define MAX_OPL_CHIPS 2
2023
2024
2025 #if (BUILD_YM3812)
2026
2027 static FM_OPL *OPL_YM3812[MAX_OPL_CHIPS]; /* array of pointers to the YM3812's */
2028 static int YM3812NumChips = 0; /* number of chips */
2029
YM3812Init(int num,int clock,int rate)2030 int YM3812Init(int num, int clock, int rate)
2031 {
2032 int i;
2033
2034 if (YM3812NumChips)
2035 return -1; /* duplicate init. */
2036
2037 YM3812NumChips = num;
2038
2039 for (i = 0;i < YM3812NumChips; i++)
2040 {
2041 /* emulator create */
2042 OPL_YM3812[i] = OPLCreate(OPL_TYPE_YM3812,clock,rate);
2043 if(OPL_YM3812[i] == NULL)
2044 {
2045 /* it's really bad - we run out of memeory */
2046 YM3812NumChips = 0;
2047 return -1;
2048 }
2049 /* reset */
2050 YM3812ResetChip(i);
2051 }
2052
2053 return 0;
2054 }
2055
YM3812Shutdown(void)2056 void YM3812Shutdown(void)
2057 {
2058 int i;
2059
2060 for (i = 0;i < YM3812NumChips; i++)
2061 {
2062 /* emulator shutdown */
2063 OPLDestroy(OPL_YM3812[i]);
2064 OPL_YM3812[i] = NULL;
2065 }
2066 YM3812NumChips = 0;
2067 }
YM3812ResetChip(int which)2068 void YM3812ResetChip(int which)
2069 {
2070 OPLResetChip(OPL_YM3812[which]);
2071 }
2072
YM3812Write(int which,int a,int v)2073 int YM3812Write(int which, int a, int v)
2074 {
2075 return OPLWrite(OPL_YM3812[which], a, v);
2076 }
2077
YM3812Read(int which,int a)2078 unsigned char YM3812Read(int which, int a)
2079 {
2080 /* YM3812 always returns bit2 and bit1 in HIGH state */
2081 return OPLRead(OPL_YM3812[which], a) | 0x06 ;
2082 }
YM3812TimerOver(int which,int c)2083 int YM3812TimerOver(int which, int c)
2084 {
2085 return OPLTimerOver(OPL_YM3812[which], c);
2086 }
2087
YM3812SetTimerHandler(int which,OPL_TIMERHANDLER TimerHandler,int channelOffset)2088 void YM3812SetTimerHandler(int which, OPL_TIMERHANDLER TimerHandler, int channelOffset)
2089 {
2090 OPLSetTimerHandler(OPL_YM3812[which], TimerHandler, channelOffset);
2091 }
YM3812SetIRQHandler(int which,OPL_IRQHANDLER IRQHandler,int param)2092 void YM3812SetIRQHandler(int which,OPL_IRQHANDLER IRQHandler,int param)
2093 {
2094 OPLSetIRQHandler(OPL_YM3812[which], IRQHandler, param);
2095 }
YM3812SetUpdateHandler(int which,OPL_UPDATEHANDLER UpdateHandler,int param)2096 void YM3812SetUpdateHandler(int which,OPL_UPDATEHANDLER UpdateHandler,int param)
2097 {
2098 OPLSetUpdateHandler(OPL_YM3812[which], UpdateHandler, param);
2099 }
2100
2101
2102 /*
2103 ** Generate samples for one of the YM3812's
2104 **
2105 ** 'which' is the virtual YM3812 number
2106 ** '*buffer' is the output buffer pointer
2107 ** 'length' is the number of samples that should be generated
2108 */
YM3812UpdateOne(int which,INT16 * buffer,int length)2109 void YM3812UpdateOne(int which, INT16 *buffer, int length)
2110 {
2111 FM_OPL *OPL = OPL_YM3812[which];
2112 UINT8 rhythm = OPL->rhythm&0x20;
2113 OPLSAMPLE *buf = buffer;
2114 int i;
2115
2116 if( (void *)OPL != cur_chip ){
2117 cur_chip = (void *)OPL;
2118 /* rhythm slots */
2119 SLOT7_1 = &OPL->P_CH[7].SLOT[SLOT1];
2120 SLOT7_2 = &OPL->P_CH[7].SLOT[SLOT2];
2121 SLOT8_1 = &OPL->P_CH[8].SLOT[SLOT1];
2122 SLOT8_2 = &OPL->P_CH[8].SLOT[SLOT2];
2123 }
2124 for( i=0; i < length ; i++ )
2125 {
2126 int lt;
2127
2128 OPL->output[0] = 0;
2129
2130 advance_lfo(OPL);
2131
2132 /* FM part */
2133 OPL_CALC_CH(OPL, &OPL->P_CH[0]);
2134 OPL_CALC_CH(OPL, &OPL->P_CH[1]);
2135 OPL_CALC_CH(OPL, &OPL->P_CH[2]);
2136 OPL_CALC_CH(OPL, &OPL->P_CH[3]);
2137 OPL_CALC_CH(OPL, &OPL->P_CH[4]);
2138 OPL_CALC_CH(OPL, &OPL->P_CH[5]);
2139
2140 if(!rhythm)
2141 {
2142 OPL_CALC_CH(OPL, &OPL->P_CH[6]);
2143 OPL_CALC_CH(OPL, &OPL->P_CH[7]);
2144 OPL_CALC_CH(OPL, &OPL->P_CH[8]);
2145 }
2146 else /* Rhythm part */
2147 {
2148 OPL_CALC_RH(OPL, &OPL->P_CH[0], (OPL->noise_rng>>0)&1 );
2149 }
2150
2151 lt = OPL->output[0];
2152
2153 lt >>= FINAL_SH;
2154
2155 /* limit check */
2156 lt = limit( lt , MAXOUT, MINOUT );
2157
2158 #ifdef SAVE_SAMPLE
2159 if (which==0)
2160 {
2161 SAVE_ALL_CHANNELS
2162 }
2163 #endif
2164
2165 /* store to sound buffer */
2166 buf[i] = lt;
2167
2168 advance(OPL);
2169 }
2170
2171 }
2172 #endif /* BUILD_YM3812 */
2173
2174
2175
2176 #if (BUILD_YM3526)
2177
2178 static FM_OPL *OPL_YM3526[MAX_OPL_CHIPS]; /* array of pointers to the YM3526's */
2179 static int YM3526NumChips = 0; /* number of chips */
2180
YM3526Init(int num,int clock,int rate)2181 int YM3526Init(int num, int clock, int rate)
2182 {
2183 int i;
2184
2185 if (YM3526NumChips)
2186 return -1; /* duplicate init. */
2187
2188 YM3526NumChips = num;
2189
2190 for (i = 0;i < YM3526NumChips; i++)
2191 {
2192 /* emulator create */
2193 OPL_YM3526[i] = OPLCreate(OPL_TYPE_YM3526,clock,rate);
2194 if(OPL_YM3526[i] == NULL)
2195 {
2196 /* it's really bad - we run out of memeory */
2197 YM3526NumChips = 0;
2198 return -1;
2199 }
2200 /* reset */
2201 YM3526ResetChip(i);
2202 }
2203
2204 return 0;
2205 }
2206
YM3526Shutdown(void)2207 void YM3526Shutdown(void)
2208 {
2209 int i;
2210
2211 for (i = 0;i < YM3526NumChips; i++)
2212 {
2213 /* emulator shutdown */
2214 OPLDestroy(OPL_YM3526[i]);
2215 OPL_YM3526[i] = NULL;
2216 }
2217 YM3526NumChips = 0;
2218 }
YM3526ResetChip(int which)2219 void YM3526ResetChip(int which)
2220 {
2221 OPLResetChip(OPL_YM3526[which]);
2222 }
2223
YM3526Write(int which,int a,int v)2224 int YM3526Write(int which, int a, int v)
2225 {
2226 return OPLWrite(OPL_YM3526[which], a, v);
2227 }
2228
YM3526Read(int which,int a)2229 unsigned char YM3526Read(int which, int a)
2230 {
2231 /* YM3526 always returns bit2 and bit1 in HIGH state */
2232 return OPLRead(OPL_YM3526[which], a) | 0x06 ;
2233 }
YM3526TimerOver(int which,int c)2234 int YM3526TimerOver(int which, int c)
2235 {
2236 return OPLTimerOver(OPL_YM3526[which], c);
2237 }
2238
YM3526SetTimerHandler(int which,OPL_TIMERHANDLER TimerHandler,int channelOffset)2239 void YM3526SetTimerHandler(int which, OPL_TIMERHANDLER TimerHandler, int channelOffset)
2240 {
2241 OPLSetTimerHandler(OPL_YM3526[which], TimerHandler, channelOffset);
2242 }
YM3526SetIRQHandler(int which,OPL_IRQHANDLER IRQHandler,int param)2243 void YM3526SetIRQHandler(int which,OPL_IRQHANDLER IRQHandler,int param)
2244 {
2245 OPLSetIRQHandler(OPL_YM3526[which], IRQHandler, param);
2246 }
YM3526SetUpdateHandler(int which,OPL_UPDATEHANDLER UpdateHandler,int param)2247 void YM3526SetUpdateHandler(int which,OPL_UPDATEHANDLER UpdateHandler,int param)
2248 {
2249 OPLSetUpdateHandler(OPL_YM3526[which], UpdateHandler, param);
2250 }
2251
2252
2253 /*
2254 ** Generate samples for one of the YM3526's
2255 **
2256 ** 'which' is the virtual YM3526 number
2257 ** '*buffer' is the output buffer pointer
2258 ** 'length' is the number of samples that should be generated
2259 */
YM3526UpdateOne(int which,INT16 * buffer,int length)2260 void YM3526UpdateOne(int which, INT16 *buffer, int length)
2261 {
2262 FM_OPL *OPL = OPL_YM3526[which];
2263 UINT8 rhythm = OPL->rhythm&0x20;
2264 OPLSAMPLE *buf = buffer;
2265 int i;
2266
2267 if( (void *)OPL != cur_chip ){
2268 cur_chip = (void *)OPL;
2269 /* rhythm slots */
2270 SLOT7_1 = &OPL->P_CH[7].SLOT[SLOT1];
2271 SLOT7_2 = &OPL->P_CH[7].SLOT[SLOT2];
2272 SLOT8_1 = &OPL->P_CH[8].SLOT[SLOT1];
2273 SLOT8_2 = &OPL->P_CH[8].SLOT[SLOT2];
2274 }
2275 for( i=0; i < length ; i++ )
2276 {
2277 int lt;
2278
2279 OPL->output[0] = 0;
2280
2281 advance_lfo(OPL);
2282
2283 /* FM part */
2284 OPL_CALC_CH(OPL, &OPL->P_CH[0]);
2285 OPL_CALC_CH(OPL, &OPL->P_CH[1]);
2286 OPL_CALC_CH(OPL, &OPL->P_CH[2]);
2287 OPL_CALC_CH(OPL, &OPL->P_CH[3]);
2288 OPL_CALC_CH(OPL, &OPL->P_CH[4]);
2289 OPL_CALC_CH(OPL, &OPL->P_CH[5]);
2290
2291 if(!rhythm)
2292 {
2293 OPL_CALC_CH(OPL, &OPL->P_CH[6]);
2294 OPL_CALC_CH(OPL, &OPL->P_CH[7]);
2295 OPL_CALC_CH(OPL, &OPL->P_CH[8]);
2296 }
2297 else /* Rhythm part */
2298 {
2299 OPL_CALC_RH(OPL, &OPL->P_CH[0], (OPL->noise_rng>>0)&1 );
2300 }
2301
2302 lt = OPL->output[0];
2303
2304 lt >>= FINAL_SH;
2305
2306 /* limit check */
2307 lt = limit( lt , MAXOUT, MINOUT );
2308
2309 #ifdef SAVE_SAMPLE
2310 if (which==0)
2311 {
2312 SAVE_ALL_CHANNELS
2313 }
2314 #endif
2315
2316 /* store to sound buffer */
2317 buf[i] = lt;
2318
2319 advance(OPL);
2320 }
2321
2322 }
2323 #endif /* BUILD_YM3526 */
2324
2325
2326
2327
2328 #if BUILD_Y8950
2329
2330 static FM_OPL *OPL_Y8950[MAX_OPL_CHIPS]; /* array of pointers to the Y8950's */
2331 static int Y8950NumChips = 0; /* number of chips */
2332
Y8950_deltat_status_set(UINT8 which,UINT8 changebits)2333 static void Y8950_deltat_status_set(UINT8 which, UINT8 changebits)
2334 {
2335 OPL_STATUS_SET(OPL_Y8950[which], changebits);
2336 }
Y8950_deltat_status_reset(UINT8 which,UINT8 changebits)2337 static void Y8950_deltat_status_reset(UINT8 which, UINT8 changebits)
2338 {
2339 OPL_STATUS_RESET(OPL_Y8950[which], changebits);
2340 }
2341
Y8950Init(int num,int clock,int rate)2342 int Y8950Init(int num, int clock, int rate)
2343 {
2344 int i;
2345
2346 if (Y8950NumChips)
2347 return -1; /* duplicate init. */
2348
2349 Y8950NumChips = num;
2350
2351 for (i = 0;i < Y8950NumChips; i++)
2352 {
2353 /* emulator create */
2354 OPL_Y8950[i] = OPLCreate(OPL_TYPE_Y8950,clock,rate);
2355 if(OPL_Y8950[i] == NULL)
2356 {
2357 /* it's really bad - we run out of memeory */
2358 Y8950NumChips = 0;
2359 return -1;
2360 }
2361 OPL_Y8950[i]->deltat->status_set_handler = Y8950_deltat_status_set;
2362 OPL_Y8950[i]->deltat->status_reset_handler = Y8950_deltat_status_reset;
2363 OPL_Y8950[i]->deltat->status_change_which_chip = i;
2364 OPL_Y8950[i]->deltat->status_change_EOS_bit = 0x10; /* status flag: set bit4 on End Of Sample */
2365 OPL_Y8950[i]->deltat->status_change_BRDY_bit = 0x08; /* status flag: set bit3 on BRDY (End Of: ADPCM analysis/synthesis, memory reading/writing) */
2366
2367 /*OPL_Y8950[i]->deltat->write_time = 10.0 / clock;*/ /* a single byte write takes 10 cycles of main clock */
2368 /*OPL_Y8950[i]->deltat->read_time = 8.0 / clock;*/ /* a single byte read takes 8 cycles of main clock */
2369 /* reset */
2370 Y8950ResetChip(i);
2371 }
2372
2373 return 0;
2374 }
2375
Y8950Shutdown(void)2376 void Y8950Shutdown(void)
2377 {
2378 int i;
2379
2380 for (i = 0;i < Y8950NumChips; i++)
2381 {
2382 /* emulator shutdown */
2383 OPLDestroy(OPL_Y8950[i]);
2384 OPL_Y8950[i] = NULL;
2385 }
2386 Y8950NumChips = 0;
2387 }
Y8950ResetChip(int which)2388 void Y8950ResetChip(int which)
2389 {
2390 OPLResetChip(OPL_Y8950[which]);
2391 }
2392
Y8950Write(int which,int a,int v)2393 int Y8950Write(int which, int a, int v)
2394 {
2395 return OPLWrite(OPL_Y8950[which], a, v);
2396 }
2397
Y8950Read(int which,int a)2398 unsigned char Y8950Read(int which, int a)
2399 {
2400 return OPLRead(OPL_Y8950[which], a);
2401 }
Y8950TimerOver(int which,int c)2402 int Y8950TimerOver(int which, int c)
2403 {
2404 return OPLTimerOver(OPL_Y8950[which], c);
2405 }
2406
Y8950SetTimerHandler(int which,OPL_TIMERHANDLER TimerHandler,int channelOffset)2407 void Y8950SetTimerHandler(int which, OPL_TIMERHANDLER TimerHandler, int channelOffset)
2408 {
2409 OPLSetTimerHandler(OPL_Y8950[which], TimerHandler, channelOffset);
2410 }
Y8950SetIRQHandler(int which,OPL_IRQHANDLER IRQHandler,int param)2411 void Y8950SetIRQHandler(int which,OPL_IRQHANDLER IRQHandler,int param)
2412 {
2413 OPLSetIRQHandler(OPL_Y8950[which], IRQHandler, param);
2414 }
Y8950SetUpdateHandler(int which,OPL_UPDATEHANDLER UpdateHandler,int param)2415 void Y8950SetUpdateHandler(int which,OPL_UPDATEHANDLER UpdateHandler,int param)
2416 {
2417 OPLSetUpdateHandler(OPL_Y8950[which], UpdateHandler, param);
2418 }
2419
Y8950SetDeltaTMemory(int which,void * deltat_mem_ptr,int deltat_mem_size)2420 void Y8950SetDeltaTMemory(int which, void * deltat_mem_ptr, int deltat_mem_size )
2421 {
2422 FM_OPL *OPL = OPL_Y8950[which];
2423 OPL->deltat->memory = (UINT8 *)(deltat_mem_ptr);
2424 OPL->deltat->memory_size = deltat_mem_size;
2425 }
2426
2427 /*
2428 ** Generate samples for one of the Y8950's
2429 **
2430 ** 'which' is the virtual Y8950 number
2431 ** '*buffer' is the output buffer pointer
2432 ** 'length' is the number of samples that should be generated
2433 */
Y8950UpdateOne(int which,INT16 * buffer,int length)2434 void Y8950UpdateOne(int which, INT16 *buffer, int length)
2435 {
2436 int i;
2437 FM_OPL *OPL = OPL_Y8950[which];
2438 UINT8 rhythm = OPL->rhythm&0x20;
2439 YM_DELTAT *DELTAT = OPL->deltat;
2440 OPLSAMPLE *buf = buffer;
2441
2442 if( (void *)OPL != cur_chip ){
2443 cur_chip = (void *)OPL;
2444 /* rhythm slots */
2445 SLOT7_1 = &OPL->P_CH[7].SLOT[SLOT1];
2446 SLOT7_2 = &OPL->P_CH[7].SLOT[SLOT2];
2447 SLOT8_1 = &OPL->P_CH[8].SLOT[SLOT1];
2448 SLOT8_2 = &OPL->P_CH[8].SLOT[SLOT2];
2449
2450 }
2451 for( i=0; i < length ; i++ )
2452 {
2453 int lt;
2454
2455 OPL->output[0] = 0;
2456 OPL->output_deltat[0] = 0;
2457
2458 advance_lfo(OPL);
2459
2460 /* deltaT ADPCM */
2461 if( DELTAT->portstate&0x80 )
2462 YM_DELTAT_ADPCM_CALC(DELTAT);
2463
2464 /* FM part */
2465 OPL_CALC_CH(OPL, &OPL->P_CH[0]);
2466 OPL_CALC_CH(OPL, &OPL->P_CH[1]);
2467 OPL_CALC_CH(OPL, &OPL->P_CH[2]);
2468 OPL_CALC_CH(OPL, &OPL->P_CH[3]);
2469 OPL_CALC_CH(OPL, &OPL->P_CH[4]);
2470 OPL_CALC_CH(OPL, &OPL->P_CH[5]);
2471
2472 if(!rhythm)
2473 {
2474 OPL_CALC_CH(OPL, &OPL->P_CH[6]);
2475 OPL_CALC_CH(OPL, &OPL->P_CH[7]);
2476 OPL_CALC_CH(OPL, &OPL->P_CH[8]);
2477 }
2478 else /* Rhythm part */
2479 {
2480 OPL_CALC_RH(OPL, &OPL->P_CH[0], (OPL->noise_rng>>0)&1 );
2481 }
2482
2483 lt = OPL->output[0] + (OPL->output_deltat[0]>>11);
2484
2485 lt >>= FINAL_SH;
2486
2487 /* limit check */
2488 lt = limit( lt , MAXOUT, MINOUT );
2489
2490 #ifdef SAVE_SAMPLE
2491 if (which==0)
2492 {
2493 SAVE_ALL_CHANNELS
2494 }
2495 #endif
2496
2497 /* store to sound buffer */
2498 buf[i] = lt;
2499
2500 advance(OPL);
2501 }
2502
2503 }
2504
Y8950SetPortHandler(int which,OPL_PORTHANDLER_W PortHandler_w,OPL_PORTHANDLER_R PortHandler_r,int param)2505 void Y8950SetPortHandler(int which,OPL_PORTHANDLER_W PortHandler_w,OPL_PORTHANDLER_R PortHandler_r,int param)
2506 {
2507 FM_OPL *OPL = OPL_Y8950[which];
2508 OPL->porthandler_w = PortHandler_w;
2509 OPL->porthandler_r = PortHandler_r;
2510 OPL->port_param = param;
2511 }
2512
Y8950SetKeyboardHandler(int which,OPL_PORTHANDLER_W KeyboardHandler_w,OPL_PORTHANDLER_R KeyboardHandler_r,int param)2513 void Y8950SetKeyboardHandler(int which,OPL_PORTHANDLER_W KeyboardHandler_w,OPL_PORTHANDLER_R KeyboardHandler_r,int param)
2514 {
2515 FM_OPL *OPL = OPL_Y8950[which];
2516 OPL->keyboardhandler_w = KeyboardHandler_w;
2517 OPL->keyboardhandler_r = KeyboardHandler_r;
2518 OPL->keyboard_param = param;
2519 }
2520
2521 #endif
2522
FMOPLScan(INT32 nType,INT32 which,INT32 nAction,INT32 * pnMin)2523 void FMOPLScan(INT32 nType, INT32 which, INT32 nAction, INT32 *pnMin)
2524 {
2525 FM_OPL *OPL = OPL_YM3812[which];
2526
2527 if (nType == FM_OPL_SAVESTATE_YM3526) {
2528 OPL = OPL_YM3526[which];
2529 }
2530
2531 if (nType == FM_OPL_SAVESTATE_Y8950) {
2532 OPL = OPL_Y8950[which];
2533 }
2534
2535 if (nAction & ACB_DRIVER_DATA) {
2536 INT32 ch;
2537 INT32 slot;
2538 for (ch = 0; ch < 9; ch++) {
2539 OPL_CH *CH = &OPL->P_CH[ch];
2540
2541 SCAN_VAR(CH->block_fnum);
2542 SCAN_VAR(CH->kcode);
2543
2544 for (slot = 0; slot < 2; slot++) {
2545 OPL_SLOT *SLOT = &CH->SLOT[slot];
2546
2547 SCAN_VAR(SLOT->ar);
2548 SCAN_VAR(SLOT->dr);
2549 SCAN_VAR(SLOT->rr);
2550 SCAN_VAR(SLOT->KSR);
2551 SCAN_VAR(SLOT->ksl);
2552 SCAN_VAR(SLOT->mul);
2553
2554 SCAN_VAR(SLOT->Cnt);
2555 SCAN_VAR(SLOT->FB);
2556 SCAN_VAR(SLOT->op1_out);
2557 SCAN_VAR(SLOT->CON);
2558
2559 SCAN_VAR(SLOT->eg_type);
2560 SCAN_VAR(SLOT->state);
2561 SCAN_VAR(SLOT->TL);
2562 SCAN_VAR(SLOT->volume);
2563 SCAN_VAR(SLOT->sl);
2564 SCAN_VAR(SLOT->key);
2565
2566 SCAN_VAR(SLOT->AMmask);
2567 SCAN_VAR(SLOT->vib);
2568
2569 SCAN_VAR(SLOT->wavetable);
2570 }
2571 }
2572
2573 SCAN_VAR(OPL->eg_cnt);
2574 SCAN_VAR(OPL->eg_timer);
2575
2576 SCAN_VAR(OPL->rhythm);
2577
2578 SCAN_VAR(OPL->lfo_am_depth);
2579 SCAN_VAR(OPL->lfo_pm_depth_range);
2580 SCAN_VAR(OPL->lfo_am_cnt);
2581 SCAN_VAR(OPL->lfo_pm_cnt);
2582
2583 SCAN_VAR(OPL->noise_rng);
2584 SCAN_VAR(OPL->noise_p);
2585
2586 if (OPL->type & OPL_TYPE_WAVESEL) {
2587 SCAN_VAR(OPL->wavesel);
2588 }
2589
2590 SCAN_VAR(OPL->T);
2591 SCAN_VAR(OPL->st);
2592
2593 #if BUILD_Y8950
2594 if ((OPL->type & OPL_TYPE_ADPCM) && (OPL->deltat)) {
2595 SCAN_VAR(OPL->deltat->portstate);
2596 SCAN_VAR(OPL->deltat->now_addr);
2597 SCAN_VAR(OPL->deltat->now_step);
2598 SCAN_VAR(OPL->deltat->acc);
2599 SCAN_VAR(OPL->deltat->prev_acc);
2600 SCAN_VAR(OPL->deltat->adpcmd);
2601 SCAN_VAR(OPL->deltat->adpcml);
2602 }
2603
2604 if (OPL->type & OPL_TYPE_IO) {
2605 SCAN_VAR(OPL->portDirection);
2606 SCAN_VAR(OPL->portLatch);
2607 }
2608 #endif
2609
2610 SCAN_VAR(OPL->address);
2611 SCAN_VAR(OPL->status);
2612 SCAN_VAR(OPL->statusmask);
2613 SCAN_VAR(OPL->mode);
2614
2615 #if BUILD_Y8950
2616 if ((OPL->type & OPL_TYPE_ADPCM) && (OPL->deltat)) {
2617 YM_DELTAT *DELTAT = OPL->deltat;
2618 SCAN_VAR(DELTAT->portstate);
2619 SCAN_VAR(DELTAT->now_addr);
2620 SCAN_VAR(DELTAT->now_step);
2621 SCAN_VAR(DELTAT->acc);
2622 SCAN_VAR(DELTAT->prev_acc);
2623 SCAN_VAR(DELTAT->adpcmd);
2624 SCAN_VAR(DELTAT->adpcml);
2625 }
2626 #endif
2627
2628 if (nAction & ACB_WRITE) {
2629 INT32 ch;
2630 INT32 slot;
2631 for (ch = 0; ch < 9; ch++) {
2632 OPL_CH *CH = &OPL->P_CH[ch];
2633
2634 UINT32 block_fnum = CH->block_fnum;
2635 CH->ksl_base = ksl_tab[block_fnum >> 6];
2636 CH->fc = OPL->fn_tab[block_fnum & 0x03ff] >> (7 - (block_fnum >> 10));
2637
2638 for (slot = 0; slot < 2; slot++) {
2639 OPL_SLOT *SLOT = &CH->SLOT[slot];
2640
2641 SLOT->ksr = CH->kcode >> SLOT->KSR;
2642
2643 if ((SLOT->ar + SLOT->ksr) < 16 + 62) {
2644 SLOT->eg_sh_ar = eg_rate_shift [SLOT->ar + SLOT->ksr ];
2645 SLOT->eg_sel_ar = eg_rate_select[SLOT->ar + SLOT->ksr ];
2646 } else {
2647 SLOT->eg_sh_ar = 0;
2648 SLOT->eg_sel_ar = 13*RATE_STEPS;
2649 }
2650 SLOT->eg_sh_dr = eg_rate_shift [SLOT->dr + SLOT->ksr ];
2651 SLOT->eg_sel_dr = eg_rate_select[SLOT->dr + SLOT->ksr ];
2652 SLOT->eg_sh_rr = eg_rate_shift [SLOT->rr + SLOT->ksr ];
2653 SLOT->eg_sel_rr = eg_rate_select[SLOT->rr + SLOT->ksr ];
2654
2655 SLOT->Incr = CH->fc * SLOT->mul;
2656
2657 SLOT->TLL = SLOT->TL + (CH->ksl_base >> SLOT->ksl);
2658
2659 SLOT->connect1 = SLOT->CON ? &OPL->output[0] : &OPL->phase_modulation;
2660 }
2661 }
2662 #if BUILD_Y8950
2663 if ((OPL->type & OPL_TYPE_ADPCM) && (OPL->deltat)) {
2664 // We really should call the postlod function for the YM_DELTAT, but it's hard without registers
2665 // (see the way the YM2610 does it)
2666 //YM_DELTAT_postload(OPL->deltat, REGS);
2667 }
2668 #endif
2669 }
2670 }
2671 }
2672