1 /*
2 **
3 ** File: ymf262.c - software implementation of YMF262
4 ** FM sound generator type OPL3
5 **
6 ** Copyright Jarek Burczynski
7 **
8 ** Version 0.2
9 **
10
11 Revision History:
12
13 03-03-2003: initial release
14 - thanks to Olivier Galibert and Chris Hardy for YMF262 and YAC512 chips
15 - thanks to Stiletto for the datasheets
16
17 Features as listed in 4MF262A6 data sheet:
18 1. Registers are compatible with YM3812 (OPL2) FM sound source.
19 2. Up to six sounds can be used as four-operator melody sounds for variety.
20 3. 18 simultaneous melody sounds, or 15 melody sounds with 5 rhythm sounds (with two operators).
21 4. 6 four-operator melody sounds and 6 two-operator melody sounds, or 6 four-operator melody
22 sounds, 3 two-operator melody sounds and 5 rhythm sounds (with four operators).
23 5. 8 selectable waveforms.
24 6. 4-channel sound output.
25 7. YMF262 compabile DAC (YAC512) is available.
26 8. LFO for vibrato and tremolo effedts.
27 9. 2 programable timers.
28 10. Shorter register access time compared with YM3812.
29 11. 5V single supply silicon gate CMOS process.
30 12. 24 Pin SOP Package (YMF262-M), 48 Pin SQFP Package (YMF262-S).
31
32
33 differences between OPL2 and OPL3 not documented in Yamaha datahasheets:
34 - sinus table is a little different: the negative part is off by one...
35
36 - in order to enable selection of four different waveforms on OPL2
37 one must set bit 5 in register 0x01(test).
38 on OPL3 this bit is ignored and 4-waveform select works *always*.
39 (Don't confuse this with OPL3's 8-waveform select.)
40
41 - Envelope Generator: all 15 x rates take zero time on OPL3
42 (on OPL2 15 0 and 15 1 rates take some time while 15 2 and 15 3 rates
43 take zero time)
44
45 - channel calculations: output of operator 1 is in perfect sync with
46 output of operator 2 on OPL3; on OPL and OPL2 output of operator 1
47 is always delayed by one sample compared to output of operator 2
48
49
50 differences between OPL2 and OPL3 shown in datasheets:
51 - YMF262 does not support CSM mode
52
53
54 */
55
56 #if defined (_MSC_VER)
57 #define _USE_MATH_DEFINES
58 #endif
59
60 #include <math.h>
61 #include "driver.h"
62 #include "ymf262.h"
63 #include "state.h"
64
65 /* output final shift */
66 #if (OPL3_SAMPLE_BITS==16)
67 #define FINAL_SH (0)
68 #define MAXOUT (+32767)
69 #define MINOUT (-32768)
70 #else
71 #define FINAL_SH (8)
72 #define MAXOUT (+127)
73 #define MINOUT (-128)
74 #endif
75
76
77 #define FREQ_SH 16 /* 16.16 fixed point (frequency calculations) */
78 #define EG_SH 16 /* 16.16 fixed point (EG timing) */
79 #define LFO_SH 24 /* 8.24 fixed point (LFO calculations) */
80 #define TIMER_SH 16 /* 16.16 fixed point (timers calculations) */
81
82 #define FREQ_MASK ((1<<FREQ_SH)-1)
83
84 /* envelope output entries */
85 #define ENV_BITS 10
86 #define ENV_LEN (1<<ENV_BITS)
87 #define ENV_STEP (128.0/ENV_LEN)
88
89 #define MAX_ATT_INDEX ((1<<(ENV_BITS-1))-1) /*511*/
90 #define MIN_ATT_INDEX (0)
91
92 /* sinwave entries */
93 #define SIN_BITS 10
94 #define SIN_LEN (1<<SIN_BITS)
95 #define SIN_MASK (SIN_LEN-1)
96
97 #define TL_RES_LEN (256) /* 8 bits addressing (real chip) */
98
99
100
101 /* register number to channel number , slot offset */
102 #define SLOT1 0
103 #define SLOT2 1
104
105 /* Envelope Generator phases */
106
107 #define EG_ATT 4
108 #define EG_DEC 3
109 #define EG_SUS 2
110 #define EG_REL 1
111 #define EG_OFF 0
112
113 /* Routing connections between slots */
114 #define CONN_NULL 0
115 #define CONN_CHAN0 1
116 #define CONN_PHASEMOD 19
117 #define CONN_PHASEMOD2 20
118
119 /* save output as raw 16-bit sample */
120
121 /*#define SAVE_SAMPLE*/
122
123 #ifdef SAVE_SAMPLE
124 static FILE *sample[1];
125 #if 1 /*save to MONO file */
126 #define SAVE_ALL_CHANNELS \
127 { signed int pom = a; \
128 fputc((unsigned short)pom&0xff,sample[0]); \
129 fputc(((unsigned short)pom>>8)&0xff,sample[0]); \
130 }
131 #else /*save to STEREO file */
132 #define SAVE_ALL_CHANNELS \
133 { signed int pom = a; \
134 fputc((unsigned short)pom&0xff,sample[0]); \
135 fputc(((unsigned short)pom>>8)&0xff,sample[0]); \
136 pom = b; \
137 fputc((unsigned short)pom&0xff,sample[0]); \
138 fputc(((unsigned short)pom>>8)&0xff,sample[0]); \
139 }
140 #endif
141 #endif
142
143
144
145
146
147
148 #define OPL3_TYPE_YMF262 (0) /* 36 operators, 8 waveforms */
149
150
151 struct OPL3_SLOT
152 {
153 UINT32 ar; /* attack rate: AR<<2 */
154 UINT32 dr; /* decay rate: DR<<2 */
155 UINT32 rr; /* release rate:RR<<2 */
156 UINT8 KSR; /* key scale rate */
157 UINT8 ksl; /* keyscale level */
158 UINT8 ksr; /* key scale rate: kcode>>KSR */
159 UINT8 mul; /* multiple: mul_tab[ML] */
160
161 /* Phase Generator */
162 UINT32 Cnt; /* frequency counter */
163 UINT32 Incr; /* frequency counter step */
164 UINT8 FB; /* feedback shift value */
165 UINT8 conn_enum; /* slot output route */
166 INT32 *connect; /* slot output pointer */
167 INT32 op1_out[2]; /* slot1 output for feedback */
168 UINT8 CON; /* connection (algorithm) type */
169
170 /* Envelope Generator */
171 UINT8 eg_type; /* percussive/non-percussive mode */
172 UINT8 state; /* phase type */
173 UINT32 TL; /* total level: TL << 2 */
174 INT32 TLL; /* adjusted now TL */
175 INT32 volume; /* envelope counter */
176 UINT32 sl; /* sustain level: sl_tab[SL] */
177
178 UINT32 eg_m_ar; /* (attack state) */
179 UINT8 eg_sh_ar; /* (attack state) */
180 UINT8 eg_sel_ar; /* (attack state) */
181 UINT32 eg_m_dr; /* (decay state) */
182 UINT8 eg_sh_dr; /* (decay state) */
183 UINT8 eg_sel_dr; /* (decay state) */
184 UINT32 eg_m_rr; /* (release state) */
185 UINT8 eg_sh_rr; /* (release state) */
186 UINT8 eg_sel_rr; /* (release state) */
187
188 UINT32 key; /* 0 = KEY OFF, >0 = KEY ON */
189
190 /* LFO */
191 UINT32 AMmask; /* LFO Amplitude Modulation enable mask */
192 UINT8 vib; /* LFO Phase Modulation enable flag (active high)*/
193
194 /* waveform select */
195 UINT8 waveform_number;
196 unsigned int wavetable;
197
198 //unsigned char reserved[128-84];//speedup: pump up the struct size to power of 2
199 unsigned char reserved[128-100];//speedup: pump up the struct size to power of 2
200
201 };
202
203 struct OPL3_CH
204 {
205 OPL3_SLOT SLOT[2];
206
207 UINT32 block_fnum; /* block+fnum */
208 UINT32 fc; /* Freq. Increment base */
209 UINT32 ksl_base; /* KeyScaleLevel Base step */
210 UINT8 kcode; /* key code (for key scaling) */
211
212 /*
213 there are 12 2-operator channels which can be combined in pairs
214 to form six 4-operator channel, they are:
215 0 and 3,
216 1 and 4,
217 2 and 5,
218 9 and 12,
219 10 and 13,
220 11 and 14
221 */
222 UINT8 extended; /* set to 1 if this channel forms up a 4op channel with another channel(only used by first of pair of channels, ie 0,1,2 and 9,10,11) */
223
224 unsigned char reserved[512-272];//speedup:pump up the struct size to power of 2
225
226 };
227
228 /* OPL3 state */
229 struct OPL3
230 {
231 OPL3_CH P_CH[18]; /* OPL3 chips have 18 channels */
232
233 UINT32 pan[18*4]; /* channels output masks (0xffffffff = enable); 4 masks per one channel */
234 UINT32 pan_ctrl_value[18]; /* output control values 1 per one channel (1 value contains 4 masks) */
235
236 signed int chanout[18];
237 signed int phase_modulation; /* phase modulation input (SLOT 2) */
238 signed int phase_modulation2; /* phase modulation input (SLOT 3 in 4 operator channels) */
239
240 UINT32 eg_cnt; /* global envelope generator counter */
241 UINT32 eg_timer; /* global envelope generator counter works at frequency = chipclock/288 (288=8*36) */
242 UINT32 eg_timer_add; /* step of eg_timer */
243 UINT32 eg_timer_overflow; /* envelope generator timer overlfows every 1 sample (on real chip) */
244
245 UINT32 fn_tab[1024]; /* fnumber->increment counter */
246
247 /* LFO */
248 UINT32 LFO_AM;
249 INT32 LFO_PM;
250
251 UINT8 lfo_am_depth;
252 UINT8 lfo_pm_depth_range;
253 UINT32 lfo_am_cnt;
254 UINT32 lfo_am_inc;
255 UINT32 lfo_pm_cnt;
256 UINT32 lfo_pm_inc;
257
258 UINT32 noise_rng; /* 23 bit noise shift register */
259 UINT32 noise_p; /* current noise 'phase' */
260 UINT32 noise_f; /* current noise period */
261
262 UINT8 OPL3_mode; /* OPL3 extension enable flag */
263
264 UINT8 rhythm; /* Rhythm mode */
265
266 int T[2]; /* timer counters */
267 UINT8 st[2]; /* timer enable */
268
269 UINT32 address; /* address register */
270 UINT8 status; /* status flag */
271 UINT8 statusmask; /* status mask */
272
273 UINT8 nts; /* NTS (note select) */
274
275 /* external event callback handlers */
276 OPL3_TIMERHANDLER timer_handler;/* TIMER handler */
277 OPL3_IRQHANDLER IRQHandler; /* IRQ handler */
278 OPL3_UPDATEHANDLER UpdateHandler;/* stream update handler */
279
280 UINT8 type; /* chip type */
281 int clock; /* master clock (Hz) */
282 int rate; /* sampling rate (Hz) */
283 double freqbase; /* frequency base */
284 double TimerBase; /* Timer base time (==sampling time)*/
285 };
286
287
288
289 /* mapping of register number (offset) to slot number used by the emulator */
290 static const int slot_array[32]=
291 {
292 0, 2, 4, 1, 3, 5,-1,-1,
293 6, 8,10, 7, 9,11,-1,-1,
294 12,14,16,13,15,17,-1,-1,
295 -1,-1,-1,-1,-1,-1,-1,-1
296 };
297
298 /* key scale level */
299 /* table is 3dB/octave , DV converts this into 6dB/octave */
300 /* 0.1875 is bit 0 weight of the envelope counter (volume) expressed in the 'decibel' scale */
301 #define DV (0.1875/2.0)
302 static const double ksl_tab[8*16]=
303 {
304 /* OCT 0 */
305 0.000/DV, 0.000/DV, 0.000/DV, 0.000/DV,
306 0.000/DV, 0.000/DV, 0.000/DV, 0.000/DV,
307 0.000/DV, 0.000/DV, 0.000/DV, 0.000/DV,
308 0.000/DV, 0.000/DV, 0.000/DV, 0.000/DV,
309 /* OCT 1 */
310 0.000/DV, 0.000/DV, 0.000/DV, 0.000/DV,
311 0.000/DV, 0.000/DV, 0.000/DV, 0.000/DV,
312 0.000/DV, 0.750/DV, 1.125/DV, 1.500/DV,
313 1.875/DV, 2.250/DV, 2.625/DV, 3.000/DV,
314 /* OCT 2 */
315 0.000/DV, 0.000/DV, 0.000/DV, 0.000/DV,
316 0.000/DV, 1.125/DV, 1.875/DV, 2.625/DV,
317 3.000/DV, 3.750/DV, 4.125/DV, 4.500/DV,
318 4.875/DV, 5.250/DV, 5.625/DV, 6.000/DV,
319 /* OCT 3 */
320 0.000/DV, 0.000/DV, 0.000/DV, 1.875/DV,
321 3.000/DV, 4.125/DV, 4.875/DV, 5.625/DV,
322 6.000/DV, 6.750/DV, 7.125/DV, 7.500/DV,
323 7.875/DV, 8.250/DV, 8.625/DV, 9.000/DV,
324 /* OCT 4 */
325 0.000/DV, 0.000/DV, 3.000/DV, 4.875/DV,
326 6.000/DV, 7.125/DV, 7.875/DV, 8.625/DV,
327 9.000/DV, 9.750/DV,10.125/DV,10.500/DV,
328 10.875/DV,11.250/DV,11.625/DV,12.000/DV,
329 /* OCT 5 */
330 0.000/DV, 3.000/DV, 6.000/DV, 7.875/DV,
331 9.000/DV,10.125/DV,10.875/DV,11.625/DV,
332 12.000/DV,12.750/DV,13.125/DV,13.500/DV,
333 13.875/DV,14.250/DV,14.625/DV,15.000/DV,
334 /* OCT 6 */
335 0.000/DV, 6.000/DV, 9.000/DV,10.875/DV,
336 12.000/DV,13.125/DV,13.875/DV,14.625/DV,
337 15.000/DV,15.750/DV,16.125/DV,16.500/DV,
338 16.875/DV,17.250/DV,17.625/DV,18.000/DV,
339 /* OCT 7 */
340 0.000/DV, 9.000/DV,12.000/DV,13.875/DV,
341 15.000/DV,16.125/DV,16.875/DV,17.625/DV,
342 18.000/DV,18.750/DV,19.125/DV,19.500/DV,
343 19.875/DV,20.250/DV,20.625/DV,21.000/DV
344 };
345 #undef DV
346
347 /* 0 / 3.0 / 1.5 / 6.0 dB/OCT */
348 static const UINT32 ksl_shift[4] = { 31, 1, 2, 0 };
349
350
351 /* sustain level table (3dB per step) */
352 /* 0 - 15: 0, 3, 6, 9,12,15,18,21,24,27,30,33,36,39,42,93 (dB)*/
353 #define SC(db) (UINT32) ( db * (2.0/ENV_STEP) )
354 static const UINT32 sl_tab[16]={
355 SC( 0),SC( 1),SC( 2),SC(3 ),SC(4 ),SC(5 ),SC(6 ),SC( 7),
356 SC( 8),SC( 9),SC(10),SC(11),SC(12),SC(13),SC(14),SC(31)
357 };
358 #undef SC
359
360
361 #define RATE_STEPS (8)
362 static const unsigned char eg_inc[15*RATE_STEPS]={
363 /*cycle:0 1 2 3 4 5 6 7*/
364
365 /* 0 */ 0,1, 0,1, 0,1, 0,1, /* rates 00..12 0 (increment by 0 or 1) */
366 /* 1 */ 0,1, 0,1, 1,1, 0,1, /* rates 00..12 1 */
367 /* 2 */ 0,1, 1,1, 0,1, 1,1, /* rates 00..12 2 */
368 /* 3 */ 0,1, 1,1, 1,1, 1,1, /* rates 00..12 3 */
369
370 /* 4 */ 1,1, 1,1, 1,1, 1,1, /* rate 13 0 (increment by 1) */
371 /* 5 */ 1,1, 1,2, 1,1, 1,2, /* rate 13 1 */
372 /* 6 */ 1,2, 1,2, 1,2, 1,2, /* rate 13 2 */
373 /* 7 */ 1,2, 2,2, 1,2, 2,2, /* rate 13 3 */
374
375 /* 8 */ 2,2, 2,2, 2,2, 2,2, /* rate 14 0 (increment by 2) */
376 /* 9 */ 2,2, 2,4, 2,2, 2,4, /* rate 14 1 */
377 /*10 */ 2,4, 2,4, 2,4, 2,4, /* rate 14 2 */
378 /*11 */ 2,4, 4,4, 2,4, 4,4, /* rate 14 3 */
379
380 /*12 */ 4,4, 4,4, 4,4, 4,4, /* rates 15 0, 15 1, 15 2, 15 3 for decay */
381 /*13 */ 8,8, 8,8, 8,8, 8,8, /* rates 15 0, 15 1, 15 2, 15 3 for attack (zero time) */
382 /*14 */ 0,0, 0,0, 0,0, 0,0, /* infinity rates for attack and decay(s) */
383 };
384
385
386 #define O(a) (a*RATE_STEPS)
387
388 /* note that there is no O(13) in this table - it's directly in the code */
389 static const unsigned char eg_rate_select[16+64+16]={ /* Envelope Generator rates (16 + 64 rates + 16 RKS) */
390 /* 16 infinite time rates */
391 O(14),O(14),O(14),O(14),O(14),O(14),O(14),O(14),
392 O(14),O(14),O(14),O(14),O(14),O(14),O(14),O(14),
393
394 /* rates 00-12 */
395 O( 0),O( 1),O( 2),O( 3),
396 O( 0),O( 1),O( 2),O( 3),
397 O( 0),O( 1),O( 2),O( 3),
398 O( 0),O( 1),O( 2),O( 3),
399 O( 0),O( 1),O( 2),O( 3),
400 O( 0),O( 1),O( 2),O( 3),
401 O( 0),O( 1),O( 2),O( 3),
402 O( 0),O( 1),O( 2),O( 3),
403 O( 0),O( 1),O( 2),O( 3),
404 O( 0),O( 1),O( 2),O( 3),
405 O( 0),O( 1),O( 2),O( 3),
406 O( 0),O( 1),O( 2),O( 3),
407 O( 0),O( 1),O( 2),O( 3),
408
409 /* rate 13 */
410 O( 4),O( 5),O( 6),O( 7),
411
412 /* rate 14 */
413 O( 8),O( 9),O(10),O(11),
414
415 /* rate 15 */
416 O(12),O(12),O(12),O(12),
417
418 /* 16 dummy rates (same as 15 3) */
419 O(12),O(12),O(12),O(12),O(12),O(12),O(12),O(12),
420 O(12),O(12),O(12),O(12),O(12),O(12),O(12),O(12),
421
422 };
423 #undef O
424
425 /*rate 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 */
426 /*shift 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0, 0, 0, 0 */
427 /*mask 4095, 2047, 1023, 511, 255, 127, 63, 31, 15, 7, 3, 1, 0, 0, 0, 0 */
428
429 #define O(a) (a*1)
430 static const unsigned char eg_rate_shift[16+64+16]={ /* Envelope Generator counter shifts (16 + 64 rates + 16 RKS) */
431 /* 16 infinite time rates */
432 O(0),O(0),O(0),O(0),O(0),O(0),O(0),O(0),
433 O(0),O(0),O(0),O(0),O(0),O(0),O(0),O(0),
434
435 /* rates 00-12 */
436 O(12),O(12),O(12),O(12),
437 O(11),O(11),O(11),O(11),
438 O(10),O(10),O(10),O(10),
439 O( 9),O( 9),O( 9),O( 9),
440 O( 8),O( 8),O( 8),O( 8),
441 O( 7),O( 7),O( 7),O( 7),
442 O( 6),O( 6),O( 6),O( 6),
443 O( 5),O( 5),O( 5),O( 5),
444 O( 4),O( 4),O( 4),O( 4),
445 O( 3),O( 3),O( 3),O( 3),
446 O( 2),O( 2),O( 2),O( 2),
447 O( 1),O( 1),O( 1),O( 1),
448 O( 0),O( 0),O( 0),O( 0),
449
450 /* rate 13 */
451 O( 0),O( 0),O( 0),O( 0),
452
453 /* rate 14 */
454 O( 0),O( 0),O( 0),O( 0),
455
456 /* rate 15 */
457 O( 0),O( 0),O( 0),O( 0),
458
459 /* 16 dummy rates (same as 15 3) */
460 O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),
461 O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),
462
463 };
464 #undef O
465
466
467 /* multiple table */
468 #define ML 2
469 static const UINT8 mul_tab[16]= {
470 /* 1/2, 1, 2, 3, 4, 5, 6, 7, 8, 9,10,10,12,12,15,15 */
471 ML/2, 1*ML, 2*ML, 3*ML, 4*ML, 5*ML, 6*ML, 7*ML,
472 8*ML, 9*ML,10*ML,10*ML,12*ML,12*ML,15*ML,15*ML
473 };
474 #undef ML
475
476 /* TL_TAB_LEN is calculated as:
477
478 * (12+1)=13 - sinus amplitude bits (Y axis)
479 * additional 1: to compensate for calculations of negative part of waveform
480 * (if we don't add it then the greatest possible _negative_ value would be -2
481 * and we really need -1 for waveform #7)
482 * 2 - sinus sign bit (Y axis)
483 * TL_RES_LEN - sinus resolution (X axis)
484 */
485 #define TL_TAB_LEN (13*2*TL_RES_LEN)
486 static signed int tl_tab[TL_TAB_LEN];
487
488 #define ENV_QUIET (TL_TAB_LEN>>4)
489
490 /* sin waveform table in 'decibel' scale */
491 /* there are eight waveforms on OPL3 chips */
492 static unsigned int sin_tab[SIN_LEN * 8];
493
494
495 /* LFO Amplitude Modulation table (verified on real YM3812)
496 27 output levels (triangle waveform); 1 level takes one of: 192, 256 or 448 samples
497
498 Length: 210 elements.
499
500 Each of the elements has to be repeated
501 exactly 64 times (on 64 consecutive samples).
502 The whole table takes: 64 * 210 = 13440 samples.
503
504 When AM = 1 data is used directly
505 When AM = 0 data is divided by 4 before being used (losing precision is important)
506 */
507
508 #define LFO_AM_TAB_ELEMENTS 210
509
510 static const UINT8 lfo_am_table[LFO_AM_TAB_ELEMENTS] = {
511 0,0,0,0,0,0,0,
512 1,1,1,1,
513 2,2,2,2,
514 3,3,3,3,
515 4,4,4,4,
516 5,5,5,5,
517 6,6,6,6,
518 7,7,7,7,
519 8,8,8,8,
520 9,9,9,9,
521 10,10,10,10,
522 11,11,11,11,
523 12,12,12,12,
524 13,13,13,13,
525 14,14,14,14,
526 15,15,15,15,
527 16,16,16,16,
528 17,17,17,17,
529 18,18,18,18,
530 19,19,19,19,
531 20,20,20,20,
532 21,21,21,21,
533 22,22,22,22,
534 23,23,23,23,
535 24,24,24,24,
536 25,25,25,25,
537 26,26,26,
538 25,25,25,25,
539 24,24,24,24,
540 23,23,23,23,
541 22,22,22,22,
542 21,21,21,21,
543 20,20,20,20,
544 19,19,19,19,
545 18,18,18,18,
546 17,17,17,17,
547 16,16,16,16,
548 15,15,15,15,
549 14,14,14,14,
550 13,13,13,13,
551 12,12,12,12,
552 11,11,11,11,
553 10,10,10,10,
554 9,9,9,9,
555 8,8,8,8,
556 7,7,7,7,
557 6,6,6,6,
558 5,5,5,5,
559 4,4,4,4,
560 3,3,3,3,
561 2,2,2,2,
562 1,1,1,1
563 };
564
565 /* LFO Phase Modulation table (verified on real YM3812) */
566 static const INT8 lfo_pm_table[8*8*2] = {
567 /* FNUM2/FNUM = 00 0xxxxxxx (0x0000) */
568 0, 0, 0, 0, 0, 0, 0, 0, /*LFO PM depth = 0*/
569 0, 0, 0, 0, 0, 0, 0, 0, /*LFO PM depth = 1*/
570
571 /* FNUM2/FNUM = 00 1xxxxxxx (0x0080) */
572 0, 0, 0, 0, 0, 0, 0, 0, /*LFO PM depth = 0*/
573 1, 0, 0, 0,-1, 0, 0, 0, /*LFO PM depth = 1*/
574
575 /* FNUM2/FNUM = 01 0xxxxxxx (0x0100) */
576 1, 0, 0, 0,-1, 0, 0, 0, /*LFO PM depth = 0*/
577 2, 1, 0,-1,-2,-1, 0, 1, /*LFO PM depth = 1*/
578
579 /* FNUM2/FNUM = 01 1xxxxxxx (0x0180) */
580 1, 0, 0, 0,-1, 0, 0, 0, /*LFO PM depth = 0*/
581 3, 1, 0,-1,-3,-1, 0, 1, /*LFO PM depth = 1*/
582
583 /* FNUM2/FNUM = 10 0xxxxxxx (0x0200) */
584 2, 1, 0,-1,-2,-1, 0, 1, /*LFO PM depth = 0*/
585 4, 2, 0,-2,-4,-2, 0, 2, /*LFO PM depth = 1*/
586
587 /* FNUM2/FNUM = 10 1xxxxxxx (0x0280) */
588 2, 1, 0,-1,-2,-1, 0, 1, /*LFO PM depth = 0*/
589 5, 2, 0,-2,-5,-2, 0, 2, /*LFO PM depth = 1*/
590
591 /* FNUM2/FNUM = 11 0xxxxxxx (0x0300) */
592 3, 1, 0,-1,-3,-1, 0, 1, /*LFO PM depth = 0*/
593 6, 3, 0,-3,-6,-3, 0, 3, /*LFO PM depth = 1*/
594
595 /* FNUM2/FNUM = 11 1xxxxxxx (0x0380) */
596 3, 1, 0,-1,-3,-1, 0, 1, /*LFO PM depth = 0*/
597 7, 3, 0,-3,-7,-3, 0, 3 /*LFO PM depth = 1*/
598 };
599
600
601 /* lock level of common table */
602 static int num_lock = 0;
603
604 /* work table */
605 #define SLOT7_1 (&chip->P_CH[7].SLOT[SLOT1])
606 #define SLOT7_2 (&chip->P_CH[7].SLOT[SLOT2])
607 #define SLOT8_1 (&chip->P_CH[8].SLOT[SLOT1])
608 #define SLOT8_2 (&chip->P_CH[8].SLOT[SLOT2])
609
610
OPL3_SLOT_CONNECT(OPL3 * chip,OPL3_SLOT * slot)611 INLINE void OPL3_SLOT_CONNECT(OPL3 *chip, OPL3_SLOT *slot) {
612 if (slot->conn_enum == CONN_NULL) {
613 slot->connect = NULL;
614 } else if (slot->conn_enum >= CONN_CHAN0 && slot->conn_enum < CONN_PHASEMOD) {
615 slot->connect = &chip->chanout[slot->conn_enum - CONN_CHAN0];
616 } else if (slot->conn_enum == CONN_PHASEMOD) {
617 slot->connect = &chip->phase_modulation;
618 } else if (slot->conn_enum == CONN_PHASEMOD2) {
619 slot->connect = &chip->phase_modulation2;
620 }
621 }
622
limit(int val,int max,int min)623 INLINE int limit( int val, int max, int min ) {
624 if ( val > max )
625 val = max;
626 else if ( val < min )
627 val = min;
628
629 return val;
630 }
631
632
633 /* status set and IRQ handling */
OPL3_STATUS_SET(OPL3 * chip,int flag)634 INLINE void OPL3_STATUS_SET(OPL3 *chip,int flag)
635 {
636 /* set status flag masking out disabled IRQs */
637 chip->status |= (flag & chip->statusmask);
638 if(!(chip->status & 0x80))
639 {
640 if(chip->status & 0x7f)
641 { /* IRQ on */
642 chip->status |= 0x80;
643 /* callback user interrupt handler (IRQ is OFF to ON) */
644 if(chip->IRQHandler) (chip->IRQHandler)(0, 1);
645 }
646 }
647 }
648
649 /* status reset and IRQ handling */
OPL3_STATUS_RESET(OPL3 * chip,int flag)650 INLINE void OPL3_STATUS_RESET(OPL3 *chip,int flag)
651 {
652 /* reset status flag */
653 chip->status &= ~flag;
654 if(chip->status & 0x80)
655 {
656 if (!(chip->status & 0x7f))
657 {
658 chip->status &= 0x7f;
659 /* callback user interrupt handler (IRQ is ON to OFF) */
660 if(chip->IRQHandler) (chip->IRQHandler)(0, 0);
661 }
662 }
663 }
664
665 /* IRQ mask set */
OPL3_STATUSMASK_SET(OPL3 * chip,int flag)666 INLINE void OPL3_STATUSMASK_SET(OPL3 *chip,int flag)
667 {
668 chip->statusmask = flag;
669 /* IRQ handling check */
670 OPL3_STATUS_SET(chip,0);
671 OPL3_STATUS_RESET(chip,0);
672 }
673
674
675 /* advance LFO to next sample */
advance_lfo(OPL3 * chip)676 INLINE void advance_lfo(OPL3 *chip)
677 {
678 UINT8 tmp;
679
680 /* LFO */
681 chip->lfo_am_cnt += chip->lfo_am_inc;
682 if (chip->lfo_am_cnt >= ((UINT32)LFO_AM_TAB_ELEMENTS<<LFO_SH) ) /* lfo_am_table is 210 elements long */
683 chip->lfo_am_cnt -= ((UINT32)LFO_AM_TAB_ELEMENTS<<LFO_SH);
684
685 tmp = lfo_am_table[ chip->lfo_am_cnt >> LFO_SH ];
686
687 if (chip->lfo_am_depth)
688 chip->LFO_AM = tmp;
689 else
690 chip->LFO_AM = tmp>>2;
691
692 chip->lfo_pm_cnt += chip->lfo_pm_inc;
693 chip->LFO_PM = ((chip->lfo_pm_cnt>>LFO_SH) & 7) | chip->lfo_pm_depth_range;
694 }
695
696 /* advance to next sample */
advance(OPL3 * chip)697 INLINE void advance(OPL3 *chip)
698 {
699 OPL3_CH *CH;
700 OPL3_SLOT *op;
701 int i;
702
703 chip->eg_timer += chip->eg_timer_add;
704
705 while (chip->eg_timer >= chip->eg_timer_overflow)
706 {
707 chip->eg_timer -= chip->eg_timer_overflow;
708
709 chip->eg_cnt++;
710
711 for (i=0; i<9*2*2; i++)
712 {
713 CH = &chip->P_CH[i/2];
714 op = &CH->SLOT[i&1];
715 #if 1
716 /* Envelope Generator */
717 switch(op->state)
718 {
719 case EG_ATT: /* attack phase */
720 // if ( !(chip->eg_cnt & ((1<<op->eg_sh_ar)-1) ) )
721 if ( !(chip->eg_cnt & op->eg_m_ar) )
722 {
723 op->volume += (~op->volume *
724 (eg_inc[op->eg_sel_ar + ((chip->eg_cnt>>op->eg_sh_ar)&7)])
725 ) >>3;
726
727 if (op->volume <= MIN_ATT_INDEX)
728 {
729 op->volume = MIN_ATT_INDEX;
730 op->state = EG_DEC;
731 }
732
733 }
734 break;
735
736 case EG_DEC: /* decay phase */
737 // if ( !(chip->eg_cnt & ((1<<op->eg_sh_dr)-1) ) )
738 if ( !(chip->eg_cnt & op->eg_m_dr) )
739 {
740 op->volume += eg_inc[op->eg_sel_dr + ((chip->eg_cnt>>op->eg_sh_dr)&7)];
741
742 if ( op->volume >= op->sl )
743 op->state = EG_SUS;
744
745 }
746 break;
747
748 case EG_SUS: /* sustain phase */
749
750 /* this is important behaviour:
751 one can change percusive/non-percussive modes on the fly and
752 the chip will remain in sustain phase - verified on real YM3812 */
753
754 if(op->eg_type) /* non-percussive mode */
755 {
756 /* do nothing */
757 }
758 else /* percussive mode */
759 {
760 /* during sustain phase chip adds Release Rate (in percussive mode) */
761 // if ( !(chip->eg_cnt & ((1<<op->eg_sh_rr)-1) ) )
762 if ( !(chip->eg_cnt & op->eg_m_rr) )
763 {
764 op->volume += eg_inc[op->eg_sel_rr + ((chip->eg_cnt>>op->eg_sh_rr)&7)];
765
766 if ( op->volume >= MAX_ATT_INDEX )
767 op->volume = MAX_ATT_INDEX;
768 }
769 /* else do nothing in sustain phase */
770 }
771 break;
772
773 case EG_REL: /* release phase */
774 // if ( !(chip->eg_cnt & ((1<<op->eg_sh_rr)-1) ) )
775 if ( !(chip->eg_cnt & op->eg_m_rr) )
776 {
777 op->volume += eg_inc[op->eg_sel_rr + ((chip->eg_cnt>>op->eg_sh_rr)&7)];
778
779 if ( op->volume >= MAX_ATT_INDEX )
780 {
781 op->volume = MAX_ATT_INDEX;
782 op->state = EG_OFF;
783 }
784
785 }
786 break;
787
788 default:
789 break;
790 }
791 #endif
792 }
793 }
794
795 for (i=0; i<9*2*2; i++)
796 {
797 CH = &chip->P_CH[i/2];
798 op = &CH->SLOT[i&1];
799
800 /* Phase Generator */
801 if(op->vib)
802 {
803 UINT8 block;
804 unsigned int block_fnum = CH->block_fnum;
805
806 unsigned int fnum_lfo = (block_fnum&0x0380) >> 7;
807
808 signed int lfo_fn_table_index_offset = lfo_pm_table[chip->LFO_PM + 16*fnum_lfo ];
809
810 if (lfo_fn_table_index_offset) /* LFO phase modulation active */
811 {
812 block_fnum += lfo_fn_table_index_offset;
813 block = (block_fnum&0x1c00) >> 10;
814 op->Cnt += (chip->fn_tab[block_fnum&0x03ff] >> (7-block)) * op->mul;
815 }
816 else /* LFO phase modulation = zero */
817 {
818 op->Cnt += op->Incr;
819 }
820 }
821 else /* LFO phase modulation disabled for this operator */
822 {
823 op->Cnt += op->Incr;
824 }
825 }
826
827 /* The Noise Generator of the YM3812 is 23-bit shift register.
828 * Period is equal to 2^23-2 samples.
829 * Register works at sampling frequency of the chip, so output
830 * can change on every sample.
831 *
832 * Output of the register and input to the bit 22 is:
833 * bit0 XOR bit14 XOR bit15 XOR bit22
834 *
835 * Simply use bit 22 as the noise output.
836 */
837
838 chip->noise_p += chip->noise_f;
839 i = chip->noise_p >> FREQ_SH; /* number of events (shifts of the shift register) */
840 chip->noise_p &= FREQ_MASK;
841 while (i)
842 {
843 /*
844 UINT32 j;
845 j = ( (chip->noise_rng) ^ (chip->noise_rng>>14) ^ (chip->noise_rng>>15) ^ (chip->noise_rng>>22) ) & 1;
846 chip->noise_rng = (j<<22) | (chip->noise_rng>>1);
847 */
848
849 /*
850 Instead of doing all the logic operations above, we
851 use a trick here (and use bit 0 as the noise output).
852 The difference is only that the noise bit changes one
853 step ahead. This doesn't matter since we don't know
854 what is real state of the noise_rng after the reset.
855 */
856
857 if (chip->noise_rng & 1) chip->noise_rng ^= 0x800302;
858 chip->noise_rng >>= 1;
859
860 i--;
861 }
862 }
863
864
op_calc(UINT32 phase,unsigned int env,signed int pm,unsigned int wave_tab)865 INLINE signed int op_calc(UINT32 phase, unsigned int env, signed int pm, unsigned int wave_tab)
866 {
867 UINT32 p;
868
869 p = (env<<4) + sin_tab[wave_tab + ((((signed int)((phase & ~FREQ_MASK) + (pm<<16))) >> FREQ_SH ) & SIN_MASK) ];
870
871 if (p >= TL_TAB_LEN)
872 return 0;
873 return tl_tab[p];
874 }
875
op_calc1(UINT32 phase,unsigned int env,signed int pm,unsigned int wave_tab)876 INLINE signed int op_calc1(UINT32 phase, unsigned int env, signed int pm, unsigned int wave_tab)
877 {
878 UINT32 p;
879
880 p = (env<<4) + sin_tab[wave_tab + ((((signed int)((phase & ~FREQ_MASK) + pm))>>FREQ_SH) & SIN_MASK)];
881
882 if (p >= TL_TAB_LEN)
883 return 0;
884 return tl_tab[p];
885 }
886
887
888 #define volume_calc(OP) ((OP)->TLL + ((UINT32)(OP)->volume) + (chip->LFO_AM & (OP)->AMmask))
889
890 /* calculate output of a standard 2 operator channel
891 (or 1st part of a 4-op channel) */
chan_calc(OPL3 * chip,OPL3_CH * CH)892 INLINE void chan_calc( OPL3 *chip, OPL3_CH *CH )
893 {
894 OPL3_SLOT *SLOT;
895 unsigned int env;
896 signed int out;
897
898 chip->phase_modulation = 0;
899 chip->phase_modulation2= 0;
900
901 /* SLOT 1 */
902 SLOT = &CH->SLOT[SLOT1];
903 env = volume_calc(SLOT);
904 out = SLOT->op1_out[0] + SLOT->op1_out[1];
905 SLOT->op1_out[0] = SLOT->op1_out[1];
906 SLOT->op1_out[1] = 0;
907 if( env < ENV_QUIET )
908 {
909 if (!SLOT->FB)
910 out = 0;
911 SLOT->op1_out[1] = op_calc1(SLOT->Cnt, env, (out<<SLOT->FB), SLOT->wavetable );
912 }
913 if (SLOT->connect) {
914 *SLOT->connect += SLOT->op1_out[1];
915 }
916 //logerror("out0=%5i vol0=%4i ", SLOT->op1_out[1], env );
917
918 /* SLOT 2 */
919 SLOT++;
920 env = volume_calc(SLOT);
921 if ((env < ENV_QUIET) && SLOT->connect)
922 *SLOT->connect += op_calc(SLOT->Cnt, env, chip->phase_modulation, SLOT->wavetable);
923
924 //logerror("out1=%5i vol1=%4i\n", op_calc(SLOT->Cnt, env, chip->phase_modulation, SLOT->wavetable), env );
925
926 }
927
928 /* calculate output of a 2nd part of 4-op channel */
chan_calc_ext(OPL3 * chip,OPL3_CH * CH)929 INLINE void chan_calc_ext( OPL3 *chip, OPL3_CH *CH )
930 {
931 OPL3_SLOT *SLOT;
932 unsigned int env;
933
934 chip->phase_modulation = 0;
935
936 /* SLOT 1 */
937 SLOT = &CH->SLOT[SLOT1];
938 env = volume_calc(SLOT);
939 if (env < ENV_QUIET && SLOT->connect)
940 *SLOT->connect += op_calc(SLOT->Cnt, env, chip->phase_modulation2, SLOT->wavetable );
941
942 /* SLOT 2 */
943 SLOT++;
944 env = volume_calc(SLOT);
945 if (env < ENV_QUIET && SLOT->connect)
946 *SLOT->connect += op_calc(SLOT->Cnt, env, chip->phase_modulation, SLOT->wavetable);
947
948 }
949
950 /*
951 operators used in the rhythm sounds generation process:
952
953 Envelope Generator:
954
955 channel operator register number Bass High Snare Tom Top
956 / slot number TL ARDR SLRR Wave Drum Hat Drum Tom Cymbal
957 6 / 0 12 50 70 90 f0 +
958 6 / 1 15 53 73 93 f3 +
959 7 / 0 13 51 71 91 f1 +
960 7 / 1 16 54 74 94 f4 +
961 8 / 0 14 52 72 92 f2 +
962 8 / 1 17 55 75 95 f5 +
963
964 Phase Generator:
965
966 channel operator register number Bass High Snare Tom Top
967 / slot number MULTIPLE Drum Hat Drum Tom Cymbal
968 6 / 0 12 30 +
969 6 / 1 15 33 +
970 7 / 0 13 31 + + +
971 7 / 1 16 34 ----- n o t u s e d -----
972 8 / 0 14 32 +
973 8 / 1 17 35 + +
974
975 channel operator register number Bass High Snare Tom Top
976 number number BLK/FNUM2 FNUM Drum Hat Drum Tom Cymbal
977 6 12,15 B6 A6 +
978
979 7 13,16 B7 A7 + + +
980
981 8 14,17 B8 A8 + + +
982
983 */
984
985 /* calculate rhythm */
986
chan_calc_rhythm(OPL3 * chip,OPL3_CH * CH,unsigned int noise)987 INLINE void chan_calc_rhythm( OPL3 *chip, OPL3_CH *CH, unsigned int noise )
988 {
989 OPL3_SLOT *SLOT;
990 signed int *chanout = chip->chanout;
991 signed int out;
992 unsigned int env;
993
994
995 /* Bass Drum (verified on real YM3812):
996 - depends on the channel 6 'connect' register:
997 when connect = 0 it works the same as in normal (non-rhythm) mode (op1->op2->out)
998 when connect = 1 _only_ operator 2 is present on output (op2->out), operator 1 is ignored
999 - output sample always is multiplied by 2
1000 */
1001
1002 chip->phase_modulation = 0;
1003
1004 /* SLOT 1 */
1005 SLOT = &CH[6].SLOT[SLOT1];
1006 env = volume_calc(SLOT);
1007
1008 out = SLOT->op1_out[0] + SLOT->op1_out[1];
1009 SLOT->op1_out[0] = SLOT->op1_out[1];
1010
1011 if (!SLOT->CON)
1012 chip->phase_modulation = SLOT->op1_out[0];
1013 //else ignore output of operator 1
1014
1015 SLOT->op1_out[1] = 0;
1016 if( env < ENV_QUIET )
1017 {
1018 if (!SLOT->FB)
1019 out = 0;
1020 SLOT->op1_out[1] = op_calc1(SLOT->Cnt, env, (out<<SLOT->FB), SLOT->wavetable );
1021 }
1022
1023 /* SLOT 2 */
1024 SLOT++;
1025 env = volume_calc(SLOT);
1026 if( env < ENV_QUIET )
1027 chanout[6] += op_calc(SLOT->Cnt, env, chip->phase_modulation, SLOT->wavetable) * 2;
1028
1029
1030 /* Phase generation is based on: */
1031 // HH (13) channel 7->slot 1 combined with channel 8->slot 2 (same combination as TOP CYMBAL but different output phases)
1032 // SD (16) channel 7->slot 1
1033 // TOM (14) channel 8->slot 1
1034 // TOP (17) channel 7->slot 1 combined with channel 8->slot 2 (same combination as HIGH HAT but different output phases)
1035
1036 /* Envelope generation based on: */
1037 // HH channel 7->slot1
1038 // SD channel 7->slot2
1039 // TOM channel 8->slot1
1040 // TOP channel 8->slot2
1041
1042
1043 /* The following formulas can be well optimized.
1044 I leave them in direct form for now (in case I've missed something).
1045 */
1046
1047 /* High Hat (verified on real YM3812) */
1048 env = volume_calc(SLOT7_1);
1049 if( env < ENV_QUIET )
1050 {
1051 /* high hat phase generation:
1052 phase = d0 or 234 (based on frequency only)
1053 phase = 34 or 2d0 (based on noise)
1054 */
1055
1056 /* base frequency derived from operator 1 in channel 7 */
1057 unsigned char bit7 = ((SLOT7_1->Cnt>>FREQ_SH)>>7)&1;
1058 unsigned char bit3 = ((SLOT7_1->Cnt>>FREQ_SH)>>3)&1;
1059 unsigned char bit2 = ((SLOT7_1->Cnt>>FREQ_SH)>>2)&1;
1060
1061 unsigned char res1 = (bit2 ^ bit7) | bit3;
1062
1063 /* when res1 = 0 phase = 0x000 | 0xd0; */
1064 /* when res1 = 1 phase = 0x200 | (0xd0>>2); */
1065 UINT32 phase = res1 ? (0x200|(0xd0>>2)) : 0xd0;
1066
1067 /* enable gate based on frequency of operator 2 in channel 8 */
1068 unsigned char bit5e= ((SLOT8_2->Cnt>>FREQ_SH)>>5)&1;
1069 unsigned char bit3e= ((SLOT8_2->Cnt>>FREQ_SH)>>3)&1;
1070
1071 unsigned char res2 = (bit3e ^ bit5e);
1072
1073 /* when res2 = 0 pass the phase from calculation above (res1); */
1074 /* when res2 = 1 phase = 0x200 | (0xd0>>2); */
1075 if (res2)
1076 phase = (0x200|(0xd0>>2));
1077
1078
1079 /* when phase & 0x200 is set and noise=1 then phase = 0x200|0xd0 */
1080 /* when phase & 0x200 is set and noise=0 then phase = 0x200|(0xd0>>2), ie no change */
1081 if (phase&0x200)
1082 {
1083 if (noise)
1084 phase = 0x200|0xd0;
1085 }
1086 else
1087 /* when phase & 0x200 is clear and noise=1 then phase = 0xd0>>2 */
1088 /* when phase & 0x200 is clear and noise=0 then phase = 0xd0, ie no change */
1089 {
1090 if (noise)
1091 phase = 0xd0>>2;
1092 }
1093
1094 chanout[7] += op_calc(phase<<FREQ_SH, env, 0, SLOT7_1->wavetable) * 2;
1095 }
1096
1097 /* Snare Drum (verified on real YM3812) */
1098 env = volume_calc(SLOT7_2);
1099 if( env < ENV_QUIET )
1100 {
1101 /* base frequency derived from operator 1 in channel 7 */
1102 unsigned char bit8 = ((SLOT7_1->Cnt>>FREQ_SH)>>8)&1;
1103
1104 /* when bit8 = 0 phase = 0x100; */
1105 /* when bit8 = 1 phase = 0x200; */
1106 UINT32 phase = bit8 ? 0x200 : 0x100;
1107
1108 /* Noise bit XOR'es phase by 0x100 */
1109 /* when noisebit = 0 pass the phase from calculation above */
1110 /* when noisebit = 1 phase ^= 0x100; */
1111 /* in other words: phase ^= (noisebit<<8); */
1112 if (noise)
1113 phase ^= 0x100;
1114
1115 chanout[7] += op_calc(phase<<FREQ_SH, env, 0, SLOT7_2->wavetable) * 2;
1116 }
1117
1118 /* Tom Tom (verified on real YM3812) */
1119 env = volume_calc(SLOT8_1);
1120 if( env < ENV_QUIET )
1121 chanout[8] += op_calc(SLOT8_1->Cnt, env, 0, SLOT8_1->wavetable) * 2;
1122
1123 /* Top Cymbal (verified on real YM3812) */
1124 env = volume_calc(SLOT8_2);
1125 if( env < ENV_QUIET )
1126 {
1127 /* base frequency derived from operator 1 in channel 7 */
1128 unsigned char bit7 = ((SLOT7_1->Cnt>>FREQ_SH)>>7)&1;
1129 unsigned char bit3 = ((SLOT7_1->Cnt>>FREQ_SH)>>3)&1;
1130 unsigned char bit2 = ((SLOT7_1->Cnt>>FREQ_SH)>>2)&1;
1131
1132 unsigned char res1 = (bit2 ^ bit7) | bit3;
1133
1134 /* when res1 = 0 phase = 0x000 | 0x100; */
1135 /* when res1 = 1 phase = 0x200 | 0x100; */
1136 UINT32 phase = res1 ? 0x300 : 0x100;
1137
1138 /* enable gate based on frequency of operator 2 in channel 8 */
1139 unsigned char bit5e= ((SLOT8_2->Cnt>>FREQ_SH)>>5)&1;
1140 unsigned char bit3e= ((SLOT8_2->Cnt>>FREQ_SH)>>3)&1;
1141
1142 unsigned char res2 = (bit3e ^ bit5e);
1143 /* when res2 = 0 pass the phase from calculation above (res1); */
1144 /* when res2 = 1 phase = 0x200 | 0x100; */
1145 if (res2)
1146 phase = 0x300;
1147
1148 chanout[8] += op_calc(phase<<FREQ_SH, env, 0, SLOT8_2->wavetable) * 2;
1149 }
1150
1151 }
1152
1153
1154 /* generic table initialize */
init_tables(void)1155 static int init_tables(void)
1156 {
1157 signed int i,x;
1158 signed int n;
1159 double o,m;
1160
1161
1162 for (x=0; x<TL_RES_LEN; x++)
1163 {
1164 m = (1<<16) / pow(2, (x+1) * (ENV_STEP/4.0) / 8.0);
1165 m = floor(m);
1166
1167 /* we never reach (1<<16) here due to the (x+1) */
1168 /* result fits within 16 bits at maximum */
1169
1170 n = (int)m; /* 16 bits here */
1171 n >>= 4; /* 12 bits here */
1172 if (n&1) /* round to nearest */
1173 n = (n>>1)+1;
1174 else
1175 n = n>>1;
1176 /* 11 bits here (rounded) */
1177 n <<= 1; /* 12 bits here (as in real chip) */
1178 tl_tab[ x*2 + 0 ] = n;
1179 tl_tab[ x*2 + 1 ] = ~tl_tab[ x*2 + 0 ]; /* this *is* different from OPL2 (verified on real YMF262) */
1180
1181 for (i=1; i<13; i++)
1182 {
1183 tl_tab[ x*2+0 + i*2*TL_RES_LEN ] = tl_tab[ x*2+0 ]>>i;
1184 tl_tab[ x*2+1 + i*2*TL_RES_LEN ] = ~tl_tab[ x*2+0 + i*2*TL_RES_LEN ]; /* this *is* different from OPL2 (verified on real YMF262) */
1185 }
1186 #if 0
1187 logerror("tl %04i", x*2);
1188 for (i=0; i<13; i++)
1189 logerror(", [%02i] %5i", i*2, tl_tab[ x*2 +0 + i*2*TL_RES_LEN ] ); /* positive */
1190 logerror("\n");
1191
1192 logerror("tl %04i", x*2);
1193 for (i=0; i<13; i++)
1194 logerror(", [%02i] %5i", i*2, tl_tab[ x*2 +1 + i*2*TL_RES_LEN ] ); /* negative */
1195 logerror("\n");
1196 #endif
1197 }
1198
1199 for (i=0; i<SIN_LEN; i++)
1200 {
1201 /* non-standard sinus */
1202 m = sin( ((i*2)+1) * M_PI / SIN_LEN ); /* checked against the real chip */
1203
1204 /* we never reach zero here due to ((i*2)+1) */
1205
1206 if (m>0.0)
1207 o = 8*log(1.0/m)/log(2.0); /* convert to 'decibels' */
1208 else
1209 o = 8*log(-1.0/m)/log(2.0); /* convert to 'decibels' */
1210
1211 o = o / (ENV_STEP/4);
1212
1213 n = (int)(2.0*o);
1214 if (n&1) /* round to nearest */
1215 n = (n>>1)+1;
1216 else
1217 n = n>>1;
1218
1219 sin_tab[ i ] = n*2 + (m>=0.0? 0: 1 );
1220
1221 /*logerror("YMF262.C: sin [%4i (hex=%03x)]= %4i (tl_tab value=%5i)\n", i, i, sin_tab[i], tl_tab[sin_tab[i]] );*/
1222 }
1223
1224 for (i=0; i<SIN_LEN; i++)
1225 {
1226 /* these 'pictures' represent _two_ cycles */
1227 /* waveform 1: __ __ */
1228 /* / \____/ \____*/
1229 /* output only first half of the sinus waveform (positive one) */
1230
1231 if (i & (1<<(SIN_BITS-1)) )
1232 sin_tab[1*SIN_LEN+i] = TL_TAB_LEN;
1233 else
1234 sin_tab[1*SIN_LEN+i] = sin_tab[i];
1235
1236 /* waveform 2: __ __ __ __ */
1237 /* / \/ \/ \/ \*/
1238 /* abs(sin) */
1239
1240 sin_tab[2*SIN_LEN+i] = sin_tab[i & (SIN_MASK>>1) ];
1241
1242 /* waveform 3: _ _ _ _ */
1243 /* / |_/ |_/ |_/ |_*/
1244 /* abs(output only first quarter of the sinus waveform) */
1245
1246 if (i & (1<<(SIN_BITS-2)) )
1247 sin_tab[3*SIN_LEN+i] = TL_TAB_LEN;
1248 else
1249 sin_tab[3*SIN_LEN+i] = sin_tab[i & (SIN_MASK>>2)];
1250
1251 /* waveform 4: */
1252 /* /\ ____/\ ____*/
1253 /* \/ \/ */
1254 /* output whole sinus waveform in half the cycle(step=2) and output 0 on the other half of cycle */
1255
1256 if (i & (1<<(SIN_BITS-1)) )
1257 sin_tab[4*SIN_LEN+i] = TL_TAB_LEN;
1258 else
1259 sin_tab[4*SIN_LEN+i] = sin_tab[i*2];
1260
1261 /* waveform 5: */
1262 /* /\/\____/\/\____*/
1263 /* */
1264 /* output abs(whole sinus) waveform in half the cycle(step=2) and output 0 on the other half of cycle */
1265
1266 if (i & (1<<(SIN_BITS-1)) )
1267 sin_tab[5*SIN_LEN+i] = TL_TAB_LEN;
1268 else
1269 sin_tab[5*SIN_LEN+i] = sin_tab[(i*2) & (SIN_MASK>>1) ];
1270
1271 /* waveform 6: ____ ____ */
1272 /* */
1273 /* ____ ____*/
1274 /* output maximum in half the cycle and output minimum on the other half of cycle */
1275
1276 if (i & (1<<(SIN_BITS-1)) )
1277 sin_tab[6*SIN_LEN+i] = 1; /* negative */
1278 else
1279 sin_tab[6*SIN_LEN+i] = 0; /* positive */
1280
1281 /* waveform 7: */
1282 /* |\____ |\____ */
1283 /* \| \|*/
1284 /* output sawtooth waveform */
1285
1286 if (i & (1<<(SIN_BITS-1)) )
1287 x = ((SIN_LEN-1)-i)*16 + 1; /* negative: from 8177 to 1 */
1288 else
1289 x = i*16; /*positive: from 0 to 8176 */
1290
1291 if (x > TL_TAB_LEN)
1292 x = TL_TAB_LEN; /* clip to the allowed range */
1293
1294 sin_tab[7*SIN_LEN+i] = x;
1295
1296 //logerror("YMF262.C: sin1[%4i]= %4i (tl_tab value=%5i)\n", i, sin_tab[1*SIN_LEN+i], tl_tab[sin_tab[1*SIN_LEN+i]] );
1297 //logerror("YMF262.C: sin2[%4i]= %4i (tl_tab value=%5i)\n", i, sin_tab[2*SIN_LEN+i], tl_tab[sin_tab[2*SIN_LEN+i]] );
1298 //logerror("YMF262.C: sin3[%4i]= %4i (tl_tab value=%5i)\n", i, sin_tab[3*SIN_LEN+i], tl_tab[sin_tab[3*SIN_LEN+i]] );
1299 //logerror("YMF262.C: sin4[%4i]= %4i (tl_tab value=%5i)\n", i, sin_tab[4*SIN_LEN+i], tl_tab[sin_tab[4*SIN_LEN+i]] );
1300 //logerror("YMF262.C: sin5[%4i]= %4i (tl_tab value=%5i)\n", i, sin_tab[5*SIN_LEN+i], tl_tab[sin_tab[5*SIN_LEN+i]] );
1301 //logerror("YMF262.C: sin6[%4i]= %4i (tl_tab value=%5i)\n", i, sin_tab[6*SIN_LEN+i], tl_tab[sin_tab[6*SIN_LEN+i]] );
1302 //logerror("YMF262.C: sin7[%4i]= %4i (tl_tab value=%5i)\n", i, sin_tab[7*SIN_LEN+i], tl_tab[sin_tab[7*SIN_LEN+i]] );
1303 }
1304 /*logerror("YMF262.C: ENV_QUIET= %08x (dec*8=%i)\n", ENV_QUIET, ENV_QUIET*8 );*/
1305
1306 #ifdef SAVE_SAMPLE
1307 sample[0]=fopen("sampsum.pcm","wb");
1308 #endif
1309
1310 return 1;
1311 }
1312
OPLCloseTable(void)1313 static void OPLCloseTable( void )
1314 {
1315 #ifdef SAVE_SAMPLE
1316 fclose(sample[0]);
1317 #endif
1318 }
1319
1320
1321
OPL3_initalize(OPL3 * chip)1322 static void OPL3_initalize(OPL3 *chip)
1323 {
1324 int i;
1325
1326 /* frequency base */
1327 chip->freqbase = (chip->rate) ? ((double)chip->clock / (8.0*36)) / chip->rate : 0;
1328 #if 0
1329 chip->rate = (double)chip->clock / (8.0*36);
1330 chip->freqbase = 1.0;
1331 #endif
1332
1333 /* logerror("YMF262: freqbase=%f\n", chip->freqbase); */
1334
1335 /* Timer base time */
1336 chip->TimerBase = 1.0 / ((double)chip->clock / (8.0*36) );
1337
1338 /* make fnumber -> increment counter table */
1339 for( i=0 ; i < 1024 ; i++ )
1340 {
1341 /* opn phase increment counter = 20bit */
1342 chip->fn_tab[i] = (UINT32)( (double)i * 64 * chip->freqbase * (1<<(FREQ_SH-10)) ); /* -10 because chip works with 10.10 fixed point, while we use 16.16 */
1343 #if 0
1344 logerror("YMF262.C: fn_tab[%4i] = %08x (dec=%8i)\n",
1345 i, chip->fn_tab[i]>>6, chip->fn_tab[i]>>6 );
1346 #endif
1347 }
1348
1349 #if 0
1350 for( i=0 ; i < 16 ; i++ )
1351 {
1352 logerror("YMF262.C: sl_tab[%i] = %08x\n",
1353 i, sl_tab[i] );
1354 }
1355 for( i=0 ; i < 8 ; i++ )
1356 {
1357 int j;
1358 logerror("YMF262.C: ksl_tab[oct=%2i] =",i);
1359 for (j=0; j<16; j++)
1360 {
1361 logerror("%08x ", ksl_tab[i*16+j] );
1362 }
1363 logerror("\n");
1364 }
1365 #endif
1366
1367
1368 /* Amplitude modulation: 27 output levels (triangle waveform); 1 level takes one of: 192, 256 or 448 samples */
1369 /* One entry from LFO_AM_TABLE lasts for 64 samples */
1370 chip->lfo_am_inc = (1.0 / 64.0 ) * (1<<LFO_SH) * chip->freqbase;
1371
1372 /* Vibrato: 8 output levels (triangle waveform); 1 level takes 1024 samples */
1373 chip->lfo_pm_inc = (1.0 / 1024.0) * (1<<LFO_SH) * chip->freqbase;
1374
1375 /*logerror ("chip->lfo_am_inc = %8x ; chip->lfo_pm_inc = %8x\n", chip->lfo_am_inc, chip->lfo_pm_inc);*/
1376
1377 /* Noise generator: a step takes 1 sample */
1378 chip->noise_f = (1.0 / 1.0) * (1<<FREQ_SH) * chip->freqbase;
1379
1380 chip->eg_timer_add = (1<<EG_SH) * chip->freqbase;
1381 chip->eg_timer_overflow = ( 1 ) * (1<<EG_SH);
1382 /*logerror("YMF262init eg_timer_add=%8x eg_timer_overflow=%8x\n", chip->eg_timer_add, chip->eg_timer_overflow);*/
1383
1384 }
1385
FM_KEYON(OPL3_SLOT * SLOT,UINT32 key_set)1386 INLINE void FM_KEYON(OPL3_SLOT *SLOT, UINT32 key_set)
1387 {
1388 if( !SLOT->key )
1389 {
1390 /* restart Phase Generator */
1391 SLOT->Cnt = 0;
1392 /* phase -> Attack */
1393 SLOT->state = EG_ATT;
1394 }
1395 SLOT->key |= key_set;
1396 }
1397
FM_KEYOFF(OPL3_SLOT * SLOT,UINT32 key_clr)1398 INLINE void FM_KEYOFF(OPL3_SLOT *SLOT, UINT32 key_clr)
1399 {
1400 if( SLOT->key )
1401 {
1402 SLOT->key &= key_clr;
1403
1404 if( !SLOT->key )
1405 {
1406 /* phase -> Release */
1407 if (SLOT->state>EG_REL)
1408 SLOT->state = EG_REL;
1409 }
1410 }
1411 }
1412
1413 /* update phase increment counter of operator (also update the EG rates if necessary) */
CALC_FCSLOT(OPL3_CH * CH,OPL3_SLOT * SLOT)1414 INLINE void CALC_FCSLOT(OPL3_CH *CH,OPL3_SLOT *SLOT)
1415 {
1416 int ksr;
1417
1418 /* (frequency) phase increment counter */
1419 SLOT->Incr = CH->fc * SLOT->mul;
1420 ksr = CH->kcode >> SLOT->KSR;
1421
1422 if( SLOT->ksr != ksr )
1423 {
1424 SLOT->ksr = ksr;
1425
1426 /* calculate envelope generator rates */
1427 if ((SLOT->ar + SLOT->ksr) < 16+60)
1428 {
1429 SLOT->eg_sh_ar = eg_rate_shift [SLOT->ar + SLOT->ksr ];
1430 SLOT->eg_m_ar = (1<<SLOT->eg_sh_ar)-1;
1431 SLOT->eg_sel_ar = eg_rate_select[SLOT->ar + SLOT->ksr ];
1432 }
1433 else
1434 {
1435 SLOT->eg_sh_ar = 0;
1436 SLOT->eg_m_ar = (1<<SLOT->eg_sh_ar)-1;
1437 SLOT->eg_sel_ar = 13*RATE_STEPS;
1438 }
1439 SLOT->eg_sh_dr = eg_rate_shift [SLOT->dr + SLOT->ksr ];
1440 SLOT->eg_m_dr = (1<<SLOT->eg_sh_dr)-1;
1441 SLOT->eg_sel_dr = eg_rate_select[SLOT->dr + SLOT->ksr ];
1442 SLOT->eg_sh_rr = eg_rate_shift [SLOT->rr + SLOT->ksr ];
1443 SLOT->eg_m_rr = (1<<SLOT->eg_sh_rr)-1;
1444 SLOT->eg_sel_rr = eg_rate_select[SLOT->rr + SLOT->ksr ];
1445 }
1446 }
1447
1448 /* set multi,am,vib,EG-TYP,KSR,mul */
set_mul(OPL3 * chip,int slot,int v)1449 INLINE void set_mul(OPL3 *chip,int slot,int v)
1450 {
1451 OPL3_CH *CH = &chip->P_CH[slot/2];
1452 OPL3_SLOT *SLOT = &CH->SLOT[slot&1];
1453
1454 SLOT->mul = mul_tab[v&0x0f];
1455 SLOT->KSR = (v&0x10) ? 0 : 2;
1456 SLOT->eg_type = (v&0x20);
1457 SLOT->vib = (v&0x40);
1458 SLOT->AMmask = (v&0x80) ? ~0 : 0;
1459
1460 if (chip->OPL3_mode & 1)
1461 {
1462 int chan_no = slot/2;
1463
1464 /* in OPL3 mode */
1465 //DO THIS:
1466 //if this is one of the slots of 1st channel forming up a 4-op channel
1467 //do normal operation
1468 //else normal 2 operator function
1469 //OR THIS:
1470 //if this is one of the slots of 2nd channel forming up a 4-op channel
1471 //update it using channel data of 1st channel of a pair
1472 //else normal 2 operator function
1473 switch(chan_no)
1474 {
1475 case 0: case 1: case 2:
1476 case 9: case 10: case 11:
1477 if (CH->extended)
1478 {
1479 /* normal */
1480 CALC_FCSLOT(CH,SLOT);
1481 }
1482 else
1483 {
1484 /* normal */
1485 CALC_FCSLOT(CH,SLOT);
1486 }
1487 break;
1488 case 3: case 4: case 5:
1489 case 12: case 13: case 14:
1490 if ((CH-3)->extended)
1491 {
1492 /* update this SLOT using frequency data for 1st channel of a pair */
1493 CALC_FCSLOT(CH-3,SLOT);
1494 }
1495 else
1496 {
1497 /* normal */
1498 CALC_FCSLOT(CH,SLOT);
1499 }
1500 break;
1501 default:
1502 /* normal */
1503 CALC_FCSLOT(CH,SLOT);
1504 break;
1505 }
1506 }
1507 else
1508 {
1509 /* in OPL2 mode */
1510 CALC_FCSLOT(CH,SLOT);
1511 }
1512 }
1513
1514 /* set ksl & tl */
set_ksl_tl(OPL3 * chip,int slot,int v)1515 INLINE void set_ksl_tl(OPL3 *chip,int slot,int v)
1516 {
1517 OPL3_CH *CH = &chip->P_CH[slot/2];
1518 OPL3_SLOT *SLOT = &CH->SLOT[slot&1];
1519
1520 SLOT->ksl = ksl_shift[v >> 6];
1521 SLOT->TL = (v&0x3f)<<(ENV_BITS-1-7); /* 7 bits TL (bit 6 = always 0) */
1522
1523 if (chip->OPL3_mode & 1)
1524 {
1525 int chan_no = slot/2;
1526
1527 /* in OPL3 mode */
1528 //DO THIS:
1529 //if this is one of the slots of 1st channel forming up a 4-op channel
1530 //do normal operation
1531 //else normal 2 operator function
1532 //OR THIS:
1533 //if this is one of the slots of 2nd channel forming up a 4-op channel
1534 //update it using channel data of 1st channel of a pair
1535 //else normal 2 operator function
1536 switch(chan_no)
1537 {
1538 case 0: case 1: case 2:
1539 case 9: case 10: case 11:
1540 if (CH->extended)
1541 {
1542 /* normal */
1543 SLOT->TLL = SLOT->TL + (CH->ksl_base>>SLOT->ksl);
1544 }
1545 else
1546 {
1547 /* normal */
1548 SLOT->TLL = SLOT->TL + (CH->ksl_base>>SLOT->ksl);
1549 }
1550 break;
1551 case 3: case 4: case 5:
1552 case 12: case 13: case 14:
1553 if ((CH-3)->extended)
1554 {
1555 /* update this SLOT using frequency data for 1st channel of a pair */
1556 SLOT->TLL = SLOT->TL + ((CH-3)->ksl_base>>SLOT->ksl);
1557 }
1558 else
1559 {
1560 /* normal */
1561 SLOT->TLL = SLOT->TL + (CH->ksl_base>>SLOT->ksl);
1562 }
1563 break;
1564 default:
1565 /* normal */
1566 SLOT->TLL = SLOT->TL + (CH->ksl_base>>SLOT->ksl);
1567 break;
1568 }
1569 }
1570 else
1571 {
1572 /* in OPL2 mode */
1573 SLOT->TLL = SLOT->TL + (CH->ksl_base>>SLOT->ksl);
1574 }
1575
1576 }
1577
1578 /* set attack rate & decay rate */
set_ar_dr(OPL3 * chip,int slot,int v)1579 INLINE void set_ar_dr(OPL3 *chip,int slot,int v)
1580 {
1581 OPL3_CH *CH = &chip->P_CH[slot/2];
1582 OPL3_SLOT *SLOT = &CH->SLOT[slot&1];
1583
1584 SLOT->ar = (v>>4) ? 16 + ((v>>4) <<2) : 0;
1585
1586 if ((SLOT->ar + SLOT->ksr) < 16+60) /* verified on real YMF262 - all 15 x rates take "zero" time */
1587 {
1588 SLOT->eg_sh_ar = eg_rate_shift [SLOT->ar + SLOT->ksr ];
1589 SLOT->eg_m_ar = (1<<SLOT->eg_sh_ar)-1;
1590 SLOT->eg_sel_ar = eg_rate_select[SLOT->ar + SLOT->ksr ];
1591 }
1592 else
1593 {
1594 SLOT->eg_sh_ar = 0;
1595 SLOT->eg_m_ar = (1<<SLOT->eg_sh_ar)-1;
1596 SLOT->eg_sel_ar = 13*RATE_STEPS;
1597 }
1598
1599 SLOT->dr = (v&0x0f)? 16 + ((v&0x0f)<<2) : 0;
1600 SLOT->eg_sh_dr = eg_rate_shift [SLOT->dr + SLOT->ksr ];
1601 SLOT->eg_m_dr = (1<<SLOT->eg_sh_dr)-1;
1602 SLOT->eg_sel_dr = eg_rate_select[SLOT->dr + SLOT->ksr ];
1603 }
1604
1605 /* set sustain level & release rate */
set_sl_rr(OPL3 * chip,int slot,int v)1606 INLINE void set_sl_rr(OPL3 *chip,int slot,int v)
1607 {
1608 OPL3_CH *CH = &chip->P_CH[slot/2];
1609 OPL3_SLOT *SLOT = &CH->SLOT[slot&1];
1610
1611 SLOT->sl = sl_tab[ v>>4 ];
1612
1613 SLOT->rr = (v&0x0f)? 16 + ((v&0x0f)<<2) : 0;
1614 SLOT->eg_sh_rr = eg_rate_shift [SLOT->rr + SLOT->ksr ];
1615 SLOT->eg_m_rr = (1<<SLOT->eg_sh_rr)-1;
1616 SLOT->eg_sel_rr = eg_rate_select[SLOT->rr + SLOT->ksr ];
1617 }
1618
1619
update_channels(OPL3 * chip,OPL3_CH * CH)1620 static void update_channels(OPL3 *chip, OPL3_CH *CH)
1621 {
1622 /* update channel passed as a parameter and a channel at CH+=3; */
1623 if (CH->extended)
1624 { /* we've just switched to combined 4 operator mode */
1625
1626 }
1627 else
1628 { /* we've just switched to normal 2 operator mode */
1629
1630 }
1631
1632 }
1633
1634 /* write a value v to register r on OPL chip */
OPL3WriteReg(OPL3 * chip,int r,int v)1635 static void OPL3WriteReg(OPL3 *chip, int r, int v)
1636 {
1637 OPL3_CH *CH;
1638 unsigned int ch_offset = 0;
1639 int slot;
1640 int block_fnum;
1641
1642 if(r&0x100)
1643 {
1644 switch(r)
1645 {
1646 case 0x101: /* test register */
1647 return;
1648
1649 case 0x104: /* 6 channels enable */
1650 {
1651 UINT8 prev;
1652
1653 CH = &chip->P_CH[0]; /* channel 0 */
1654 prev = CH->extended;
1655 CH->extended = (v>>0) & 1;
1656 if(prev != CH->extended)
1657 update_channels(chip, CH);
1658 CH++; /* channel 1 */
1659 prev = CH->extended;
1660 CH->extended = (v>>1) & 1;
1661 if(prev != CH->extended)
1662 update_channels(chip, CH);
1663 CH++; /* channel 2 */
1664 prev = CH->extended;
1665 CH->extended = (v>>2) & 1;
1666 if(prev != CH->extended)
1667 update_channels(chip, CH);
1668
1669
1670 CH = &chip->P_CH[9]; /* channel 9 */
1671 prev = CH->extended;
1672 CH->extended = (v>>3) & 1;
1673 if(prev != CH->extended)
1674 update_channels(chip, CH);
1675 CH++; /* channel 10 */
1676 prev = CH->extended;
1677 CH->extended = (v>>4) & 1;
1678 if(prev != CH->extended)
1679 update_channels(chip, CH);
1680 CH++; /* channel 11 */
1681 prev = CH->extended;
1682 CH->extended = (v>>5) & 1;
1683 if(prev != CH->extended)
1684 update_channels(chip, CH);
1685
1686 }
1687 return;
1688
1689 case 0x105: /* OPL3 extensions enable register */
1690
1691 chip->OPL3_mode = v&0x01; /* OPL3 mode when bit0=1 otherwise it is OPL2 mode */
1692
1693 /* following behaviour was tested on real YMF262,
1694 switching OPL3/OPL2 modes on the fly:
1695 - does not change the waveform previously selected (unless when ....)
1696 - does not update CH.A, CH.B, CH.C and CH.D output selectors (registers c0-c8) (unless when ....)
1697 - does not disable channels 9-17 on OPL3->OPL2 switch
1698 - does not switch 4 operator channels back to 2 operator channels
1699 */
1700
1701 return;
1702
1703 default:
1704 if (r < 0x120)
1705 logerror("YMF262: write to unknown register (set#2): %03x value=%02x\n",r,v);
1706 break;
1707 }
1708
1709 ch_offset = 9; /* register page #2 starts from channel 9 (counting from 0) */
1710 }
1711
1712 /* adjust bus to 8 bits */
1713 r &= 0xff;
1714 v &= 0xff;
1715
1716
1717 switch(r&0xe0)
1718 {
1719 case 0x00: /* 00-1f:control */
1720 switch(r&0x1f)
1721 {
1722 case 0x01: /* test register */
1723 break;
1724 case 0x02: /* Timer 1 */
1725 chip->T[0] = (256-v)*4;
1726 break;
1727 case 0x03: /* Timer 2 */
1728 chip->T[1] = (256-v)*16;
1729 break;
1730 case 0x04: /* IRQ clear / mask and Timer enable */
1731 if(v&0x80)
1732 { /* IRQ flags clear */
1733 OPL3_STATUS_RESET(chip,0x60);
1734 }
1735 else
1736 { /* set IRQ mask ,timer enable */
1737 UINT8 st1 = v & 1;
1738 UINT8 st2 = (v>>1) & 1;
1739
1740 /* IRQRST,T1MSK,t2MSK,x,x,x,ST2,ST1 */
1741 OPL3_STATUS_RESET(chip, v & 0x60);
1742 OPL3_STATUSMASK_SET(chip, (~v) & 0x60 );
1743
1744 /* timer 2 */
1745 if(chip->st[1] != st2)
1746 {
1747 double period = st2 ? chip->TimerBase * chip->T[1] : 0.0;
1748 chip->st[1] = st2;
1749 if (chip->timer_handler) (chip->timer_handler)(0, 1,period);
1750 }
1751 /* timer 1 */
1752 if(chip->st[0] != st1)
1753 {
1754 double period = st1 ? chip->TimerBase * chip->T[0] : 0.0;
1755 chip->st[0] = st1;
1756 if (chip->timer_handler) (chip->timer_handler)(0, 0,period);
1757 }
1758 }
1759 break;
1760 case 0x08: /* x,NTS,x,x, x,x,x,x */
1761 chip->nts = v;
1762 break;
1763
1764 default:
1765 logerror("YMF262: write to unknown register: %02x value=%02x\n",r,v);
1766 break;
1767 }
1768 break;
1769 case 0x20: /* am ON, vib ON, ksr, eg_type, mul */
1770 slot = slot_array[r&0x1f];
1771 if(slot < 0) return;
1772 set_mul(chip, slot + ch_offset*2, v);
1773 break;
1774 case 0x40:
1775 slot = slot_array[r&0x1f];
1776 if(slot < 0) return;
1777 set_ksl_tl(chip, slot + ch_offset*2, v);
1778 break;
1779 case 0x60:
1780 slot = slot_array[r&0x1f];
1781 if(slot < 0) return;
1782 set_ar_dr(chip, slot + ch_offset*2, v);
1783 break;
1784 case 0x80:
1785 slot = slot_array[r&0x1f];
1786 if(slot < 0) return;
1787 set_sl_rr(chip, slot + ch_offset*2, v);
1788 break;
1789 case 0xa0:
1790 if (r == 0xbd) /* am depth, vibrato depth, r,bd,sd,tom,tc,hh */
1791 {
1792 if (ch_offset != 0) /* 0xbd register is present in set #1 only */
1793 return;
1794
1795 chip->lfo_am_depth = v & 0x80;
1796 chip->lfo_pm_depth_range = (v&0x40) ? 8 : 0;
1797
1798 chip->rhythm = v&0x3f;
1799
1800 if(chip->rhythm&0x20)
1801 {
1802 /* BD key on/off */
1803 if(v&0x10)
1804 {
1805 FM_KEYON (&chip->P_CH[6].SLOT[SLOT1], 2);
1806 FM_KEYON (&chip->P_CH[6].SLOT[SLOT2], 2);
1807 }
1808 else
1809 {
1810 FM_KEYOFF(&chip->P_CH[6].SLOT[SLOT1],~2);
1811 FM_KEYOFF(&chip->P_CH[6].SLOT[SLOT2],~2);
1812 }
1813 /* HH key on/off */
1814 if(v&0x01) FM_KEYON (&chip->P_CH[7].SLOT[SLOT1], 2);
1815 else FM_KEYOFF(&chip->P_CH[7].SLOT[SLOT1],~2);
1816 /* SD key on/off */
1817 if(v&0x08) FM_KEYON (&chip->P_CH[7].SLOT[SLOT2], 2);
1818 else FM_KEYOFF(&chip->P_CH[7].SLOT[SLOT2],~2);
1819 /* TOM key on/off */
1820 if(v&0x04) FM_KEYON (&chip->P_CH[8].SLOT[SLOT1], 2);
1821 else FM_KEYOFF(&chip->P_CH[8].SLOT[SLOT1],~2);
1822 /* TOP-CY key on/off */
1823 if(v&0x02) FM_KEYON (&chip->P_CH[8].SLOT[SLOT2], 2);
1824 else FM_KEYOFF(&chip->P_CH[8].SLOT[SLOT2],~2);
1825 }
1826 else
1827 {
1828 /* BD key off */
1829 FM_KEYOFF(&chip->P_CH[6].SLOT[SLOT1],~2);
1830 FM_KEYOFF(&chip->P_CH[6].SLOT[SLOT2],~2);
1831 /* HH key off */
1832 FM_KEYOFF(&chip->P_CH[7].SLOT[SLOT1],~2);
1833 /* SD key off */
1834 FM_KEYOFF(&chip->P_CH[7].SLOT[SLOT2],~2);
1835 /* TOM key off */
1836 FM_KEYOFF(&chip->P_CH[8].SLOT[SLOT1],~2);
1837 /* TOP-CY off */
1838 FM_KEYOFF(&chip->P_CH[8].SLOT[SLOT2],~2);
1839 }
1840 return;
1841 }
1842
1843 /* keyon,block,fnum */
1844 if( (r&0x0f) > 8) return;
1845 CH = &chip->P_CH[(r&0x0f) + ch_offset];
1846
1847 if(!(r&0x10))
1848 { /* a0-a8 */
1849 block_fnum = (CH->block_fnum&0x1f00) | v;
1850 }
1851 else
1852 { /* b0-b8 */
1853 block_fnum = ((v&0x1f)<<8) | (CH->block_fnum&0xff);
1854
1855 if (chip->OPL3_mode & 1)
1856 {
1857 int chan_no = (r&0x0f) + ch_offset;
1858
1859 /* in OPL3 mode */
1860 //DO THIS:
1861 //if this is 1st channel forming up a 4-op channel
1862 //ALSO keyon/off slots of 2nd channel forming up 4-op channel
1863 //else normal 2 operator function keyon/off
1864 //OR THIS:
1865 //if this is 2nd channel forming up 4-op channel just do nothing
1866 //else normal 2 operator function keyon/off
1867 switch(chan_no)
1868 {
1869 case 0: case 1: case 2:
1870 case 9: case 10: case 11:
1871 if (CH->extended)
1872 {
1873 //if this is 1st channel forming up a 4-op channel
1874 //ALSO keyon/off slots of 2nd channel forming up 4-op channel
1875 if(v&0x20)
1876 {
1877 FM_KEYON (&CH->SLOT[SLOT1], 1);
1878 FM_KEYON (&CH->SLOT[SLOT2], 1);
1879 FM_KEYON (&(CH+3)->SLOT[SLOT1], 1);
1880 FM_KEYON (&(CH+3)->SLOT[SLOT2], 1);
1881 }
1882 else
1883 {
1884 FM_KEYOFF(&CH->SLOT[SLOT1],~1);
1885 FM_KEYOFF(&CH->SLOT[SLOT2],~1);
1886 FM_KEYOFF(&(CH+3)->SLOT[SLOT1],~1);
1887 FM_KEYOFF(&(CH+3)->SLOT[SLOT2],~1);
1888 }
1889 }
1890 else
1891 {
1892 //else normal 2 operator function keyon/off
1893 if(v&0x20)
1894 {
1895 FM_KEYON (&CH->SLOT[SLOT1], 1);
1896 FM_KEYON (&CH->SLOT[SLOT2], 1);
1897 }
1898 else
1899 {
1900 FM_KEYOFF(&CH->SLOT[SLOT1],~1);
1901 FM_KEYOFF(&CH->SLOT[SLOT2],~1);
1902 }
1903 }
1904 break;
1905
1906 case 3: case 4: case 5:
1907 case 12: case 13: case 14:
1908 if ((CH-3)->extended)
1909 {
1910 //if this is 2nd channel forming up 4-op channel just do nothing
1911 }
1912 else
1913 {
1914 //else normal 2 operator function keyon/off
1915 if(v&0x20)
1916 {
1917 FM_KEYON (&CH->SLOT[SLOT1], 1);
1918 FM_KEYON (&CH->SLOT[SLOT2], 1);
1919 }
1920 else
1921 {
1922 FM_KEYOFF(&CH->SLOT[SLOT1],~1);
1923 FM_KEYOFF(&CH->SLOT[SLOT2],~1);
1924 }
1925 }
1926 break;
1927
1928 default:
1929 if(v&0x20)
1930 {
1931 FM_KEYON (&CH->SLOT[SLOT1], 1);
1932 FM_KEYON (&CH->SLOT[SLOT2], 1);
1933 }
1934 else
1935 {
1936 FM_KEYOFF(&CH->SLOT[SLOT1],~1);
1937 FM_KEYOFF(&CH->SLOT[SLOT2],~1);
1938 }
1939 break;
1940 }
1941 }
1942 else
1943 {
1944 if(v&0x20)
1945 {
1946 FM_KEYON (&CH->SLOT[SLOT1], 1);
1947 FM_KEYON (&CH->SLOT[SLOT2], 1);
1948 }
1949 else
1950 {
1951 FM_KEYOFF(&CH->SLOT[SLOT1],~1);
1952 FM_KEYOFF(&CH->SLOT[SLOT2],~1);
1953 }
1954 }
1955 }
1956 /* update */
1957 if(CH->block_fnum != block_fnum)
1958 {
1959 UINT8 block = block_fnum >> 10;
1960
1961 CH->block_fnum = block_fnum;
1962
1963 CH->ksl_base = (UINT32)(ksl_tab[block_fnum>>6]);
1964 CH->fc = chip->fn_tab[block_fnum&0x03ff] >> (7-block);
1965
1966 /* BLK 2,1,0 bits -> bits 3,2,1 of kcode */
1967 CH->kcode = (CH->block_fnum&0x1c00)>>9;
1968
1969 /* the info below is actually opposite to what is stated in the Manuals (verifed on real YMF262) */
1970 /* if notesel == 0 -> lsb of kcode is bit 10 (MSB) of fnum */
1971 /* if notesel == 1 -> lsb of kcode is bit 9 (MSB-1) of fnum */
1972 if (chip->nts&0x40)
1973 CH->kcode |= (CH->block_fnum&0x100)>>8; /* notesel == 1 */
1974 else
1975 CH->kcode |= (CH->block_fnum&0x200)>>9; /* notesel == 0 */
1976
1977 if (chip->OPL3_mode & 1)
1978 {
1979 int chan_no = (r&0x0f) + ch_offset;
1980 /* in OPL3 mode */
1981 //DO THIS:
1982 //if this is 1st channel forming up a 4-op channel
1983 //ALSO update slots of 2nd channel forming up 4-op channel
1984 //else normal 2 operator function keyon/off
1985 //OR THIS:
1986 //if this is 2nd channel forming up 4-op channel just do nothing
1987 //else normal 2 operator function keyon/off
1988 switch(chan_no)
1989 {
1990 case 0: case 1: case 2:
1991 case 9: case 10: case 11:
1992 if (CH->extended)
1993 {
1994 //if this is 1st channel forming up a 4-op channel
1995 //ALSO update slots of 2nd channel forming up 4-op channel
1996
1997 /* refresh Total Level in FOUR SLOTs of this channel and channel+3 using data from THIS channel */
1998 CH->SLOT[SLOT1].TLL = CH->SLOT[SLOT1].TL + (CH->ksl_base>>CH->SLOT[SLOT1].ksl);
1999 CH->SLOT[SLOT2].TLL = CH->SLOT[SLOT2].TL + (CH->ksl_base>>CH->SLOT[SLOT2].ksl);
2000 (CH+3)->SLOT[SLOT1].TLL = (CH+3)->SLOT[SLOT1].TL + (CH->ksl_base>>(CH+3)->SLOT[SLOT1].ksl);
2001 (CH+3)->SLOT[SLOT2].TLL = (CH+3)->SLOT[SLOT2].TL + (CH->ksl_base>>(CH+3)->SLOT[SLOT2].ksl);
2002
2003 /* refresh frequency counter in FOUR SLOTs of this channel and channel+3 using data from THIS channel */
2004 CALC_FCSLOT(CH,&CH->SLOT[SLOT1]);
2005 CALC_FCSLOT(CH,&CH->SLOT[SLOT2]);
2006 CALC_FCSLOT(CH,&(CH+3)->SLOT[SLOT1]);
2007 CALC_FCSLOT(CH,&(CH+3)->SLOT[SLOT2]);
2008 }
2009 else
2010 {
2011 //else normal 2 operator function
2012 /* refresh Total Level in both SLOTs of this channel */
2013 CH->SLOT[SLOT1].TLL = CH->SLOT[SLOT1].TL + (CH->ksl_base>>CH->SLOT[SLOT1].ksl);
2014 CH->SLOT[SLOT2].TLL = CH->SLOT[SLOT2].TL + (CH->ksl_base>>CH->SLOT[SLOT2].ksl);
2015
2016 /* refresh frequency counter in both SLOTs of this channel */
2017 CALC_FCSLOT(CH,&CH->SLOT[SLOT1]);
2018 CALC_FCSLOT(CH,&CH->SLOT[SLOT2]);
2019 }
2020 break;
2021
2022 case 3: case 4: case 5:
2023 case 12: case 13: case 14:
2024 if ((CH-3)->extended)
2025 {
2026 //if this is 2nd channel forming up 4-op channel just do nothing
2027 }
2028 else
2029 {
2030 //else normal 2 operator function
2031 /* refresh Total Level in both SLOTs of this channel */
2032 CH->SLOT[SLOT1].TLL = CH->SLOT[SLOT1].TL + (CH->ksl_base>>CH->SLOT[SLOT1].ksl);
2033 CH->SLOT[SLOT2].TLL = CH->SLOT[SLOT2].TL + (CH->ksl_base>>CH->SLOT[SLOT2].ksl);
2034
2035 /* refresh frequency counter in both SLOTs of this channel */
2036 CALC_FCSLOT(CH,&CH->SLOT[SLOT1]);
2037 CALC_FCSLOT(CH,&CH->SLOT[SLOT2]);
2038 }
2039 break;
2040
2041 default:
2042 /* refresh Total Level in both SLOTs of this channel */
2043 CH->SLOT[SLOT1].TLL = CH->SLOT[SLOT1].TL + (CH->ksl_base>>CH->SLOT[SLOT1].ksl);
2044 CH->SLOT[SLOT2].TLL = CH->SLOT[SLOT2].TL + (CH->ksl_base>>CH->SLOT[SLOT2].ksl);
2045
2046 /* refresh frequency counter in both SLOTs of this channel */
2047 CALC_FCSLOT(CH,&CH->SLOT[SLOT1]);
2048 CALC_FCSLOT(CH,&CH->SLOT[SLOT2]);
2049 break;
2050 }
2051 }
2052 else
2053 {
2054 /* in OPL2 mode */
2055
2056 /* refresh Total Level in both SLOTs of this channel */
2057 CH->SLOT[SLOT1].TLL = CH->SLOT[SLOT1].TL + (CH->ksl_base>>CH->SLOT[SLOT1].ksl);
2058 CH->SLOT[SLOT2].TLL = CH->SLOT[SLOT2].TL + (CH->ksl_base>>CH->SLOT[SLOT2].ksl);
2059
2060 /* refresh frequency counter in both SLOTs of this channel */
2061 CALC_FCSLOT(CH,&CH->SLOT[SLOT1]);
2062 CALC_FCSLOT(CH,&CH->SLOT[SLOT2]);
2063 }
2064 }
2065 break;
2066
2067 case 0xc0:
2068 /* CH.D, CH.C, CH.B, CH.A, FB(3bits), C */
2069 if( (r&0xf) > 8) return;
2070
2071 CH = &chip->P_CH[(r&0xf) + ch_offset];
2072
2073 if( chip->OPL3_mode & 1 )
2074 {
2075 int base = ((r&0xf) + ch_offset) * 4;
2076
2077 /* OPL3 mode */
2078 chip->pan[ base ] = (v & 0x10) ? ~0 : 0; /* ch.A */
2079 chip->pan[ base +1 ] = (v & 0x20) ? ~0 : 0; /* ch.B */
2080 chip->pan[ base +2 ] = (v & 0x40) ? ~0 : 0; /* ch.C */
2081 chip->pan[ base +3 ] = (v & 0x80) ? ~0 : 0; /* ch.D */
2082 }
2083 else
2084 {
2085 int base = ((r&0xf) + ch_offset) * 4;
2086
2087 /* OPL2 mode - always enabled */
2088 chip->pan[ base ] = ~0; /* ch.A */
2089 chip->pan[ base +1 ] = ~0; /* ch.B */
2090 chip->pan[ base +2 ] = ~0; /* ch.C */
2091 chip->pan[ base +3 ] = ~0; /* ch.D */
2092 }
2093
2094 chip->pan_ctrl_value[ (r&0xf) + ch_offset ] = v; /* store control value for OPL3/OPL2 mode switching on the fly */
2095
2096 CH->SLOT[SLOT1].FB = (v>>1)&7 ? ((v>>1)&7) + 7 : 0;
2097 CH->SLOT[SLOT1].CON = v&1;
2098
2099 if( chip->OPL3_mode & 1 )
2100 {
2101 int chan_no = (r&0x0f) + ch_offset;
2102
2103 switch(chan_no)
2104 {
2105 case 0: case 1: case 2:
2106 case 9: case 10: case 11:
2107 if (CH->extended)
2108 {
2109 UINT8 conn = (CH->SLOT[SLOT1].CON<<1) | ((CH+3)->SLOT[SLOT1].CON<<0);
2110 switch(conn)
2111 {
2112 case 0:
2113 /* 1 -> 2 -> 3 -> 4 - out */
2114
2115 CH->SLOT[SLOT1].conn_enum = CONN_PHASEMOD;
2116 CH->SLOT[SLOT2].conn_enum = CONN_PHASEMOD2;
2117 (CH+3)->SLOT[SLOT1].conn_enum = CONN_PHASEMOD;
2118 (CH+3)->SLOT[SLOT2].conn_enum = CONN_CHAN0 + chan_no + 3;
2119 break;
2120 case 1:
2121 /* 1 -> 2 -\
2122 3 -> 4 -+- out */
2123
2124 CH->SLOT[SLOT1].conn_enum = CONN_PHASEMOD;
2125 CH->SLOT[SLOT2].conn_enum = CONN_CHAN0 + chan_no;
2126 (CH+3)->SLOT[SLOT1].conn_enum = CONN_PHASEMOD;
2127 (CH+3)->SLOT[SLOT2].conn_enum = CONN_CHAN0 + chan_no + 3;
2128 break;
2129 case 2:
2130 /* 1 -----------\
2131 2 -> 3 -> 4 -+- out */
2132
2133 CH->SLOT[SLOT1].conn_enum = CONN_CHAN0 + chan_no;
2134 CH->SLOT[SLOT2].conn_enum = CONN_PHASEMOD2;
2135 (CH+3)->SLOT[SLOT1].conn_enum = CONN_PHASEMOD;
2136 (CH+3)->SLOT[SLOT2].conn_enum = CONN_CHAN0 + chan_no + 3;
2137 break;
2138 case 3:
2139 /* 1 ------\
2140 2 -> 3 -+- out
2141 4 ------/ */
2142 CH->SLOT[SLOT1].conn_enum = CONN_CHAN0 + chan_no;
2143 CH->SLOT[SLOT2].conn_enum = CONN_PHASEMOD2;
2144 (CH+3)->SLOT[SLOT1].conn_enum = CONN_CHAN0 + chan_no + 3;
2145 (CH+3)->SLOT[SLOT2].conn_enum = CONN_CHAN0 + chan_no + 3;
2146 break;
2147 }
2148 OPL3_SLOT_CONNECT(chip, &CH->SLOT[SLOT1]);
2149 OPL3_SLOT_CONNECT(chip, &CH->SLOT[SLOT2]);
2150 OPL3_SLOT_CONNECT(chip, &(CH+3)->SLOT[SLOT1]);
2151 OPL3_SLOT_CONNECT(chip, &(CH+3)->SLOT[SLOT2]);
2152 }
2153 else
2154 {
2155 /* 2 operators mode */
2156 CH->SLOT[SLOT1].conn_enum = CH->SLOT[SLOT1].CON ? CONN_CHAN0 + (r&0xf)+ch_offset : CONN_PHASEMOD;
2157 CH->SLOT[SLOT2].conn_enum = CONN_CHAN0 + (r&0xf)+ch_offset;
2158 OPL3_SLOT_CONNECT(chip, &CH->SLOT[SLOT1]);
2159 OPL3_SLOT_CONNECT(chip, &CH->SLOT[SLOT2]);
2160 }
2161 break;
2162
2163 case 3: case 4: case 5:
2164 case 12: case 13: case 14:
2165 if ((CH-3)->extended)
2166 {
2167 UINT8 conn = ((CH-3)->SLOT[SLOT1].CON<<1) | (CH->SLOT[SLOT1].CON<<0);
2168 switch(conn)
2169 {
2170 case 0:
2171 /* 1 -> 2 -> 3 -> 4 - out */
2172
2173 (CH-3)->SLOT[SLOT1].conn_enum = CONN_PHASEMOD;
2174 (CH-3)->SLOT[SLOT2].conn_enum = CONN_PHASEMOD2;
2175 CH->SLOT[SLOT1].conn_enum = CONN_PHASEMOD;
2176 CH->SLOT[SLOT2].conn_enum = CONN_CHAN0 + chan_no;
2177 break;
2178 case 1:
2179 /* 1 -> 2 -\
2180 3 -> 4 -+- out */
2181
2182 (CH-3)->SLOT[SLOT1].conn_enum = CONN_PHASEMOD;
2183 (CH-3)->SLOT[SLOT2].conn_enum = CONN_CHAN0 + chan_no - 3;
2184 CH->SLOT[SLOT1].conn_enum = CONN_PHASEMOD;
2185 CH->SLOT[SLOT2].conn_enum = CONN_CHAN0 + chan_no;
2186 break;
2187 case 2:
2188 /* 1 -----------\
2189 2 -> 3 -> 4 -+- out */
2190
2191 (CH-3)->SLOT[SLOT1].conn_enum = CONN_CHAN0 + chan_no - 3;
2192 (CH-3)->SLOT[SLOT2].conn_enum = CONN_PHASEMOD2;
2193 CH->SLOT[SLOT1].conn_enum = CONN_PHASEMOD;
2194 CH->SLOT[SLOT2].conn_enum = CONN_CHAN0 + chan_no;
2195 break;
2196 case 3:
2197 /* 1 ------\
2198 2 -> 3 -+- out
2199 4 ------/ */
2200 (CH-3)->SLOT[SLOT1].conn_enum = CONN_CHAN0 + chan_no - 3;
2201 (CH-3)->SLOT[SLOT2].conn_enum = CONN_PHASEMOD2;
2202 CH->SLOT[SLOT1].conn_enum = CONN_CHAN0 + chan_no;
2203 CH->SLOT[SLOT2].conn_enum = CONN_CHAN0 + chan_no;
2204 break;
2205 }
2206 OPL3_SLOT_CONNECT(chip, &(CH-3)->SLOT[SLOT1]);
2207 OPL3_SLOT_CONNECT(chip, &(CH-3)->SLOT[SLOT2]);
2208 OPL3_SLOT_CONNECT(chip, &CH->SLOT[SLOT1]);
2209 OPL3_SLOT_CONNECT(chip, &CH->SLOT[SLOT2]);
2210 }
2211 else
2212 {
2213 /* 2 operators mode */
2214 CH->SLOT[SLOT1].conn_enum = CH->SLOT[SLOT1].CON ? CONN_CHAN0 + (r&0xf)+ch_offset : CONN_PHASEMOD;
2215 CH->SLOT[SLOT2].conn_enum = CONN_CHAN0 + (r&0xf)+ch_offset;
2216 OPL3_SLOT_CONNECT(chip, &CH->SLOT[SLOT1]);
2217 OPL3_SLOT_CONNECT(chip, &CH->SLOT[SLOT2]);
2218 }
2219 break;
2220
2221 default:
2222 /* 2 operators mode */
2223 CH->SLOT[SLOT1].conn_enum = CH->SLOT[SLOT1].CON ? CONN_CHAN0 + (r&0xf)+ch_offset : CONN_PHASEMOD;
2224 CH->SLOT[SLOT2].conn_enum = CONN_CHAN0 + (r&0xf)+ch_offset;
2225 OPL3_SLOT_CONNECT(chip, &CH->SLOT[SLOT1]);
2226 OPL3_SLOT_CONNECT(chip, &CH->SLOT[SLOT2]);
2227 break;
2228 }
2229 }
2230 else
2231 {
2232 /* OPL2 mode - always 2 operators mode */
2233 CH->SLOT[SLOT1].conn_enum = CH->SLOT[SLOT1].CON ? CONN_CHAN0 + (r&0xf)+ch_offset : CONN_PHASEMOD;
2234 CH->SLOT[SLOT2].conn_enum = CONN_CHAN0 + (r&0xf)+ch_offset;
2235 OPL3_SLOT_CONNECT(chip, &CH->SLOT[SLOT1]);
2236 OPL3_SLOT_CONNECT(chip, &CH->SLOT[SLOT2]);
2237 }
2238 break;
2239
2240 case 0xe0: /* waveform select */
2241 slot = slot_array[r&0x1f];
2242 if(slot < 0) return;
2243
2244 slot += ch_offset*2;
2245
2246 CH = &chip->P_CH[slot/2];
2247
2248
2249 /* store 3-bit value written regardless of current OPL2 or OPL3 mode... (verified on real YMF262) */
2250 v &= 7;
2251 CH->SLOT[slot&1].waveform_number = v;
2252
2253 /* ... but select only waveforms 0-3 in OPL2 mode */
2254 if( !(chip->OPL3_mode & 1) )
2255 {
2256 v &= 3; /* we're in OPL2 mode */
2257 }
2258 CH->SLOT[slot&1].wavetable = v * SIN_LEN;
2259 break;
2260 }
2261 }
2262
2263 /* lock/unlock for common table */
OPL3_LockTable()2264 static int OPL3_LockTable()
2265 {
2266 num_lock++;
2267 if(num_lock>1) return 0;
2268
2269 /* first time */
2270
2271 if( !init_tables() )
2272 {
2273 num_lock--;
2274 return -1;
2275 }
2276
2277 return 0;
2278 }
2279
OPL3_UnLockTable(void)2280 static void OPL3_UnLockTable(void)
2281 {
2282 if(num_lock) num_lock--;
2283 if(num_lock) return;
2284
2285 /* last time */
2286 OPLCloseTable();
2287 }
2288
OPL3ResetChip(OPL3 * chip)2289 static void OPL3ResetChip(OPL3 *chip)
2290 {
2291 int c,s;
2292
2293 chip->eg_timer = 0;
2294 chip->eg_cnt = 0;
2295
2296 chip->noise_rng = 1; /* noise shift register */
2297 chip->nts = 0; /* note split */
2298 OPL3_STATUS_RESET(chip,0x60);
2299
2300 /* reset with register write */
2301 OPL3WriteReg(chip,0x01,0); /* test register */
2302 OPL3WriteReg(chip,0x02,0); /* Timer1 */
2303 OPL3WriteReg(chip,0x03,0); /* Timer2 */
2304 OPL3WriteReg(chip,0x04,0); /* IRQ mask clear */
2305
2306
2307 //FIX IT registers 101, 104 and 105
2308
2309
2310 //FIX IT (dont change CH.D, CH.C, CH.B and CH.A in C0-C8 registers)
2311 for(c = 0xff ; c >= 0x20 ; c-- )
2312 OPL3WriteReg(chip,c,0);
2313 //FIX IT (dont change CH.D, CH.C, CH.B and CH.A in C0-C8 registers)
2314 for(c = 0x1ff ; c >= 0x120 ; c-- )
2315 OPL3WriteReg(chip,c,0);
2316
2317
2318
2319 /* reset operator parameters */
2320 for( c = 0 ; c < 9*2 ; c++ )
2321 {
2322 OPL3_CH *CH = &chip->P_CH[c];
2323 for(s = 0 ; s < 2 ; s++ )
2324 {
2325 CH->SLOT[s].state = EG_OFF;
2326 CH->SLOT[s].volume = MAX_ATT_INDEX;
2327 }
2328 }
2329 }
2330
2331 /* Create one of virtual YMF262 */
2332 /* 'clock' is chip clock in Hz */
2333 /* 'rate' is sampling rate */
OPL3Create(int clock,int rate,int type)2334 static OPL3 *OPL3Create(int clock, int rate, int type)
2335 {
2336 OPL3 *chip;
2337
2338 if (OPL3_LockTable() == -1) return NULL;
2339
2340 /* allocate memory block */
2341 chip = (OPL3 *)malloc(sizeof(OPL3));
2342 memset(chip, 0, sizeof(OPL3));
2343
2344 chip->type = type;
2345 chip->clock = clock;
2346 chip->rate = rate;
2347
2348 /* init global tables */
2349 OPL3_initalize(chip);
2350
2351 /* reset chip */
2352 OPL3ResetChip(chip);
2353 return chip;
2354 }
2355
2356 /* Destroy one of virtual YMF262 */
OPL3Destroy(OPL3 * chip)2357 static void OPL3Destroy(OPL3 *chip)
2358 {
2359 OPL3_UnLockTable();
2360
2361 free(chip);
2362 }
2363
2364
2365 /* YMF262 I/O interface */
OPL3Write(OPL3 * chip,int a,int v)2366 static int OPL3Write(OPL3 *chip, int a, int v)
2367 {
2368 /* data bus is 8 bits */
2369 v &= 0xff;
2370
2371 switch(a&3)
2372 {
2373 case 0: /* address port 0 (register set #1) */
2374 chip->address = v;
2375 break;
2376
2377 case 1: /* data port - ignore A1 */
2378 case 3: /* data port - ignore A1 */
2379 if(chip->UpdateHandler) chip->UpdateHandler();
2380 OPL3WriteReg(chip,chip->address,v);
2381 break;
2382
2383 case 2: /* address port 1 (register set #2) */
2384
2385 /* verified on real YMF262:
2386 in OPL3 mode:
2387 address line A1 is stored during *address* write and ignored during *data* write.
2388
2389 in OPL2 mode:
2390 register set#2 writes go to register set#1 (ignoring A1)
2391 verified on registers from set#2: 0x01, 0x04, 0x20-0xef
2392 The only exception is register 0x05.
2393 */
2394 if( chip->OPL3_mode & 1 )
2395 {
2396 /* OPL3 mode */
2397 chip->address = v | 0x100;
2398 }
2399 else
2400 {
2401 /* in OPL2 mode the only accessible in set #2 is register 0x05 */
2402 if( v==5 )
2403 chip->address = v | 0x100;
2404 else
2405 chip->address = v; /* verified range: 0x01, 0x04, 0x20-0xef(set #2 becomes set #1 in opl2 mode) */
2406 }
2407 break;
2408 }
2409
2410 return chip->status>>7;
2411 }
2412
OPL3Read(OPL3 * chip,int a)2413 static unsigned char OPL3Read(OPL3 *chip,int a)
2414 {
2415 if( a==0 )
2416 {
2417 /* status port */
2418 return chip->status;
2419 }
2420
2421 return 0x00; /* verified on real YMF262 */
2422 }
2423
2424
2425
OPL3TimerOver(OPL3 * chip,int c)2426 static int OPL3TimerOver(OPL3 *chip,int c)
2427 {
2428 if( c )
2429 { /* Timer B */
2430 OPL3_STATUS_SET(chip,0x20);
2431 }
2432 else
2433 { /* Timer A */
2434 OPL3_STATUS_SET(chip,0x40);
2435 }
2436 /* reload timer */
2437 if (chip->timer_handler) (chip->timer_handler)(0, c,chip->TimerBase * chip->T[c]);
2438 return chip->status>>7;
2439 }
2440
ymf262_save_state(void * chippy,INT32 nAction)2441 void ymf262_save_state(void *chippy, INT32 nAction)
2442 {
2443 OPL3 *chip = (OPL3*)chippy;
2444
2445 if (nAction & ACB_DRIVER_DATA) {
2446 for (INT32 ch = 0; ch < 18; ch++) {
2447 OPL3_CH *channel = &chip->P_CH[ch];
2448 SCAN_VAR(channel->block_fnum);
2449 SCAN_VAR(channel->fc);
2450 SCAN_VAR(channel->ksl_base);
2451 SCAN_VAR(channel->kcode);
2452 SCAN_VAR(channel->extended);
2453
2454 for (INT32 sl = 0; sl < 2; sl++) {
2455 OPL3_SLOT *slot = &channel->SLOT[sl];
2456 SCAN_VAR(slot->ar);
2457 SCAN_VAR(slot->dr);
2458 SCAN_VAR(slot->rr);
2459 SCAN_VAR(slot->KSR);
2460 SCAN_VAR(slot->ksl);
2461 SCAN_VAR(slot->ksr);
2462 SCAN_VAR(slot->mul);
2463
2464 SCAN_VAR(slot->Cnt);
2465 SCAN_VAR(slot->Incr);
2466 SCAN_VAR(slot->FB);
2467 SCAN_VAR(slot->conn_enum);
2468 SCAN_VAR(slot->op1_out);
2469 SCAN_VAR(slot->CON);
2470
2471 SCAN_VAR(slot->eg_type);
2472 SCAN_VAR(slot->state);
2473 SCAN_VAR(slot->TL);
2474 SCAN_VAR(slot->TLL);
2475 SCAN_VAR(slot->volume);
2476 SCAN_VAR(slot->sl);
2477
2478 SCAN_VAR(slot->eg_m_ar);
2479 SCAN_VAR(slot->eg_sh_ar);
2480 SCAN_VAR(slot->eg_sel_ar);
2481 SCAN_VAR(slot->eg_m_dr);
2482 SCAN_VAR(slot->eg_sh_dr);
2483 SCAN_VAR(slot->eg_sel_dr);
2484 SCAN_VAR(slot->eg_m_rr);
2485 SCAN_VAR(slot->eg_sh_rr);
2486 SCAN_VAR(slot->eg_sel_rr);
2487
2488 SCAN_VAR(slot->key);
2489
2490 SCAN_VAR(slot->AMmask);
2491 SCAN_VAR(slot->vib);
2492
2493 SCAN_VAR(slot->waveform_number);
2494 SCAN_VAR(slot->wavetable);
2495 }
2496 }
2497
2498 SCAN_VAR(chip->pan);
2499 SCAN_VAR(chip->pan_ctrl_value);
2500
2501 SCAN_VAR(chip->lfo_am_depth);
2502 SCAN_VAR(chip->lfo_pm_depth_range);
2503
2504 SCAN_VAR(chip->OPL3_mode);
2505 SCAN_VAR(chip->rhythm);
2506
2507 SCAN_VAR(chip->T);
2508 SCAN_VAR(chip->st);
2509
2510 SCAN_VAR(chip->address);
2511 SCAN_VAR(chip->status);
2512 SCAN_VAR(chip->statusmask);
2513
2514 SCAN_VAR(chip->nts);
2515 }
2516
2517 if (nAction & ACB_WRITE) {
2518 for (int ch=0; ch<18; ch++) {
2519 for (int sl=0; sl<2; sl++) {
2520 OPL3_SLOT_CONNECT(chip, &(chip->P_CH[ch].SLOT[sl]));
2521 }
2522 }
2523 }
2524 }
2525
2526
ymf262_init(int clock,int rate,void (* irq_cb)(INT32,INT32),void (* timer_cb)(INT32,INT32,double))2527 void * ymf262_init(int clock, int rate, void (*irq_cb)(INT32, INT32), void (*timer_cb)(INT32, INT32, double))
2528 {
2529 OPL3 *chip = OPL3Create(clock,rate,OPL3_TYPE_YMF262);
2530
2531 if (chip) {
2532 chip->IRQHandler = irq_cb;
2533 chip->timer_handler = timer_cb;
2534 }
2535
2536 return chip;
2537 }
2538
ymf262_shutdown(void * chip)2539 void ymf262_shutdown(void *chip)
2540 {
2541 OPL3Destroy((OPL3 *)chip);
2542 }
ymf262_reset_chip(void * chip)2543 void ymf262_reset_chip(void *chip)
2544 {
2545 OPL3ResetChip((OPL3 *)chip);
2546 }
2547
ymf262_write(void * chip,int a,int v)2548 int ymf262_write(void *chip, int a, int v)
2549 {
2550 return OPL3Write((OPL3 *)chip, a, v);
2551 }
2552
ymf262_read(void * chip,int a)2553 unsigned char ymf262_read(void *chip, int a)
2554 {
2555 /* Note on status register: */
2556
2557 /* YM3526(OPL) and YM3812(OPL2) return bit2 and bit1 in HIGH state */
2558
2559 /* YMF262(OPL3) always returns bit2 and bit1 in LOW state */
2560 /* which can be used to identify the chip */
2561
2562 /* YMF278(OPL4) returns bit2 in LOW and bit1 in HIGH state ??? info from manual - not verified */
2563
2564 return OPL3Read((OPL3 *)chip, a);
2565 }
ymf262_timer_over(void * chip,int c)2566 int ymf262_timer_over(void *chip, int c)
2567 {
2568 return OPL3TimerOver((OPL3 *)chip, c);
2569 }
2570
2571
2572 /*
2573 ** Generate samples for one of the YMF262's
2574 **
2575 ** 'which' is the virtual YMF262 number
2576 ** '**buffers' is table of 4 pointers to the buffers: CH.A, CH.B, CH.C and CH.D
2577 ** 'length' is the number of samples that should be generated
2578 */
ymf262_update_one(void * _chip,INT16 ** buffers,int length)2579 void ymf262_update_one(void *_chip, INT16 **buffers, int length)
2580 {
2581 int i;
2582 OPL3 *chip = (OPL3 *)_chip;
2583 signed int *chanout = chip->chanout;
2584 UINT8 rhythm = chip->rhythm&0x20;
2585
2586 OPL3SAMPLE *ch_a = buffers[0];
2587 OPL3SAMPLE *ch_b = buffers[1];
2588 //OPL3SAMPLE *ch_c = buffers[0];
2589 //OPL3SAMPLE *ch_d = buffers[1];
2590
2591 for( i=0; i < length ; i++ )
2592 {
2593 int a,b,c,d;
2594
2595
2596 advance_lfo(chip);
2597
2598 /* clear channel outputs */
2599 memset(chip->chanout, 0, sizeof(chip->chanout));
2600
2601 #if 1
2602 /* register set #1 */
2603 chan_calc(chip, &chip->P_CH[0]); /* extended 4op ch#0 part 1 or 2op ch#0 */
2604 if (chip->P_CH[0].extended)
2605 chan_calc_ext(chip, &chip->P_CH[3]); /* extended 4op ch#0 part 2 */
2606 else
2607 chan_calc(chip, &chip->P_CH[3]); /* standard 2op ch#3 */
2608
2609
2610 chan_calc(chip, &chip->P_CH[1]); /* extended 4op ch#1 part 1 or 2op ch#1 */
2611 if (chip->P_CH[1].extended)
2612 chan_calc_ext(chip, &chip->P_CH[4]); /* extended 4op ch#1 part 2 */
2613 else
2614 chan_calc(chip, &chip->P_CH[4]); /* standard 2op ch#4 */
2615
2616
2617 chan_calc(chip, &chip->P_CH[2]); /* extended 4op ch#2 part 1 or 2op ch#2 */
2618 if (chip->P_CH[2].extended)
2619 chan_calc_ext(chip, &chip->P_CH[5]); /* extended 4op ch#2 part 2 */
2620 else
2621 chan_calc(chip, &chip->P_CH[5]); /* standard 2op ch#5 */
2622
2623
2624 if(!rhythm)
2625 {
2626 chan_calc(chip, &chip->P_CH[6]);
2627 chan_calc(chip, &chip->P_CH[7]);
2628 chan_calc(chip, &chip->P_CH[8]);
2629 }
2630 else /* Rhythm part */
2631 {
2632 chan_calc_rhythm(chip, &chip->P_CH[0], (chip->noise_rng>>0)&1 );
2633 }
2634
2635 /* register set #2 */
2636 chan_calc(chip, &chip->P_CH[ 9]);
2637 if (chip->P_CH[9].extended)
2638 chan_calc_ext(chip, &chip->P_CH[12]);
2639 else
2640 chan_calc(chip, &chip->P_CH[12]);
2641
2642
2643 chan_calc(chip, &chip->P_CH[10]);
2644 if (chip->P_CH[10].extended)
2645 chan_calc_ext(chip, &chip->P_CH[13]);
2646 else
2647 chan_calc(chip, &chip->P_CH[13]);
2648
2649
2650 chan_calc(chip, &chip->P_CH[11]);
2651 if (chip->P_CH[11].extended)
2652 chan_calc_ext(chip, &chip->P_CH[14]);
2653 else
2654 chan_calc(chip, &chip->P_CH[14]);
2655
2656
2657 /* channels 15,16,17 are fixed 2-operator channels only */
2658 chan_calc(chip, &chip->P_CH[15]);
2659 chan_calc(chip, &chip->P_CH[16]);
2660 chan_calc(chip, &chip->P_CH[17]);
2661 #endif
2662
2663 /* accumulator register set #1 */
2664 a = chanout[0] & chip->pan[0];
2665 b = chanout[0] & chip->pan[1];
2666 c = chanout[0] & chip->pan[2];
2667 d = chanout[0] & chip->pan[3];
2668 #if 1
2669 a += chanout[1] & chip->pan[4];
2670 b += chanout[1] & chip->pan[5];
2671 c += chanout[1] & chip->pan[6];
2672 d += chanout[1] & chip->pan[7];
2673 a += chanout[2] & chip->pan[8];
2674 b += chanout[2] & chip->pan[9];
2675 c += chanout[2] & chip->pan[10];
2676 d += chanout[2] & chip->pan[11];
2677
2678 a += chanout[3] & chip->pan[12];
2679 b += chanout[3] & chip->pan[13];
2680 c += chanout[3] & chip->pan[14];
2681 d += chanout[3] & chip->pan[15];
2682 a += chanout[4] & chip->pan[16];
2683 b += chanout[4] & chip->pan[17];
2684 c += chanout[4] & chip->pan[18];
2685 d += chanout[4] & chip->pan[19];
2686 a += chanout[5] & chip->pan[20];
2687 b += chanout[5] & chip->pan[21];
2688 c += chanout[5] & chip->pan[22];
2689 d += chanout[5] & chip->pan[23];
2690
2691 a += chanout[6] & chip->pan[24];
2692 b += chanout[6] & chip->pan[25];
2693 c += chanout[6] & chip->pan[26];
2694 d += chanout[6] & chip->pan[27];
2695 a += chanout[7] & chip->pan[28];
2696 b += chanout[7] & chip->pan[29];
2697 c += chanout[7] & chip->pan[30];
2698 d += chanout[7] & chip->pan[31];
2699 a += chanout[8] & chip->pan[32];
2700 b += chanout[8] & chip->pan[33];
2701 c += chanout[8] & chip->pan[34];
2702 d += chanout[8] & chip->pan[35];
2703
2704 /* accumulator register set #2 */
2705 a += chanout[9] & chip->pan[36];
2706 b += chanout[9] & chip->pan[37];
2707 c += chanout[9] & chip->pan[38];
2708 d += chanout[9] & chip->pan[39];
2709 a += chanout[10] & chip->pan[40];
2710 b += chanout[10] & chip->pan[41];
2711 c += chanout[10] & chip->pan[42];
2712 d += chanout[10] & chip->pan[43];
2713 a += chanout[11] & chip->pan[44];
2714 b += chanout[11] & chip->pan[45];
2715 c += chanout[11] & chip->pan[46];
2716 d += chanout[11] & chip->pan[47];
2717
2718 a += chanout[12] & chip->pan[48];
2719 b += chanout[12] & chip->pan[49];
2720 c += chanout[12] & chip->pan[50];
2721 d += chanout[12] & chip->pan[51];
2722 a += chanout[13] & chip->pan[52];
2723 b += chanout[13] & chip->pan[53];
2724 c += chanout[13] & chip->pan[54];
2725 d += chanout[13] & chip->pan[55];
2726 a += chanout[14] & chip->pan[56];
2727 b += chanout[14] & chip->pan[57];
2728 c += chanout[14] & chip->pan[58];
2729 d += chanout[14] & chip->pan[59];
2730
2731 a += chanout[15] & chip->pan[60];
2732 b += chanout[15] & chip->pan[61];
2733 c += chanout[15] & chip->pan[62];
2734 d += chanout[15] & chip->pan[63];
2735 a += chanout[16] & chip->pan[64];
2736 b += chanout[16] & chip->pan[65];
2737 c += chanout[16] & chip->pan[66];
2738 d += chanout[16] & chip->pan[67];
2739 a += chanout[17] & chip->pan[68];
2740 b += chanout[17] & chip->pan[69];
2741 c += chanout[17] & chip->pan[70];
2742 d += chanout[17] & chip->pan[71];
2743 #endif
2744 a >>= FINAL_SH;
2745 b >>= FINAL_SH;
2746 c >>= FINAL_SH;
2747 d >>= FINAL_SH;
2748
2749 /* limit check */
2750 a = limit( a , MAXOUT, MINOUT );
2751 b = limit( b , MAXOUT, MINOUT );
2752 c = limit( c , MAXOUT, MINOUT );
2753 d = limit( d , MAXOUT, MINOUT );
2754
2755 #ifdef SAVE_SAMPLE
2756 if (which==0)
2757 {
2758 SAVE_ALL_CHANNELS
2759 }
2760 #endif
2761
2762 /* store to sound buffer */
2763 ch_a[i] = limit(a + c, MAXOUT, MINOUT );
2764 ch_b[i] = limit(b + d, MAXOUT, MINOUT );
2765 //ch_c[i] = c;
2766 //ch_d[i] = d;
2767
2768 advance(chip);
2769 }
2770
2771 }
2772