1 /*
2  * Copyright (c) 2015, Marcos Medeiros
3  * Licensed under BSD 3-clause.
4  */
5 #ifndef TMS34010_DEFS_H
6 #define TMS34010_DEFS_H
7 
8 #define R_BIT   (opcode & 0x10)
9 #define RS      (((opcode >> 5) & 0xF) | R_BIT)
10 #define RD      ((opcode & 0xF) | R_BIT)
11 #define RS_n    ((opcode >> 5) & 0xF)
12 #define RD_n    (opcode & 0xF)
13 #define K       ((opcode >> 5) & 0x1F)
14 #define KN      ((~opcode >> 5) & 0x1F)
15 
16 #define R(i)    cpu->r[(i)|R_BIT]->value
17 
18 #define OFFS    ((opcode >> 5) & 0x1F)
19 #define BKW_DIR (opcode & (1 << 10))
20 
21 #define _rs     cpu->r[RS]->value
22 #define _rd     cpu->r[RD]->value
23 #define _rd_0   cpu->r[RD+0]->value
24 #define _rd_1   cpu->r[RD+1]->value
25 #define _pc     cpu->pc
26 #define _sp     cpu->sp.value
27 #define _st     cpu->st
28 
29 #define _rsx     cpu->r[RS]->datavalue.x
30 #define _rdx     cpu->r[RD]->datavalue.x
31 #define _rsy     cpu->r[RS]->datavalue.y
32 #define _rdy     cpu->r[RD]->datavalue.y
33 
34 #define ODD_RD  (RD_n & 1)
35 
36 #define ZF  (_st & ST_Z)
37 #define CF  (_st & ST_C)
38 #define VF  (_st & ST_V)
39 #define NF  (_st & ST_N)
40 
41 #define FS0 (_st & ST_FS0_MASK)
42 #define FS1 ((_st & ST_FS1_MASK) >> ST_FS1_SHIFT)
43 #define FE0 ((_st & ST_FE0) ? 32 : 0)
44 #define FE1 ((_st & ST_FE1) ? 32 : 0)
45 
46 #define CONSUME_CYCLES(n) do { cpu->icounter -= (n); tms::check_timer(cpu, (n)); } while (0)
47 
48 #define FW(i)         ((_st >> (i ? 6 : 0)) & 0x1f)
49 #define FWEX(i)       ((_st >> (i ? 6 : 0)) & 0x3f)
50 
51 #define FW0_  FW(0)
52 #define FW1_  FW(1)
53 #define RFW0 FWEX(0)
54 #define RFW1 FWEX(1)
55 
56 #define FW0  fw_lut[FW0_]
57 #define FW1  fw_lut[FW1_]
58 
59 #define wsign_ext(n)    ((sdword)(sword)(n))
60 
61 #define update_zn(val)              \
62         _st &= ~(ST_N | ST_Z);      \
63         if (!val)                   \
64             _st |= ST_Z;            \
65         _st |= val & SIGN_BIT32;
66 
67 #define update_z(val)   \
68         _st &= ~ST_Z;   \
69         if (!val)        \
70             _st |= ST_Z;
71 
72 #define SADDR     cpu->b[_SADDR].value
73 #define SPTCH       cpu->b[_SPTCH].value
74 #define SADDR_R   cpu->b[_SADDR]
75 
76 #define DADDR       cpu->b[_DADDR].value
77 #define DADDR_X   cpu->b[_DADDR].datavalue.x
78 #define DADDR_Y   cpu->b[_DADDR].datavalue.y
79 #define DADDR_R   cpu->b[_DADDR]
80 
81 #define DPTCH   cpu->b[_DPTCH].value
82 #define OFFSET  cpu->b[_OFFSET].value
83 #define WSTART  cpu->b[_WSTART].value
84 #define WEND    cpu->b[_WEND].value
85 
86 #define WSTART_X  cpu->b[_WSTART].datavalue.x
87 #define WSTART_Y  cpu->b[_WSTART].datavalue.y
88 #define WEND_X    cpu->b[_WEND].datavalue.x
89 #define WEND_Y    cpu->b[_WEND].datavalue.y
90 
91 
92 #define DYDX    cpu->b[_DYDX].value
93 #define DYDX_X    cpu->b[_DYDX].datavalue.x
94 #define DYDX_Y    cpu->b[_DYDX].datavalue.y
95 
96 #define COLOR0  cpu->b[_COLOR0].value
97 #define COLOR1  cpu->b[_COLOR1].value
98 #define COUNT   cpu->b[COUNT].value
99 #define INC1    cpu->b[INC1].value
100 #define INC2    cpu->b[INC2].value
101 #define PATTRN  cpu->b[PATTRN].value
102 #define TEMP    cpu->b[TEMP].value
103 
104 #define PPOP    ((cpu->io_regs[CONTROL] >> 10) & 0x1F)
105 
106 #endif // TMS34010_DEFS_H
107