1
2 // AM3 Functions (for ReadAM)
3 // **************************
4
am3Register(void)5 static UINT32 am3Register(void)
6 {
7 switch (modDim)
8 {
9 case 0:
10 SETREG8(v60.reg[modVal&0x1F], modWriteValB);
11 break;
12 case 1:
13 SETREG16(v60.reg[modVal&0x1F], modWriteValH);
14 break;
15 case 2:
16 v60.reg[modVal&0x1F] = modWriteValW;
17 break;
18 }
19
20 return 1;
21 }
22
am3RegisterIndirect(void)23 static UINT32 am3RegisterIndirect(void)
24 {
25 switch (modDim)
26 {
27 case 0:
28 MemWrite8(v60.reg[modVal&0x1F], modWriteValB);
29 break;
30 case 1:
31 MemWrite16(v60.reg[modVal&0x1F], modWriteValH);
32 break;
33 case 2:
34 MemWrite32(v60.reg[modVal&0x1F], modWriteValW);
35 break;
36 }
37
38 return 1;
39 }
40
am3RegisterIndirectIndexed(void)41 static UINT32 am3RegisterIndirectIndexed(void)
42 {
43 switch (modDim)
44 {
45 case 0:
46 MemWrite8(v60.reg[modVal2&0x1F] + v60.reg[modVal&0x1F], modWriteValB);
47 break;
48 case 1:
49 MemWrite16(v60.reg[modVal2&0x1F] + v60.reg[modVal&0x1F] * 2, modWriteValH);
50 break;
51 case 2:
52 MemWrite32(v60.reg[modVal2&0x1F] + v60.reg[modVal&0x1F] * 4, modWriteValW);
53 break;
54 }
55
56 return 2;
57 }
58
am3Autoincrement(void)59 static UINT32 am3Autoincrement(void)
60 {
61 switch (modDim)
62 {
63 case 0:
64 MemWrite8(v60.reg[modVal&0x1F], modWriteValB);
65 v60.reg[modVal&0x1F] += 1;
66 break;
67 case 1:
68 MemWrite16(v60.reg[modVal&0x1F], modWriteValH);
69 v60.reg[modVal&0x1F] += 2;
70 break;
71 case 2:
72 MemWrite32(v60.reg[modVal&0x1F], modWriteValW);
73 v60.reg[modVal&0x1F] += 4;
74 break;
75 }
76
77 return 1;
78 }
79
am3Autodecrement(void)80 static UINT32 am3Autodecrement(void)
81 {
82 switch (modDim)
83 {
84 case 0:
85 v60.reg[modVal&0x1F] -= 1;
86 MemWrite8(v60.reg[modVal&0x1F], modWriteValB);
87 break;
88 case 1:
89 v60.reg[modVal&0x1F] -= 2;
90 MemWrite16(v60.reg[modVal&0x1F], modWriteValH);
91 break;
92 case 2:
93 v60.reg[modVal&0x1F] -= 4;
94 MemWrite32(v60.reg[modVal&0x1F], modWriteValW);
95 break;
96 }
97
98 return 1;
99 }
100
am3Displacement8(void)101 static UINT32 am3Displacement8(void)
102 {
103 switch (modDim)
104 {
105 case 0:
106 MemWrite8(v60.reg[modVal&0x1F] + (INT8)OpRead8(modAdd+1), modWriteValB);
107 break;
108 case 1:
109 MemWrite16(v60.reg[modVal&0x1F] + (INT8)OpRead8(modAdd+1), modWriteValH);
110 break;
111 case 2:
112 MemWrite32(v60.reg[modVal&0x1F] + (INT8)OpRead8(modAdd+1), modWriteValW);
113 break;
114 }
115
116 return 2;
117 }
118
am3Displacement16(void)119 static UINT32 am3Displacement16(void)
120 {
121 switch (modDim)
122 {
123 case 0:
124 MemWrite8(v60.reg[modVal&0x1F] + (INT16)OpRead16(modAdd+1), modWriteValB);
125 break;
126 case 1:
127 MemWrite16(v60.reg[modVal&0x1F] + (INT16)OpRead16(modAdd+1), modWriteValH);
128 break;
129 case 2:
130 MemWrite32(v60.reg[modVal&0x1F] + (INT16)OpRead16(modAdd+1), modWriteValW);
131 break;
132 }
133
134 return 3;
135 }
136
am3Displacement32(void)137 static UINT32 am3Displacement32(void)
138 {
139 switch (modDim)
140 {
141 case 0:
142 MemWrite8(v60.reg[modVal&0x1F] + OpRead32(modAdd+1), modWriteValB);
143 break;
144 case 1:
145 MemWrite16(v60.reg[modVal&0x1F] + OpRead32(modAdd+1), modWriteValH);
146 break;
147 case 2:
148 MemWrite32(v60.reg[modVal&0x1F] + OpRead32(modAdd+1), modWriteValW);
149 break;
150 }
151
152 return 5;
153 }
154
155
am3DisplacementIndexed8(void)156 static UINT32 am3DisplacementIndexed8(void)
157 {
158 switch (modDim)
159 {
160 case 0:
161 MemWrite8(v60.reg[modVal2&0x1F] + (INT8)OpRead8(modAdd+2) + v60.reg[modVal&0x1F], modWriteValB);
162 break;
163 case 1:
164 MemWrite16(v60.reg[modVal2&0x1F] + (INT8)OpRead8(modAdd+2) + v60.reg[modVal&0x1F] * 2, modWriteValH);
165 break;
166 case 2:
167 MemWrite32(v60.reg[modVal2&0x1F] + (INT8)OpRead8(modAdd+2) + v60.reg[modVal&0x1F] * 4, modWriteValW);
168 break;
169 }
170
171 return 3;
172 }
173
am3DisplacementIndexed16(void)174 static UINT32 am3DisplacementIndexed16(void)
175 {
176 switch (modDim)
177 {
178 case 0:
179 MemWrite8(v60.reg[modVal2&0x1F] + (INT16)OpRead16(modAdd+2) + v60.reg[modVal&0x1F], modWriteValB);
180 break;
181 case 1:
182 MemWrite16(v60.reg[modVal2&0x1F] + (INT16)OpRead16(modAdd+2) + v60.reg[modVal&0x1F] * 2, modWriteValH);
183 break;
184 case 2:
185 MemWrite32(v60.reg[modVal2&0x1F] + (INT16)OpRead16(modAdd+2) + v60.reg[modVal&0x1F] * 4, modWriteValW);
186 break;
187 }
188
189 return 4;
190 }
191
am3DisplacementIndexed32(void)192 static UINT32 am3DisplacementIndexed32(void)
193 {
194 switch (modDim)
195 {
196 case 0:
197 MemWrite8(v60.reg[modVal2&0x1F] + OpRead32(modAdd+2) + v60.reg[modVal&0x1F], modWriteValB);
198 break;
199 case 1:
200 MemWrite16(v60.reg[modVal2&0x1F] + OpRead32(modAdd+2) + v60.reg[modVal&0x1F] * 2, modWriteValH);
201 break;
202 case 2:
203 MemWrite32(v60.reg[modVal2&0x1F] + OpRead32(modAdd+2) + v60.reg[modVal&0x1F] * 4, modWriteValW);
204 break;
205 }
206
207 return 6;
208 }
209
210
am3PCDisplacement8(void)211 static UINT32 am3PCDisplacement8(void)
212 {
213 switch (modDim)
214 {
215 case 0:
216 MemWrite8(PC + (INT8)OpRead8(modAdd+1), modWriteValB);
217 break;
218 case 1:
219 MemWrite16(PC + (INT8)OpRead8(modAdd+1), modWriteValH);
220 break;
221 case 2:
222 MemWrite32(PC + (INT8)OpRead8(modAdd+1), modWriteValW);
223 break;
224 }
225
226 return 2;
227 }
228
am3PCDisplacement16(void)229 static UINT32 am3PCDisplacement16(void)
230 {
231 switch (modDim)
232 {
233 case 0:
234 MemWrite8(PC + (INT16)OpRead16(modAdd+1), modWriteValB);
235 break;
236 case 1:
237 MemWrite16(PC + (INT16)OpRead16(modAdd+1), modWriteValH);
238 break;
239 case 2:
240 MemWrite32(PC + (INT16)OpRead16(modAdd+1), modWriteValW);
241 break;
242 }
243
244 return 3;
245 }
246
am3PCDisplacement32(void)247 static UINT32 am3PCDisplacement32(void)
248 {
249 switch (modDim)
250 {
251 case 0:
252 MemWrite8(PC + OpRead32(modAdd+1), modWriteValB);
253 break;
254 case 1:
255 MemWrite16(PC + OpRead32(modAdd+1), modWriteValH);
256 break;
257 case 2:
258 MemWrite32(PC + OpRead32(modAdd+1), modWriteValW);
259 break;
260 }
261
262 return 5;
263 }
264
am3PCDisplacementIndexed8(void)265 static UINT32 am3PCDisplacementIndexed8(void)
266 {
267 switch (modDim)
268 {
269 case 0:
270 MemWrite8(PC + (INT8)OpRead8(modAdd+2) + v60.reg[modVal&0x1F], modWriteValB);
271 break;
272 case 1:
273 MemWrite16(PC + (INT8)OpRead8(modAdd+2) + v60.reg[modVal&0x1F] * 2, modWriteValH);
274 break;
275 case 2:
276 MemWrite32(PC + (INT8)OpRead8(modAdd+2) + v60.reg[modVal&0x1F] * 4, modWriteValW);
277 break;
278 }
279
280 return 3;
281 }
282
am3PCDisplacementIndexed16(void)283 static UINT32 am3PCDisplacementIndexed16(void)
284 {
285 switch (modDim)
286 {
287 case 0:
288 MemWrite8(PC + (INT16)OpRead16(modAdd+2) + v60.reg[modVal&0x1F], modWriteValB);
289 break;
290 case 1:
291 MemWrite16(PC + (INT16)OpRead16(modAdd+2) + v60.reg[modVal&0x1F] * 2, modWriteValH);
292 break;
293 case 2:
294 MemWrite32(PC + (INT16)OpRead16(modAdd+2) + v60.reg[modVal&0x1F] * 4, modWriteValW);
295 break;
296 }
297
298 return 4;
299 }
300
am3PCDisplacementIndexed32(void)301 static UINT32 am3PCDisplacementIndexed32(void)
302 {
303 switch (modDim)
304 {
305 case 0:
306 MemWrite8(PC + OpRead32(modAdd+2) + v60.reg[modVal&0x1F], modWriteValB);
307 break;
308 case 1:
309 MemWrite16(PC + OpRead32(modAdd+2) + v60.reg[modVal&0x1F] * 2, modWriteValH);
310 break;
311 case 2:
312 MemWrite32(PC + OpRead32(modAdd+2) + v60.reg[modVal&0x1F] * 4, modWriteValW);
313 break;
314 }
315
316 return 6;
317 }
318
am3DisplacementIndirect8(void)319 static UINT32 am3DisplacementIndirect8(void)
320 {
321 switch (modDim)
322 {
323 case 0:
324 MemWrite8(MemRead32(v60.reg[modVal&0x1F] + (INT8)OpRead8(modAdd+1)), modWriteValB);
325 break;
326 case 1:
327 MemWrite16(MemRead32(v60.reg[modVal&0x1F] + (INT8)OpRead8(modAdd+1)), modWriteValH);
328 break;
329 case 2:
330 MemWrite32(MemRead32(v60.reg[modVal&0x1F] + (INT8)OpRead8(modAdd+1)), modWriteValW);
331 break;
332 }
333
334 return 2;
335 }
336
am3DisplacementIndirect16(void)337 static UINT32 am3DisplacementIndirect16(void)
338 {
339 switch (modDim)
340 {
341 case 0:
342 MemWrite8(MemRead32(v60.reg[modVal&0x1F] + (INT16)OpRead16(modAdd+1)), modWriteValB);
343 break;
344 case 1:
345 MemWrite16(MemRead32(v60.reg[modVal&0x1F] + (INT16)OpRead16(modAdd+1)), modWriteValH);
346 break;
347 case 2:
348 MemWrite32(MemRead32(v60.reg[modVal&0x1F] + (INT16)OpRead16(modAdd+1)), modWriteValW);
349 break;
350 }
351
352 return 3;
353 }
354
am3DisplacementIndirect32(void)355 static UINT32 am3DisplacementIndirect32(void)
356 {
357 switch (modDim)
358 {
359 case 0:
360 MemWrite8(MemRead32(v60.reg[modVal&0x1F] + OpRead32(modAdd+1)), modWriteValB);
361 break;
362 case 1:
363 MemWrite16(MemRead32(v60.reg[modVal&0x1F] + OpRead32(modAdd+1)), modWriteValH);
364 break;
365 case 2:
366 MemWrite32(MemRead32(v60.reg[modVal&0x1F] + OpRead32(modAdd+1)), modWriteValW);
367 break;
368 }
369
370 return 5;
371 }
372
373
am3DisplacementIndirectIndexed8(void)374 static UINT32 am3DisplacementIndirectIndexed8(void)
375 {
376 switch (modDim)
377 {
378 case 0:
379 MemWrite8(MemRead32(v60.reg[modVal2&0x1F] + (INT8)OpRead8(modAdd+2)) + v60.reg[modVal&0x1F], modWriteValB);
380 break;
381 case 1:
382 MemWrite16(MemRead32(v60.reg[modVal2&0x1F] + (INT8)OpRead8(modAdd+2)) + v60.reg[modVal&0x1F] * 2, modWriteValH);
383 break;
384 case 2:
385 MemWrite32(MemRead32(v60.reg[modVal2&0x1F] + (INT8)OpRead8(modAdd+2)) + v60.reg[modVal&0x1F] * 4, modWriteValW);
386 break;
387 }
388
389 return 3;
390 }
391
am3DisplacementIndirectIndexed16(void)392 static UINT32 am3DisplacementIndirectIndexed16(void)
393 {
394 switch (modDim)
395 {
396 case 0:
397 MemWrite8(MemRead32(v60.reg[modVal2&0x1F] + (INT16)OpRead16(modAdd+2)) + v60.reg[modVal&0x1F], modWriteValB);
398 break;
399 case 1:
400 MemWrite16(MemRead32(v60.reg[modVal2&0x1F] + (INT16)OpRead16(modAdd+2)) + v60.reg[modVal&0x1F] * 2, modWriteValH);
401 break;
402 case 2:
403 MemWrite32(MemRead32(v60.reg[modVal2&0x1F] + (INT16)OpRead16(modAdd+2)) + v60.reg[modVal&0x1F] * 4, modWriteValW);
404 break;
405 }
406
407 return 4;
408 }
409
am3DisplacementIndirectIndexed32(void)410 static UINT32 am3DisplacementIndirectIndexed32(void)
411 {
412 switch (modDim)
413 {
414 case 0:
415 MemWrite8(MemRead32(v60.reg[modVal2&0x1F] + OpRead32(modAdd+2)) + v60.reg[modVal&0x1F], modWriteValB);
416 break;
417 case 1:
418 MemWrite16(MemRead32(v60.reg[modVal2&0x1F] + OpRead32(modAdd+2)) + v60.reg[modVal&0x1F] * 2, modWriteValH);
419 break;
420 case 2:
421 MemWrite32(MemRead32(v60.reg[modVal2&0x1F] + OpRead32(modAdd+2)) + v60.reg[modVal&0x1F] * 4, modWriteValW);
422 break;
423 }
424
425 return 6;
426 }
427
am3PCDisplacementIndirect8(void)428 static UINT32 am3PCDisplacementIndirect8(void)
429 {
430 switch (modDim)
431 {
432 case 0:
433 MemWrite8(MemRead32(PC + (INT8)OpRead8(modAdd+1)), modWriteValB);
434 break;
435 case 1:
436 MemWrite16(MemRead32(PC + (INT8)OpRead8(modAdd+1)), modWriteValH);
437 break;
438 case 2:
439 MemWrite32(MemRead32(PC + (INT8)OpRead8(modAdd+1)), modWriteValW);
440 break;
441 }
442
443 return 2;
444 }
445
am3PCDisplacementIndirect16(void)446 static UINT32 am3PCDisplacementIndirect16(void)
447 {
448 switch (modDim)
449 {
450 case 0:
451 MemWrite8(MemRead32(PC + (INT16)OpRead16(modAdd+1)), modWriteValB);
452 break;
453 case 1:
454 MemWrite16(MemRead32(PC + (INT16)OpRead16(modAdd+1)), modWriteValH);
455 break;
456 case 2:
457 MemWrite32(MemRead32(PC + (INT16)OpRead16(modAdd+1)), modWriteValW);
458 break;
459 }
460
461 return 3;
462 }
463
am3PCDisplacementIndirect32(void)464 static UINT32 am3PCDisplacementIndirect32(void)
465 {
466 switch (modDim)
467 {
468 case 0:
469 MemWrite8(MemRead32(PC + OpRead32(modAdd+1)), modWriteValB);
470 break;
471 case 1:
472 MemWrite16(MemRead32(PC + OpRead32(modAdd+1)), modWriteValH);
473 break;
474 case 2:
475 MemWrite32(MemRead32(PC + OpRead32(modAdd+1)), modWriteValW);
476 break;
477 }
478
479 return 5;
480 }
481
482
am3PCDisplacementIndirectIndexed8(void)483 static UINT32 am3PCDisplacementIndirectIndexed8(void)
484 {
485 switch (modDim)
486 {
487 case 0:
488 MemWrite8(MemRead32(PC + (INT8)OpRead8(modAdd+2)) + v60.reg[modVal&0x1F], modWriteValB);
489 break;
490 case 1:
491 MemWrite16(MemRead32(PC + (INT8)OpRead8(modAdd+2)) + v60.reg[modVal&0x1F] * 2, modWriteValH);
492 break;
493 case 2:
494 MemWrite32(MemRead32(PC + (INT8)OpRead8(modAdd+2)) + v60.reg[modVal&0x1F] * 4, modWriteValW);
495 break;
496 }
497
498 return 3;
499 }
500
am3PCDisplacementIndirectIndexed16(void)501 static UINT32 am3PCDisplacementIndirectIndexed16(void)
502 {
503 switch (modDim)
504 {
505 case 0:
506 MemWrite8(MemRead32(PC + (INT16)OpRead16(modAdd+2)) + v60.reg[modVal&0x1F], modWriteValB);
507 break;
508 case 1:
509 MemWrite16(MemRead32(PC + (INT16)OpRead16(modAdd+2)) + v60.reg[modVal&0x1F] * 2, modWriteValH);
510 break;
511 case 2:
512 MemWrite32(MemRead32(PC + (INT16)OpRead16(modAdd+2)) + v60.reg[modVal&0x1F] * 4, modWriteValW);
513 break;
514 }
515
516 return 4;
517 }
518
am3PCDisplacementIndirectIndexed32(void)519 static UINT32 am3PCDisplacementIndirectIndexed32(void)
520 {
521 switch (modDim)
522 {
523 case 0:
524 MemWrite8(MemRead32(PC + OpRead32(modAdd+2)) + v60.reg[modVal&0x1F], modWriteValB);
525 break;
526 case 1:
527 MemWrite16(MemRead32(PC + OpRead32(modAdd+2)) + v60.reg[modVal&0x1F] * 2, modWriteValH);
528 break;
529 case 2:
530 MemWrite32(MemRead32(PC + OpRead32(modAdd+2)) + v60.reg[modVal&0x1F] * 4, modWriteValW);
531 break;
532 }
533
534 return 6;
535 }
536
537
am3DoubleDisplacement8(void)538 static UINT32 am3DoubleDisplacement8(void)
539 {
540 switch (modDim)
541 {
542 case 0:
543 MemWrite8(MemRead32(v60.reg[modVal&0x1F] + (INT8)OpRead8(modAdd+1)) + (INT8)OpRead8(modAdd+2), modWriteValB);
544 break;
545 case 1:
546 MemWrite16(MemRead32(v60.reg[modVal&0x1F] + (INT8)OpRead8(modAdd+1)) + (INT8)OpRead8(modAdd+2), modWriteValH);
547 break;
548 case 2:
549 MemWrite32(MemRead32(v60.reg[modVal&0x1F] + (INT8)OpRead8(modAdd+1)) + (INT8)OpRead8(modAdd+2), modWriteValW);
550 break;
551 }
552
553 return 3;
554 }
555
am3DoubleDisplacement16(void)556 static UINT32 am3DoubleDisplacement16(void)
557 {
558 switch (modDim)
559 {
560 case 0:
561 MemWrite8(MemRead32(v60.reg[modVal&0x1F] + (INT16)OpRead16(modAdd+1)) + (INT16)OpRead16(modAdd+3), modWriteValB);
562 break;
563 case 1:
564 MemWrite16(MemRead32(v60.reg[modVal&0x1F] + (INT16)OpRead16(modAdd+1)) + (INT16)OpRead16(modAdd+3), modWriteValH);
565 break;
566 case 2:
567 MemWrite32(MemRead32(v60.reg[modVal&0x1F] + (INT16)OpRead16(modAdd+1)) + (INT16)OpRead16(modAdd+3), modWriteValW);
568 break;
569 }
570
571 return 5;
572 }
573
am3DoubleDisplacement32(void)574 static UINT32 am3DoubleDisplacement32(void)
575 {
576 switch (modDim)
577 {
578 case 0:
579 MemWrite8(MemRead32(v60.reg[modVal&0x1F] + OpRead32(modAdd+1)) + OpRead32(modAdd+5), modWriteValB);
580 break;
581 case 1:
582 MemWrite16(MemRead32(v60.reg[modVal&0x1F] + OpRead32(modAdd+1)) + OpRead32(modAdd+5), modWriteValH);
583 break;
584 case 2:
585 MemWrite32(MemRead32(v60.reg[modVal&0x1F] + OpRead32(modAdd+1)) + OpRead32(modAdd+5), modWriteValW);
586 break;
587 }
588
589 return 9;
590 }
591
592
am3PCDoubleDisplacement8(void)593 static UINT32 am3PCDoubleDisplacement8(void)
594 {
595 switch (modDim)
596 {
597 case 0:
598 MemWrite8(MemRead32(PC + (INT8)OpRead8(modAdd+1)) + (INT8)OpRead8(modAdd+2), modWriteValB);
599 break;
600 case 1:
601 MemWrite16(MemRead32(PC + (INT8)OpRead8(modAdd+1)) + (INT8)OpRead8(modAdd+2), modWriteValH);
602 break;
603 case 2:
604 MemWrite32(MemRead32(PC + (INT8)OpRead8(modAdd+1)) + (INT8)OpRead8(modAdd+2), modWriteValW);
605 break;
606 }
607
608 return 3;
609 }
610
am3PCDoubleDisplacement16(void)611 static UINT32 am3PCDoubleDisplacement16(void)
612 {
613 switch (modDim)
614 {
615 case 0:
616 MemWrite8(MemRead32(PC + (INT16)OpRead16(modAdd+1)) + (INT16)OpRead16(modAdd+3), modWriteValB);
617 break;
618 case 1:
619 MemWrite16(MemRead32(PC + (INT16)OpRead16(modAdd+1)) + (INT16)OpRead16(modAdd+3), modWriteValH);
620 break;
621 case 2:
622 MemWrite32(MemRead32(PC + (INT16)OpRead16(modAdd+1)) + (INT16)OpRead16(modAdd+3), modWriteValW);
623 break;
624 }
625
626 return 5;
627 }
628
am3PCDoubleDisplacement32(void)629 static UINT32 am3PCDoubleDisplacement32(void)
630 {
631 switch (modDim)
632 {
633 case 0:
634 MemWrite8(MemRead32(PC + OpRead32(modAdd+1)) + OpRead32(modAdd+5), modWriteValB);
635 break;
636 case 1:
637 MemWrite16(MemRead32(PC + OpRead32(modAdd+1)) + OpRead32(modAdd+5), modWriteValH);
638 break;
639 case 2:
640 MemWrite32(MemRead32(PC + OpRead32(modAdd+1)) + OpRead32(modAdd+5), modWriteValW);
641 break;
642 }
643
644 return 9;
645 }
646
am3DirectAddress(void)647 static UINT32 am3DirectAddress(void)
648 {
649 switch (modDim)
650 {
651 case 0:
652 MemWrite8(OpRead32(modAdd+1), modWriteValB);
653 break;
654 case 1:
655 MemWrite16(OpRead32(modAdd+1), modWriteValH);
656 break;
657 case 2:
658 MemWrite32(OpRead32(modAdd+1), modWriteValW);
659 break;
660 }
661
662 return 5;
663 }
664
am3DirectAddressIndexed(void)665 static UINT32 am3DirectAddressIndexed(void)
666 {
667 switch (modDim)
668 {
669 case 0:
670 MemWrite8(OpRead32(modAdd+2) + v60.reg[modVal&0x1F], modWriteValB);
671 break;
672 case 1:
673 MemWrite16(OpRead32(modAdd+2) + v60.reg[modVal&0x1F] * 2, modWriteValH);
674 break;
675 case 2:
676 MemWrite32(OpRead32(modAdd+2) + v60.reg[modVal&0x1F] * 4, modWriteValW);
677 break;
678 }
679
680 return 6;
681 }
682
am3DirectAddressDeferred(void)683 static UINT32 am3DirectAddressDeferred(void)
684 {
685 switch (modDim)
686 {
687 case 0:
688 MemWrite8(MemRead32(OpRead32(modAdd+1)), modWriteValB);
689 break;
690 case 1:
691 MemWrite16(MemRead32(OpRead32(modAdd+1)), modWriteValH);
692 break;
693 case 2:
694 MemWrite32(MemRead32(OpRead32(modAdd+1)), modWriteValW);
695 break;
696 }
697
698 return 5;
699 }
700
am3DirectAddressDeferredIndexed(void)701 static UINT32 am3DirectAddressDeferredIndexed(void)
702 {
703 switch (modDim)
704 {
705 case 0:
706 MemWrite8(MemRead32(OpRead32(modAdd+2)) + v60.reg[modVal&0x1F], modWriteValB);
707 break;
708 case 1:
709 MemWrite16(MemRead32(OpRead32(modAdd+2)) + v60.reg[modVal&0x1F], modWriteValH);
710 break;
711 case 2:
712 MemWrite32(MemRead32(OpRead32(modAdd+2)) + v60.reg[modVal&0x1F], modWriteValW);
713 break;
714 }
715
716 return 6;
717 }
718
am3Immediate(void)719 static UINT32 am3Immediate(void)
720 {
721 //fatalerror("CPU - AM3 - IMM (PC=%06x)", PC);
722 return 0; /* never reached, fatalerror won't return */
723 }
724
am3ImmediateQuick(void)725 static UINT32 am3ImmediateQuick(void)
726 {
727 //fatalerror("CPU - AM3 - IMMQ (PC=%06x)", PC);
728 return 0; /* never reached, fatalerror won't return */
729 }
730
731
732
733 // AM3 Tables (for ReadAMAddress)
734 // ******************************
735
am3Error1(void)736 static UINT32 am3Error1(void)
737 {
738 //fatalerror("CPU - AM3 - 1 (PC=%06x)", PC);
739 return 0; /* never reached, fatalerror won't return */
740 }
741
am3Error2(void)742 static UINT32 am3Error2(void)
743 {
744 //fatalerror("CPU - AM3 - 2 (PC=%06x)", PC);
745 return 0; /* never reached, fatalerror won't return */
746 }
747 #if 0
748 static UINT32 am3Error3(void)
749 {
750 //fatalerror("CPU - AM3 - 3 (PC=%06x)", PC);
751 return 0; /* never reached, fatalerror won't return */
752 }
753 #endif
am3Error4(void)754 static UINT32 am3Error4(void)
755 {
756 //fatalerror("CPU - AM3 - 4 (PC=%06x)", PC);
757 return 0; /* never reached, fatalerror won't return */
758 }
759
am3Error5(void)760 static UINT32 am3Error5(void)
761 {
762 //fatalerror("CPU - AM3 - 5 (PC=%06x)", PC);
763 return 0; /* never reached, fatalerror won't return */
764 }
765
766 static UINT32 (*const AMTable3_G7a[16])(void) =
767 {
768 am3PCDisplacementIndexed8,
769 am3PCDisplacementIndexed16,
770 am3PCDisplacementIndexed32,
771 am3DirectAddressIndexed,
772 am3Error5,
773 am3Error5,
774 am3Error5,
775 am3Error5,
776 am3PCDisplacementIndirectIndexed8,
777 am3PCDisplacementIndirectIndexed16,
778 am3PCDisplacementIndirectIndexed32,
779 am3DirectAddressDeferredIndexed,
780 am3Error5,
781 am3Error5,
782 am3Error5,
783 am3Error5
784 };
785
am3Group7a(void)786 static UINT32 am3Group7a(void)
787 {
788 if (!(modVal2&0x10))
789 return am3Error4();
790
791 return AMTable3_G7a[modVal2&0xF]();
792 }
793
794 static UINT32 (*const AMTable3_G7[32])(void) =
795 {
796 am3ImmediateQuick,
797 am3ImmediateQuick,
798 am3ImmediateQuick,
799 am3ImmediateQuick,
800 am3ImmediateQuick,
801 am3ImmediateQuick,
802 am3ImmediateQuick,
803 am3ImmediateQuick,
804 am3ImmediateQuick,
805 am3ImmediateQuick,
806 am3ImmediateQuick,
807 am3ImmediateQuick,
808 am3ImmediateQuick,
809 am3ImmediateQuick,
810 am3ImmediateQuick,
811 am3ImmediateQuick,
812 am3PCDisplacement8,
813 am3PCDisplacement16,
814 am3PCDisplacement32,
815 am3DirectAddress,
816 am3Immediate,
817 am3Error2,
818 am3Error2,
819 am3Error2,
820 am3PCDisplacementIndirect8,
821 am3PCDisplacementIndirect16,
822 am3PCDisplacementIndirect32,
823 am3DirectAddressDeferred,
824 am3PCDoubleDisplacement8,
825 am3PCDoubleDisplacement16,
826 am3PCDoubleDisplacement32,
827 am3Error2
828 };
829
830 static UINT32 (*const AMTable3_G6[8])(void) =
831 {
832 am3DisplacementIndexed8,
833 am3DisplacementIndexed16,
834 am3DisplacementIndexed32,
835 am3RegisterIndirectIndexed,
836 am3DisplacementIndirectIndexed8,
837 am3DisplacementIndirectIndexed16,
838 am3DisplacementIndirectIndexed32,
839 am3Group7a
840 };
841
842
843
844
am3Group6(void)845 static UINT32 am3Group6(void)
846 {
847 modVal2=OpRead8(modAdd+1);
848 return AMTable3_G6[modVal2>>5]();
849 }
850
851
am3Group7(void)852 static UINT32 am3Group7(void)
853 {
854 return AMTable3_G7[modVal&0x1F]();
855 }
856
857
858
859 static UINT32 (*const AMTable3[2][8])(void) =
860 {
861 {
862 am3Displacement8,
863 am3Displacement16,
864 am3Displacement32,
865 am3RegisterIndirect,
866 am3DisplacementIndirect8,
867 am3DisplacementIndirect16,
868 am3DisplacementIndirect32,
869 am3Group7
870 },
871
872 {
873 am3DoubleDisplacement8,
874 am3DoubleDisplacement16,
875 am3DoubleDisplacement32,
876 am3Register,
877 am3Autoincrement,
878 am3Autodecrement,
879 am3Group6,
880 am3Error1
881 }
882 };
883
884
885
886