1 #ifdef HAVE_OPLL_CORE
2 /*
3 * Copyright (C) 2019 Nuke.YKT
4 *
5 * Redistribution and use of this code or any derivative works are permitted
6 * provided that the following conditions are met:
7 *
8 * - Redistributions may not be sold, nor may they be used in a commercial
9 * product or activity.
10 *
11 * - Redistributions that are modified from the original source must include the
12 * complete source code, including the source code for all components used by a
13 * binary built from the modified sources. However, as a special exception, the
14 * source code distributed need not include anything that is normally distributed
15 * (in either source or binary form) with the major components (compiler, kernel,
16 * and so on) of the operating system on which the executable runs, unless that
17 * component itself accompanies the executable.
18 *
19 * - Redistributions must reproduce the above copyright notice, this list of
20 * conditions and the following disclaimer in the documentation and/or other
21 * materials provided with the distribution.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
33 * POSSIBILITY OF SUCH DAMAGE.
34 *
35 *
36 * Yamaha YM2413 emulator
37 * Thanks:
38 * siliconpr0n.org(digshadow, John McMaster):
39 * VRC VII decap and die shot.
40 *
41 * version: 1.0
42 */
43
44 #include <string.h>
45 #include "opll.h"
46
47 enum {
48 eg_num_attack = 0,
49 eg_num_decay = 1,
50 eg_num_sustain = 2,
51 eg_num_release = 3
52 };
53
54 enum {
55 rm_num_bd0 = 0,
56 rm_num_hh = 1,
57 rm_num_tom = 2,
58 rm_num_bd1 = 3,
59 rm_num_sd = 4,
60 rm_num_tc = 5
61 };
62
63 /* logsin table */
64 static const uint16_t logsinrom[256] = {
65 0x859, 0x6c3, 0x607, 0x58b, 0x52e, 0x4e4, 0x4a6, 0x471,
66 0x443, 0x41a, 0x3f5, 0x3d3, 0x3b5, 0x398, 0x37e, 0x365,
67 0x34e, 0x339, 0x324, 0x311, 0x2ff, 0x2ed, 0x2dc, 0x2cd,
68 0x2bd, 0x2af, 0x2a0, 0x293, 0x286, 0x279, 0x26d, 0x261,
69 0x256, 0x24b, 0x240, 0x236, 0x22c, 0x222, 0x218, 0x20f,
70 0x206, 0x1fd, 0x1f5, 0x1ec, 0x1e4, 0x1dc, 0x1d4, 0x1cd,
71 0x1c5, 0x1be, 0x1b7, 0x1b0, 0x1a9, 0x1a2, 0x19b, 0x195,
72 0x18f, 0x188, 0x182, 0x17c, 0x177, 0x171, 0x16b, 0x166,
73 0x160, 0x15b, 0x155, 0x150, 0x14b, 0x146, 0x141, 0x13c,
74 0x137, 0x133, 0x12e, 0x129, 0x125, 0x121, 0x11c, 0x118,
75 0x114, 0x10f, 0x10b, 0x107, 0x103, 0x0ff, 0x0fb, 0x0f8,
76 0x0f4, 0x0f0, 0x0ec, 0x0e9, 0x0e5, 0x0e2, 0x0de, 0x0db,
77 0x0d7, 0x0d4, 0x0d1, 0x0cd, 0x0ca, 0x0c7, 0x0c4, 0x0c1,
78 0x0be, 0x0bb, 0x0b8, 0x0b5, 0x0b2, 0x0af, 0x0ac, 0x0a9,
79 0x0a7, 0x0a4, 0x0a1, 0x09f, 0x09c, 0x099, 0x097, 0x094,
80 0x092, 0x08f, 0x08d, 0x08a, 0x088, 0x086, 0x083, 0x081,
81 0x07f, 0x07d, 0x07a, 0x078, 0x076, 0x074, 0x072, 0x070,
82 0x06e, 0x06c, 0x06a, 0x068, 0x066, 0x064, 0x062, 0x060,
83 0x05e, 0x05c, 0x05b, 0x059, 0x057, 0x055, 0x053, 0x052,
84 0x050, 0x04e, 0x04d, 0x04b, 0x04a, 0x048, 0x046, 0x045,
85 0x043, 0x042, 0x040, 0x03f, 0x03e, 0x03c, 0x03b, 0x039,
86 0x038, 0x037, 0x035, 0x034, 0x033, 0x031, 0x030, 0x02f,
87 0x02e, 0x02d, 0x02b, 0x02a, 0x029, 0x028, 0x027, 0x026,
88 0x025, 0x024, 0x023, 0x022, 0x021, 0x020, 0x01f, 0x01e,
89 0x01d, 0x01c, 0x01b, 0x01a, 0x019, 0x018, 0x017, 0x017,
90 0x016, 0x015, 0x014, 0x014, 0x013, 0x012, 0x011, 0x011,
91 0x010, 0x00f, 0x00f, 0x00e, 0x00d, 0x00d, 0x00c, 0x00c,
92 0x00b, 0x00a, 0x00a, 0x009, 0x009, 0x008, 0x008, 0x007,
93 0x007, 0x007, 0x006, 0x006, 0x005, 0x005, 0x005, 0x004,
94 0x004, 0x004, 0x003, 0x003, 0x003, 0x002, 0x002, 0x002,
95 0x002, 0x001, 0x001, 0x001, 0x001, 0x001, 0x001, 0x001,
96 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000
97 };
98
99 /* exp table */
100 static const uint16_t exprom[256] = {
101 0x7fa, 0x7f5, 0x7ef, 0x7ea, 0x7e4, 0x7df, 0x7da, 0x7d4,
102 0x7cf, 0x7c9, 0x7c4, 0x7bf, 0x7b9, 0x7b4, 0x7ae, 0x7a9,
103 0x7a4, 0x79f, 0x799, 0x794, 0x78f, 0x78a, 0x784, 0x77f,
104 0x77a, 0x775, 0x770, 0x76a, 0x765, 0x760, 0x75b, 0x756,
105 0x751, 0x74c, 0x747, 0x742, 0x73d, 0x738, 0x733, 0x72e,
106 0x729, 0x724, 0x71f, 0x71a, 0x715, 0x710, 0x70b, 0x706,
107 0x702, 0x6fd, 0x6f8, 0x6f3, 0x6ee, 0x6e9, 0x6e5, 0x6e0,
108 0x6db, 0x6d6, 0x6d2, 0x6cd, 0x6c8, 0x6c4, 0x6bf, 0x6ba,
109 0x6b5, 0x6b1, 0x6ac, 0x6a8, 0x6a3, 0x69e, 0x69a, 0x695,
110 0x691, 0x68c, 0x688, 0x683, 0x67f, 0x67a, 0x676, 0x671,
111 0x66d, 0x668, 0x664, 0x65f, 0x65b, 0x657, 0x652, 0x64e,
112 0x649, 0x645, 0x641, 0x63c, 0x638, 0x634, 0x630, 0x62b,
113 0x627, 0x623, 0x61e, 0x61a, 0x616, 0x612, 0x60e, 0x609,
114 0x605, 0x601, 0x5fd, 0x5f9, 0x5f5, 0x5f0, 0x5ec, 0x5e8,
115 0x5e4, 0x5e0, 0x5dc, 0x5d8, 0x5d4, 0x5d0, 0x5cc, 0x5c8,
116 0x5c4, 0x5c0, 0x5bc, 0x5b8, 0x5b4, 0x5b0, 0x5ac, 0x5a8,
117 0x5a4, 0x5a0, 0x59c, 0x599, 0x595, 0x591, 0x58d, 0x589,
118 0x585, 0x581, 0x57e, 0x57a, 0x576, 0x572, 0x56f, 0x56b,
119 0x567, 0x563, 0x560, 0x55c, 0x558, 0x554, 0x551, 0x54d,
120 0x549, 0x546, 0x542, 0x53e, 0x53b, 0x537, 0x534, 0x530,
121 0x52c, 0x529, 0x525, 0x522, 0x51e, 0x51b, 0x517, 0x514,
122 0x510, 0x50c, 0x509, 0x506, 0x502, 0x4ff, 0x4fb, 0x4f8,
123 0x4f4, 0x4f1, 0x4ed, 0x4ea, 0x4e7, 0x4e3, 0x4e0, 0x4dc,
124 0x4d9, 0x4d6, 0x4d2, 0x4cf, 0x4cc, 0x4c8, 0x4c5, 0x4c2,
125 0x4be, 0x4bb, 0x4b8, 0x4b5, 0x4b1, 0x4ae, 0x4ab, 0x4a8,
126 0x4a4, 0x4a1, 0x49e, 0x49b, 0x498, 0x494, 0x491, 0x48e,
127 0x48b, 0x488, 0x485, 0x482, 0x47e, 0x47b, 0x478, 0x475,
128 0x472, 0x46f, 0x46c, 0x469, 0x466, 0x463, 0x460, 0x45d,
129 0x45a, 0x457, 0x454, 0x451, 0x44e, 0x44b, 0x448, 0x445,
130 0x442, 0x43f, 0x43c, 0x439, 0x436, 0x433, 0x430, 0x42d,
131 0x42a, 0x428, 0x425, 0x422, 0x41f, 0x41c, 0x419, 0x416,
132 0x414, 0x411, 0x40e, 0x40b, 0x408, 0x406, 0x403, 0x400
133 };
134
135 static const opll_patch_t patch_ds1001[opll_patch_max] = {
136 { 0x05, 0x00, 0x00, 0x06,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x01 },{ 0x00, 0x00 },{ 0x03, 0x01 },{ 0x00, 0x00 },{ 0x0e, 0x08 },{ 0x08, 0x01 },{ 0x04, 0x02 },{ 0x02, 0x07 } },
137 { 0x14, 0x00, 0x01, 0x05,{ 0x00, 0x00 },{ 0x00, 0x01 },{ 0x00, 0x00 },{ 0x01, 0x00 },{ 0x03, 0x01 },{ 0x00, 0x00 },{ 0x0d, 0x0f },{ 0x08, 0x06 },{ 0x02, 0x01 },{ 0x03, 0x02 } },
138 { 0x08, 0x00, 0x01, 0x00,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x01, 0x01 },{ 0x01, 0x01 },{ 0x00, 0x00 },{ 0x0f, 0x0b },{ 0x0a, 0x02 },{ 0x02, 0x01 },{ 0x00, 0x02 } },
139 { 0x0c, 0x00, 0x00, 0x07,{ 0x00, 0x00 },{ 0x00, 0x01 },{ 0x01, 0x01 },{ 0x01, 0x00 },{ 0x01, 0x01 },{ 0x00, 0x00 },{ 0x0a, 0x06 },{ 0x08, 0x04 },{ 0x06, 0x02 },{ 0x01, 0x07 } },
140 { 0x1e, 0x00, 0x00, 0x06,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x01, 0x01 },{ 0x01, 0x00 },{ 0x02, 0x01 },{ 0x00, 0x00 },{ 0x0e, 0x07 },{ 0x01, 0x06 },{ 0x00, 0x02 },{ 0x01, 0x08 } },
141 { 0x06, 0x00, 0x00, 0x00,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x02, 0x01 },{ 0x00, 0x00 },{ 0x0a, 0x0e },{ 0x03, 0x02 },{ 0x0f, 0x0f },{ 0x04, 0x04 } },
142 { 0x1d, 0x00, 0x00, 0x07,{ 0x00, 0x00 },{ 0x00, 0x01 },{ 0x01, 0x01 },{ 0x00, 0x00 },{ 0x01, 0x01 },{ 0x00, 0x00 },{ 0x08, 0x08 },{ 0x02, 0x01 },{ 0x01, 0x00 },{ 0x01, 0x07 } },
143 { 0x22, 0x01, 0x00, 0x07,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x01, 0x01 },{ 0x00, 0x00 },{ 0x03, 0x01 },{ 0x00, 0x00 },{ 0x0a, 0x07 },{ 0x02, 0x02 },{ 0x00, 0x01 },{ 0x01, 0x07 } },
144 { 0x25, 0x00, 0x00, 0x00,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x01, 0x00 },{ 0x01, 0x01 },{ 0x05, 0x01 },{ 0x00, 0x00 },{ 0x04, 0x07 },{ 0x00, 0x03 },{ 0x07, 0x00 },{ 0x02, 0x01 } },
145 { 0x0f, 0x00, 0x01, 0x07,{ 0x01, 0x00 },{ 0x00, 0x00 },{ 0x01, 0x00 },{ 0x01, 0x00 },{ 0x05, 0x01 },{ 0x00, 0x00 },{ 0x0a, 0x0a },{ 0x08, 0x05 },{ 0x05, 0x00 },{ 0x01, 0x02 } },
146 { 0x24, 0x00, 0x00, 0x07,{ 0x00, 0x01 },{ 0x00, 0x01 },{ 0x00, 0x00 },{ 0x01, 0x00 },{ 0x07, 0x01 },{ 0x00, 0x00 },{ 0x0f, 0x0f },{ 0x08, 0x08 },{ 0x02, 0x01 },{ 0x02, 0x02 } },
147 { 0x11, 0x00, 0x00, 0x06,{ 0x00, 0x00 },{ 0x01, 0x00 },{ 0x01, 0x01 },{ 0x01, 0x00 },{ 0x01, 0x03 },{ 0x00, 0x00 },{ 0x06, 0x07 },{ 0x05, 0x04 },{ 0x01, 0x01 },{ 0x08, 0x06 } },
148 { 0x13, 0x00, 0x00, 0x05,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x01, 0x02 },{ 0x03, 0x00 },{ 0x0c, 0x09 },{ 0x09, 0x05 },{ 0x00, 0x00 },{ 0x03, 0x02 } },
149 { 0x0c, 0x00, 0x00, 0x00,{ 0x00, 0x00 },{ 0x01, 0x01 },{ 0x01, 0x01 },{ 0x00, 0x00 },{ 0x01, 0x03 },{ 0x00, 0x00 },{ 0x09, 0x0c },{ 0x04, 0x00 },{ 0x03, 0x0f },{ 0x03, 0x06 } },
150 { 0x0d, 0x00, 0x00, 0x00,{ 0x00, 0x00 },{ 0x00, 0x01 },{ 0x01, 0x01 },{ 0x00, 0x01 },{ 0x01, 0x02 },{ 0x00, 0x00 },{ 0x0c, 0x0d },{ 0x01, 0x05 },{ 0x05, 0x00 },{ 0x06, 0x06 } },
151
152 { 0x18, 0x00, 0x01, 0x07,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x01, 0x00 },{ 0x00, 0x00 },{ 0x0d, 0x00 },{ 0x0f, 0x00 },{ 0x06, 0x00 },{ 0x0a, 0x00 } },
153 { 0x00, 0x00, 0x00, 0x00,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x01, 0x00 },{ 0x00, 0x00 },{ 0x0c, 0x00 },{ 0x08, 0x00 },{ 0x0a, 0x00 },{ 0x07, 0x00 } },
154 { 0x00, 0x00, 0x00, 0x00,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x05, 0x00 },{ 0x00, 0x00 },{ 0x0f, 0x00 },{ 0x08, 0x00 },{ 0x05, 0x00 },{ 0x09, 0x00 } },
155 { 0x00, 0x00, 0x00, 0x00,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x01 },{ 0x00, 0x00 },{ 0x00, 0x0f },{ 0x00, 0x08 },{ 0x00, 0x06 },{ 0x00, 0x0d } },
156 { 0x00, 0x00, 0x00, 0x00,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x01 },{ 0x00, 0x00 },{ 0x00, 0x0d },{ 0x00, 0x08 },{ 0x00, 0x06 },{ 0x00, 0x08 } },
157 { 0x00, 0x00, 0x00, 0x00,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x01 },{ 0x00, 0x00 },{ 0x00, 0x0a },{ 0x00, 0x0a },{ 0x00, 0x05 },{ 0x00, 0x05 } }
158 };
159
160 static const opll_patch_t patch_ym2413[opll_patch_max] = {
161 { 0x1e, 0x01, 0x00, 0x07,{ 0x00, 0x00 },{ 0x01, 0x01 },{ 0x01, 0x01 },{ 0x01, 0x00 },{ 0x01, 0x01 },{ 0x00, 0x00 },{ 0x0d, 0x07 },{ 0x00, 0x08 },{ 0x00, 0x01 },{ 0x00, 0x07 } },
162 { 0x1a, 0x00, 0x01, 0x05,{ 0x00, 0x00 },{ 0x00, 0x01 },{ 0x00, 0x00 },{ 0x01, 0x00 },{ 0x03, 0x01 },{ 0x00, 0x00 },{ 0x0d, 0x0f },{ 0x08, 0x07 },{ 0x02, 0x01 },{ 0x03, 0x03 } },
163 { 0x19, 0x00, 0x00, 0x00,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x01, 0x00 },{ 0x03, 0x01 },{ 0x02, 0x00 },{ 0x0f, 0x0c },{ 0x02, 0x04 },{ 0x01, 0x02 },{ 0x01, 0x03 } },
164 { 0x0e, 0x00, 0x00, 0x07,{ 0x00, 0x00 },{ 0x00, 0x01 },{ 0x01, 0x01 },{ 0x01, 0x00 },{ 0x01, 0x01 },{ 0x00, 0x00 },{ 0x0a, 0x06 },{ 0x08, 0x04 },{ 0x07, 0x02 },{ 0x00, 0x07 } },
165 { 0x1e, 0x00, 0x00, 0x06,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x01, 0x01 },{ 0x01, 0x00 },{ 0x02, 0x01 },{ 0x00, 0x00 },{ 0x0e, 0x07 },{ 0x00, 0x06 },{ 0x00, 0x02 },{ 0x00, 0x08 } },
166 { 0x16, 0x00, 0x00, 0x05,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x01, 0x01 },{ 0x01, 0x00 },{ 0x01, 0x02 },{ 0x00, 0x00 },{ 0x0e, 0x07 },{ 0x00, 0x01 },{ 0x00, 0x01 },{ 0x00, 0x08 } },
167 { 0x1d, 0x00, 0x00, 0x07,{ 0x00, 0x00 },{ 0x00, 0x01 },{ 0x01, 0x01 },{ 0x00, 0x00 },{ 0x01, 0x01 },{ 0x00, 0x00 },{ 0x08, 0x08 },{ 0x02, 0x01 },{ 0x01, 0x00 },{ 0x00, 0x07 } },
168 { 0x2d, 0x01, 0x00, 0x04,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x01, 0x01 },{ 0x00, 0x00 },{ 0x03, 0x01 },{ 0x00, 0x00 },{ 0x0a, 0x07 },{ 0x02, 0x02 },{ 0x00, 0x00 },{ 0x00, 0x07 } },
169 { 0x1b, 0x00, 0x00, 0x06,{ 0x00, 0x00 },{ 0x01, 0x01 },{ 0x01, 0x01 },{ 0x00, 0x00 },{ 0x01, 0x01 },{ 0x00, 0x00 },{ 0x06, 0x06 },{ 0x04, 0x05 },{ 0x01, 0x01 },{ 0x00, 0x07 } },
170 { 0x0b, 0x01, 0x01, 0x00,{ 0x00, 0x00 },{ 0x01, 0x01 },{ 0x00, 0x01 },{ 0x00, 0x00 },{ 0x01, 0x01 },{ 0x00, 0x00 },{ 0x08, 0x0f },{ 0x05, 0x07 },{ 0x07, 0x00 },{ 0x01, 0x07 } },
171 { 0x03, 0x01, 0x00, 0x01,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x01, 0x00 },{ 0x03, 0x01 },{ 0x02, 0x00 },{ 0x0f, 0x0e },{ 0x0a, 0x04 },{ 0x01, 0x00 },{ 0x00, 0x04 } },
172 { 0x24, 0x00, 0x00, 0x07,{ 0x00, 0x01 },{ 0x00, 0x01 },{ 0x00, 0x00 },{ 0x01, 0x00 },{ 0x07, 0x01 },{ 0x00, 0x00 },{ 0x0f, 0x0f },{ 0x08, 0x08 },{ 0x02, 0x01 },{ 0x02, 0x02 } },
173 { 0x0c, 0x00, 0x00, 0x05,{ 0x00, 0x00 },{ 0x01, 0x01 },{ 0x01, 0x00 },{ 0x00, 0x01 },{ 0x01, 0x00 },{ 0x00, 0x00 },{ 0x0c, 0x0f },{ 0x02, 0x05 },{ 0x02, 0x04 },{ 0x00, 0x02 } },
174 { 0x15, 0x00, 0x00, 0x03,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x01, 0x01 },{ 0x01, 0x00 },{ 0x0c, 0x09 },{ 0x09, 0x05 },{ 0x00, 0x00 },{ 0x03, 0x02 } },
175 { 0x09, 0x00, 0x00, 0x03,{ 0x00, 0x00 },{ 0x01, 0x01 },{ 0x01, 0x00 },{ 0x00, 0x00 },{ 0x01, 0x01 },{ 0x02, 0x00 },{ 0x0f, 0x0e },{ 0x01, 0x04 },{ 0x04, 0x01 },{ 0x00, 0x03 } },
176
177 { 0x18, 0x00, 0x01, 0x07,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x01, 0x00 },{ 0x00, 0x00 },{ 0x0d, 0x00 },{ 0x0f, 0x00 },{ 0x06, 0x00 },{ 0x0a, 0x00 } },
178 { 0x00, 0x00, 0x00, 0x00,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x01, 0x00 },{ 0x00, 0x00 },{ 0x0c, 0x00 },{ 0x08, 0x00 },{ 0x0a, 0x00 },{ 0x07, 0x00 } },
179 { 0x00, 0x00, 0x00, 0x00,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x05, 0x00 },{ 0x00, 0x00 },{ 0x0f, 0x00 },{ 0x08, 0x00 },{ 0x05, 0x00 },{ 0x09, 0x00 } },
180 { 0x00, 0x00, 0x00, 0x00,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x01 },{ 0x00, 0x00 },{ 0x00, 0x0f },{ 0x00, 0x08 },{ 0x00, 0x06 },{ 0x00, 0x0d } },
181 { 0x00, 0x00, 0x00, 0x00,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x01 },{ 0x00, 0x00 },{ 0x00, 0x0d },{ 0x00, 0x08 },{ 0x00, 0x04 },{ 0x00, 0x08 } },
182 { 0x00, 0x00, 0x00, 0x00,{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x00 },{ 0x00, 0x01 },{ 0x00, 0x00 },{ 0x00, 0x0a },{ 0x00, 0x0a },{ 0x00, 0x05 },{ 0x00, 0x05 } }
183 };
184
185 static const uint32_t ch_offset[18] = {
186 1, 2, 0, 1, 2, 3, 4, 5, 3, 4, 5, 6, 7, 8, 6, 7, 8, 0
187 };
188
189 static const uint32_t pg_multi[16] = {
190 1, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 20, 24, 24, 30, 30
191 };
192
193 static const uint32_t eg_stephi[4][4] = {
194 { 0, 0, 0, 0 },
195 { 1, 0, 0, 0 },
196 { 1, 0, 1, 0 },
197 { 1, 1, 1, 0 }
198 };
199
200 static const uint32_t eg_ksltable[16] = {
201 0, 32, 40, 45, 48, 51, 53, 55, 56, 58, 59, 60, 61, 62, 63, 64
202 };
203
OPLL_DoIO(opll_t * chip)204 void OPLL_DoIO(opll_t *chip) {
205 /* Write signal check */
206 chip->write_a_en = (chip->write_a & 0x03) == 0x01;
207 chip->write_d_en = (chip->write_d & 0x03) == 0x01;
208 chip->write_a <<= 1;
209 chip->write_d <<= 1;
210 }
211
OPLL_DoModeWrite(opll_t * chip)212 void OPLL_DoModeWrite(opll_t *chip) {
213 uint8_t slot;
214 if ((chip->write_mode_address & 0x10) && chip->write_d_en) {
215 slot = chip->write_mode_address & 0x01;
216 switch (chip->write_mode_address & 0x0f) {
217 case 0x00:
218 case 0x01:
219 chip->patch.multi[slot] = chip->write_data & 0x0f;
220 chip->patch.ksr[slot] = (chip->write_data >> 4) & 0x01;
221 chip->patch.et[slot] = (chip->write_data >> 5) & 0x01;
222 chip->patch.vib[slot] = (chip->write_data >> 6) & 0x01;
223 chip->patch.am[slot] = (chip->write_data >> 7) & 0x01;
224 break;
225
226 case 0x02:
227 chip->patch.ksl[0] = (chip->write_data >> 6) & 0x03;
228 chip->patch.tl = chip->write_data & 0x3f;
229 break;
230
231 case 0x03:
232 chip->patch.ksl[1] = (chip->write_data >> 6) & 0x03;
233 chip->patch.dc = (chip->write_data >> 4) & 0x01;
234 chip->patch.dm = (chip->write_data >> 3) & 0x01;
235 chip->patch.fb = chip->write_data & 0x07;
236 break;
237
238 case 0x04:
239 case 0x05:
240 chip->patch.dr[slot] = chip->write_data & 0x0f;
241 chip->patch.ar[slot] = (chip->write_data >> 4) & 0x0f;
242 break;
243
244 case 0x06:
245 case 0x07:
246 chip->patch.rr[slot] = chip->write_data & 0x0f;
247 chip->patch.sl[slot] = (chip->write_data >> 4) & 0x0f;
248 break;
249
250 case 0x0e:
251 chip->rhythm = chip->write_data & 0x3f;
252 if (chip->chip_type == opll_type_ds1001) {
253 chip->rhythm |= 0x20;
254 }
255 chip->rm_enable = (chip->rm_enable & 0x7f) | ((chip->rhythm << 2) & 0x80);
256 break;
257
258 case 0x0f:
259 chip->testmode = chip->write_data & 0x0f;
260 break;
261 }
262 }
263 }
264
OPLL_Reset(opll_t * chip,uint32_t chip_type)265 void OPLL_Reset(opll_t *chip, uint32_t chip_type) {
266 uint32_t i;
267 memset(chip, 0, sizeof(opll_t));
268 chip->chip_type = chip_type;
269 if (chip_type == opll_type_ds1001) {
270 /* Rhythm mode is always on */
271 chip->rhythm = 0x20;
272 chip->rm_enable = (int8_t)0x80;
273 }
274 switch (chip_type) {
275 case opll_type_ds1001:
276 chip->patchrom = patch_ds1001;
277 break;
278 case opll_type_ym2413:
279 case opll_type_ym2413b:
280 default:
281 chip->patchrom = patch_ym2413;
282 break;
283 }
284 for (i = 0; i < 18; i++) {
285 chip->eg_state[i] = eg_num_release;
286 chip->eg_level[i] = 0x7f;
287 chip->eg_out = 0x7f;
288 }
289 chip->rm_select = rm_num_tc + 1;
290 }
291
OPLL_DoRegWrite(opll_t * chip)292 void OPLL_DoRegWrite(opll_t *chip) {
293 uint32_t channel;
294
295 /* Address */
296 if (chip->write_a_en) {
297 if ((chip->write_data & 0xc0) == 0x00) {
298 /* FM Write */
299 chip->write_fm_address = 1;
300 chip->address = chip->write_data;
301 } else {
302 chip->write_fm_address = 0;
303 }
304 }
305 /* Data */
306 if (chip->write_fm_address && chip->write_d_en) {
307 chip->data = chip->write_data;
308 }
309
310 /* Update registers */
311 if (chip->write_fm_data && !chip->write_a_en) {
312 if ((chip->address & 0x0f) == chip->cycles && chip->cycles < 16) {
313 channel = chip->cycles % 9;
314 switch (chip->address & 0xf0) {
315 case 0x10:
316 chip->fnum[channel] = (chip->fnum[channel] & 0x100) | chip->data;
317 break;
318 case 0x20:
319 chip->fnum[channel] = (chip->fnum[channel] & 0xff) | ((chip->data & 0x01) << 8);
320 chip->block[channel] = (chip->data >> 1) & 0x07;
321 chip->kon[channel] = (chip->data >> 4) & 0x01;
322 chip->son[channel] = (chip->data >> 5) & 0x01;
323 break;
324 case 0x30:
325 chip->vol[channel] = chip->data & 0x0f;
326 chip->inst[channel] = (chip->data >> 4) & 0x0f;
327 break;
328 }
329 }
330 }
331
332
333 if (chip->write_a_en) {
334 chip->write_fm_data = 0;
335 }
336 if (chip->write_fm_address && chip->write_d_en) {
337 chip->write_fm_data = 1;
338 }
339 if (chip->write_a_en) {
340 if (((chip->write_data & 0xf0) == 0x00)) {
341 chip->write_mode_address = 0x10 | (chip->write_data & 0x0f);
342 } else {
343 chip->write_mode_address = 0x00;
344 }
345 }
346
347 }
OPLL_PreparePatch1(opll_t * chip)348 void OPLL_PreparePatch1(opll_t *chip) {
349 uint8_t instr;
350 uint32_t mcsel = ((chip->cycles + 1) / 3) & 0x01;
351 uint32_t instr_index;
352 uint32_t ch = ch_offset[chip->cycles];
353 const opll_patch_t *patch;
354 instr = chip->inst[ch];
355 if (instr > 0) {
356 instr_index = opll_patch_1 + instr - 1;
357 }
358 if (chip->rm_select <= rm_num_tc) {
359 instr_index = opll_patch_drum_0 + chip->rm_select;
360 }
361 if (chip->rm_select <= rm_num_tc || instr > 0) {
362 patch = &chip->patchrom[instr_index];
363 } else {
364 patch = &chip->patch;
365 }
366 if (chip->rm_select == rm_num_hh || chip->rm_select == rm_num_tom) {
367 chip->c_tl = chip->inst[ch] << 2;
368 } else if (mcsel == 1) {
369 chip->c_tl = chip->vol[ch] << 2;
370 } else {
371 chip->c_tl = patch->tl;
372 }
373
374 chip->c_adrr[0] = patch->ar[mcsel];
375 chip->c_adrr[1] = patch->dr[mcsel];
376 chip->c_adrr[2] = patch->rr[mcsel];
377 chip->c_et = patch->et[mcsel];
378 chip->c_ksr = patch->ksr[mcsel];
379 chip->c_ksl = patch->ksl[mcsel];
380 chip->c_ksr_freq = (chip->block[ch] << 1) | (chip->fnum[ch] >> 8);
381 chip->c_ksl_freq = (chip->fnum[ch]>>5);
382 chip->c_ksl_block = (chip->block[ch]);
383 }
384
OPLL_PreparePatch2(opll_t * chip)385 void OPLL_PreparePatch2(opll_t *chip) {
386 uint8_t instr;
387 uint32_t mcsel = ((chip->cycles + 1) / 3) & 0x01;
388 uint32_t instr_index;
389 const opll_patch_t *patch;
390 instr = chip->inst[ch_offset[chip->cycles]];
391 if (instr > 0) {
392 instr_index = opll_patch_1 + instr - 1;
393 }
394 if (chip->rm_select <= rm_num_tc) {
395 instr_index = opll_patch_drum_0 + chip->rm_select;
396 }
397 if (chip->rm_select <= rm_num_tc || instr > 0) {
398 patch = &chip->patchrom[instr_index];
399 } else {
400 patch = &chip->patch;
401 }
402
403 chip->c_fnum = chip->fnum[ch_offset[chip->cycles]];
404 chip->c_block = chip->block[ch_offset[chip->cycles]];
405
406 chip->c_multi = patch->multi[mcsel];
407 chip->c_sl = patch->sl[mcsel];
408 chip->c_fb = patch->fb;
409 chip->c_vib = patch->vib[mcsel];
410 chip->c_am = patch->am[mcsel];
411 chip->c_dc <<= 1;
412 chip->c_dm <<= 1;
413 chip->c_dc |= patch->dc;
414 chip->c_dm |= patch->dm;
415 }
416
OPLL_PhaseGenerate(opll_t * chip)417 void OPLL_PhaseGenerate(opll_t *chip) {
418 uint32_t ismod;
419 uint32_t phase;
420 uint8_t rm_bit;
421 uint16_t pg_out;
422
423 chip->pg_phase[(chip->cycles + 17) % 18] = chip->pg_phase_next + chip->pg_inc;
424
425 if ((chip->rm_enable & 0x40) && (chip->cycles == 13 || chip->cycles == 14)) {
426 ismod = 0;
427 } else {
428 ismod = ((chip->cycles + 3) / 3) & 1;
429 }
430 phase = chip->pg_phase[chip->cycles];
431 /* KeyOn event check */
432 if ((chip->testmode & 0x04)
433 || (ismod && (chip->eg_dokon & 0x8000)) || (!ismod && (chip->eg_dokon & 0x01))) {
434 chip->pg_phase_next = 0;
435 } else {
436 chip->pg_phase_next = phase;
437 }
438 /* Rhythm mode */
439 if (chip->cycles == 13) {
440 chip->rm_hh_bit2 = (phase >> (2 + 9)) & 1;
441 chip->rm_hh_bit3 = (phase >> (3 + 9)) & 1;
442 chip->rm_hh_bit7 = (phase >> (7 + 9)) & 1;
443 chip->rm_hh_bit8 = (phase >> (8 + 9)) & 1;
444 } else if (chip->cycles == 17 && (chip->rm_enable & 0x80)) {
445 chip->rm_tc_bit3 = (phase >> (3 + 9)) & 1;
446 chip->rm_tc_bit5 = (phase >> (5 + 9)) & 1;
447 }
448 if ((chip->rm_enable & 0x80)) {
449 switch (chip->cycles) {
450 case 13:
451 /* HH */
452 rm_bit = (chip->rm_hh_bit2 ^ chip->rm_hh_bit7)
453 | (chip->rm_hh_bit3 ^ chip->rm_tc_bit5)
454 | (chip->rm_tc_bit3 ^ chip->rm_tc_bit5);
455 pg_out = rm_bit << 9;
456 if (rm_bit ^ (chip->rm_noise & 1)) {
457 pg_out |= 0xd0;
458 } else {
459 pg_out |= 0x34;
460 }
461 break;
462 case 16:
463 /* SD */
464 pg_out = (chip->rm_hh_bit8 << 9)
465 | ((chip->rm_hh_bit8 ^ (chip->rm_noise & 1)) << 8);
466 break;
467 case 17:
468 /* TC */
469 rm_bit = (chip->rm_hh_bit2 ^ chip->rm_hh_bit7)
470 | (chip->rm_hh_bit3 ^ chip->rm_tc_bit5)
471 | (chip->rm_tc_bit3 ^ chip->rm_tc_bit5);
472 pg_out = (rm_bit << 9) | 0x100;
473 break;
474 default:
475 pg_out = phase >> 9;
476 }
477 } else {
478 pg_out = phase >> 9;
479 }
480 chip->pg_out = pg_out;
481 }
482
OPLL_PhaseCalcIncrement(opll_t * chip)483 void OPLL_PhaseCalcIncrement(opll_t *chip) {
484 uint32_t freq;
485 uint16_t block;
486 freq = chip->c_fnum << 1;
487 block = chip->c_block;
488 /* Apply vibrato */
489 if (chip->c_vib) {
490 switch (chip->lfo_vib_counter) {
491 case 0:
492 case 4:
493 break;
494 case 1:
495 case 3:
496 freq += freq >> 8;
497 break;
498 case 2:
499 freq += freq >> 7;
500 break;
501 case 5:
502 case 7:
503 freq -= freq >> 8;
504 break;
505 case 6:
506 freq -= freq >> 7;
507 break;
508 }
509 }
510 /* Apply block */
511 freq = (freq << block) >> 1;
512
513 chip->pg_inc = (freq * pg_multi[chip->c_multi]) >> 1;
514 }
515
OPLL_EnvelopeKSLTL(opll_t * chip)516 void OPLL_EnvelopeKSLTL(opll_t *chip)
517 {
518 int32_t ksl;
519
520 ksl = eg_ksltable[chip->c_ksl_freq]-((8-chip->c_ksl_block)<<3);
521 if (ksl < 0) {
522 ksl = 0;
523 }
524
525 ksl <<= 1;
526
527 if (chip->c_ksl) {
528 ksl = ksl >> (3-chip->c_ksl);
529 } else {
530 ksl = 0;
531 }
532
533 chip->eg_ksltl = ksl + (chip->c_tl<<1);
534 }
535
OPLL_EnvelopeOutput(opll_t * chip)536 void OPLL_EnvelopeOutput(opll_t *chip)
537 {
538 int32_t level = chip->eg_level[(chip->cycles+17)%18];
539
540 level += chip->eg_ksltl;
541
542 if (chip->c_am) {
543 level += chip->lfo_am_out;
544 }
545
546 if (level >= 128) {
547 level = 127;
548 }
549
550 if (chip->testmode & 0x01) {
551 level = 0;
552 }
553
554 chip->eg_out = level;
555 }
556
OPLL_EnvelopeGenerate(opll_t * chip)557 void OPLL_EnvelopeGenerate(opll_t *chip) {
558 uint8_t timer_inc;
559 uint8_t timer_bit;
560 uint8_t timer_low;
561 uint8_t rate;
562 uint8_t state_rate;
563 uint8_t ksr;
564 uint8_t sum;
565 uint8_t rate_hi;
566 uint8_t rate_lo;
567 int32_t level;
568 int32_t next_level;
569 uint8_t zero;
570 uint8_t state;
571 uint8_t next_state;
572 int32_t step;
573 int32_t sl;
574 uint32_t mcsel = ((chip->cycles + 1) / 3) & 0x01;
575
576
577 /* EG timer */
578 if ((chip->eg_counter_state & 3) != 3) {
579 timer_inc = 0;
580 } else if (chip->cycles == 0) {
581 timer_inc = 1;
582 } else {
583 timer_inc = chip->eg_timer_carry;
584 }
585 timer_low = chip->eg_timer & 3;
586 timer_bit = chip->eg_timer & 1;
587 timer_bit += timer_inc;
588 chip->eg_timer_carry = timer_bit >> 1;
589 chip->eg_timer = ((timer_bit & 1) << 17) | (chip->eg_timer >> 1);
590 if (chip->testmode & 0x08) {
591 chip->eg_timer &= 0x2ffff;
592 chip->eg_timer |= (chip->write_data << (16 - 2)) & 0x10000;
593 }
594 if (!chip->eg_timer_shift_stop && ((chip->eg_timer >> 16) & 1)) {
595 chip->eg_timer_shift = chip->cycles;
596 }
597 if (chip->cycles == 0 && (chip->eg_counter_state_prev & 1) == 1) {
598 chip->eg_timer_low_lock = timer_low;
599 chip->eg_timer_shift_lock = chip->eg_timer_shift;
600 if (chip->eg_timer_shift_lock > 13)
601 chip->eg_timer_shift_lock = 0;
602
603 chip->eg_timer_shift = 0;
604 }
605 chip->eg_timer_shift_stop |= (chip->eg_timer >> 16) & 1;
606 if (chip->cycles == 0) {
607 chip->eg_timer_shift_stop = 0;
608 }
609 chip->eg_counter_state_prev = chip->eg_counter_state;
610 if (chip->cycles == 17) {
611 chip->eg_counter_state++;
612 }
613
614 level = chip->eg_level[(chip->cycles+16)%18];
615 next_level = level;
616 zero = level == 0;
617 chip->eg_silent = level == 0x7f;
618
619 if (chip->eg_state[(chip->cycles+16)%18] != eg_num_attack && (chip->eg_off&2) && !(chip->eg_dokon&2)) {
620 next_level = 0x7f;
621 }
622
623 if (chip->eg_maxrate && (chip->eg_dokon&2)) {
624 next_level = 0x00;
625 }
626
627
628 state = chip->eg_state[(chip->cycles+16)%18];
629 next_state = eg_num_attack;
630
631 step = 0;
632 sl = chip->eg_sl;
633
634 switch (state) {
635 case eg_num_attack:
636 if (!chip->eg_maxrate && (chip->eg_kon & 2) && !zero) {
637 int32_t shift = chip->eg_rate_hi - 11 + chip->eg_inc_hi;
638 if (chip->eg_inc_lo) {
639 shift = 1;
640 }
641 if (shift > 0) {
642 if (shift > 4)
643 shift = 4;
644 step = ~level >> (5 - shift);
645 }
646 }
647 if (zero) {
648 next_state = eg_num_decay;
649 } else {
650 next_state = eg_num_attack;
651 }
652 break;
653 case eg_num_decay:
654 if (!(chip->eg_off & 2) && !(chip->eg_dokon & 2) && (level >> 3) != sl)
655 {
656 uint8_t i0 = chip->eg_rate_hi == 15 || (chip->eg_rate_hi == 14 && chip->eg_inc_hi);
657 uint8_t i1 = (chip->eg_rate_hi == 14 && !chip->eg_inc_hi) || (chip->eg_rate_hi == 13 && chip->eg_inc_hi) ||
658 (chip->eg_rate_hi == 13 && !chip->eg_inc_hi && (chip->eg_counter_state_prev & 1))
659 || (chip->eg_rate_hi == 12 && chip->eg_inc_hi && (chip->eg_counter_state_prev & 1))
660 || (chip->eg_rate_hi == 12 && !chip->eg_inc_hi && ((chip->eg_counter_state_prev & 3) == 3))
661 || (chip->eg_inc_lo && ((chip->eg_counter_state_prev & 3) == 3));
662 step = (i0<<1) | i1;
663 }
664 if ((level >> 3) == sl) {
665 next_state = eg_num_sustain;
666 } else {
667 next_state = eg_num_decay;
668 }
669 break;
670 case eg_num_sustain:
671 case eg_num_release:
672 if (!(chip->eg_off & 2) && !(chip->eg_dokon & 2))
673 {
674 uint8_t i0 = chip->eg_rate_hi == 15 || (chip->eg_rate_hi == 14 && chip->eg_inc_hi);
675 uint8_t i1 = (chip->eg_rate_hi == 14 && !chip->eg_inc_hi) || (chip->eg_rate_hi == 13 && chip->eg_inc_hi) ||
676 (chip->eg_rate_hi == 13 && !chip->eg_inc_hi && (chip->eg_counter_state_prev & 1))
677 || (chip->eg_rate_hi == 12 && chip->eg_inc_hi && (chip->eg_counter_state_prev & 1))
678 || (chip->eg_rate_hi == 12 && !chip->eg_inc_hi && ((chip->eg_counter_state_prev & 3) == 3))
679 || (chip->eg_inc_lo && ((chip->eg_counter_state_prev & 3) == 3));
680 step = (i0<<1) | i1;
681 }
682 next_state = state;
683 break;
684 }
685
686 if (!(chip->eg_kon & 2)) {
687 next_state = eg_num_release;
688 }
689 if (chip->eg_dokon & 2) {
690 next_state = eg_num_attack;
691 }
692
693 chip->eg_level[(chip->cycles+16)%18] = next_level+step;
694 chip->eg_state[(chip->cycles+16)%18] = next_state;
695
696 rate_hi = chip->eg_rate >> 2;
697 rate_lo = chip->eg_rate & 3;
698 chip->eg_inc_hi = eg_stephi[rate_lo][chip->eg_timer_low_lock];
699 sum = (chip->eg_timer_shift_lock + rate_hi) & 0x0f;
700 chip->eg_inc_lo = 0;
701 if (rate_hi < 12 && !chip->eg_zerorate) {
702 switch (sum) {
703 case 12:
704 chip->eg_inc_lo = 1;
705 break;
706 case 13:
707 chip->eg_inc_lo = (rate_lo >> 1) & 1;
708 break;
709 case 14:
710 chip->eg_inc_lo = rate_lo & 1;
711 break;
712 }
713 }
714 chip->eg_maxrate = rate_hi == 0x0f;
715
716 chip->eg_rate_hi = rate_hi;
717
718 chip->eg_kon <<= 1;
719 chip->eg_kon |= chip->kon[ch_offset[chip->cycles]];
720 chip->eg_off <<= 1;
721 chip->eg_off |= (chip->eg_level[chip->cycles] >> 2) == 0x1f;
722 switch (chip->rm_select) {
723 case rm_num_bd0:
724 case rm_num_bd1:
725 chip->eg_kon |= (chip->rhythm >> 4) & 1;
726 break;
727 case rm_num_sd:
728 chip->eg_kon |= (chip->rhythm >> 3) & 1;
729 break;
730 case rm_num_tom:
731 chip->eg_kon |= (chip->rhythm >> 2) & 1;
732 break;
733 case rm_num_tc:
734 chip->eg_kon |= (chip->rhythm >> 1) & 1;
735 break;
736 case rm_num_hh:
737 chip->eg_kon |= chip->rhythm & 1;
738 break;
739 }
740
741 /* Calculate rate */
742 rate = 0;
743 chip->eg_dokon <<= 1;
744 state_rate = chip->eg_state[chip->cycles];
745 if (state_rate == eg_num_release && (chip->eg_kon&1) && (chip->eg_off&1)) {
746 state_rate = eg_num_attack;
747 chip->eg_dokon |= 1;
748 }
749 switch (state_rate) {
750 case eg_num_attack:
751 rate = chip->c_adrr[0];
752 break;
753 case eg_num_decay:
754 rate = chip->c_adrr[1];
755 break;
756 case eg_num_sustain:
757 if (!chip->c_et) {
758 rate = chip->c_adrr[2];
759 }
760 break;
761 case eg_num_release:
762 if (chip->son[ch_offset[chip->cycles]]) {
763 rate = 5;
764 } else {
765 rate = chip->c_adrr[2];
766 }
767 break;
768 }
769 if (!(chip->eg_kon&1) && !mcsel && chip->rm_select != rm_num_tom && chip->rm_select != rm_num_hh) {
770 rate = 0;
771 }
772 if ((chip->eg_kon&1) && chip->eg_state[chip->cycles] == eg_num_release && !(chip->eg_off&1)) {
773 rate = 12;
774 }
775 if (!(chip->eg_kon&1) && !chip->son[ch_offset[chip->cycles]] && mcsel == 1 && !chip->c_et) {
776 rate = 7;
777 }
778 chip->eg_zerorate = rate == 0;
779 ksr = chip->c_ksr_freq;
780 if (!chip->c_ksr)
781 ksr >>= 2;
782 chip->eg_rate = (rate << 2) + ksr;
783 if (chip->eg_rate & 0x40) {
784 chip->eg_rate = 0x3c | (ksr & 3);
785 }
786 chip->eg_sl = chip->c_sl;
787 }
788
OPLL_Channel(opll_t * chip)789 void OPLL_Channel(opll_t *chip) {
790 int16_t sign;
791 int16_t ch_out = chip->ch_out;
792 uint8_t ismod = (chip->cycles / 3) & 1;
793 uint8_t mute_m = ismod || ((chip->rm_enable&0x40) && (chip->cycles+15)%18 >= 12);
794 uint8_t mute_r = 1;
795 if (chip->chip_type == opll_type_ds1001) {
796 chip->output_m = ch_out;
797 if (chip->output_m >= 0) {
798 chip->output_m++;
799 }
800 if (mute_m) {
801 chip->output_m = 0;
802 }
803 chip->output_r = 0;
804 return;
805 } else {
806 /* TODO: This might be incorrect */
807 if ((chip->rm_enable & 0x40)) {
808 switch (chip->cycles) {
809 case 16: /* HH */
810 case 17: /* TOM */
811 case 0: /* BD */
812 case 1: /* SD */
813 case 2: /* TC */
814 case 3: /* HH */
815 case 4: /* TOM */
816 case 5: /* BD */
817 case 9: /* TOM */
818 case 10: /* TOM */
819 mute_r = 0;
820 break;
821 }
822 }
823 if (chip->chip_type == opll_type_ym2413b) {
824 if (mute_m)
825 chip->output_m = 0;
826 else
827 chip->output_m = ch_out;
828 if (mute_r)
829 chip->output_r = 0;
830 else
831 chip->output_r = ch_out;
832 } else {
833 sign = ch_out >> 8;
834 if (ch_out >= 0) {
835 ch_out++;
836 sign++;
837 }
838 if (mute_m)
839 chip->output_m = sign;
840 else
841 chip->output_m = ch_out;
842 if (mute_r)
843 chip->output_r = sign;
844 else
845 chip->output_r = ch_out;
846 }
847 }
848 }
849
OPLL_Operator(opll_t * chip)850 void OPLL_Operator(opll_t *chip) {
851 uint8_t ismod1, ismod2, ismod3;
852 uint32_t op_mod;
853 uint16_t exp_shift;
854 int16_t output;
855 uint32_t level;
856 uint32_t phase;
857 int16_t routput;
858 if ((chip->rm_enable & 0x80) && (chip->cycles == 15 || chip->cycles == 16)) {
859 ismod1 = 0;
860 } else {
861 ismod1 = ((chip->cycles + 1) / 3) & 1;
862 }
863 if ((chip->rm_enable & 0x40) && (chip->cycles == 13 || chip->cycles == 14)) {
864 ismod2 = 0;
865 } else {
866 ismod2 = ((chip->cycles + 3) / 3) & 1;
867 }
868 if ((chip->rm_enable & 0x40) && (chip->cycles == 16 || chip->cycles == 17)) {
869 ismod3 = 0;
870 } else {
871 ismod3 = (chip->cycles / 3) & 1;
872 }
873
874 op_mod = 0;
875
876 if (ismod3) {
877 op_mod |= chip->op_mod << 1;
878 }
879
880 if (ismod2 && chip->c_fb) {
881 op_mod |= chip->op_fbsum >> (7 - chip->c_fb);
882 }
883
884 exp_shift = chip->op_exp_s;
885 if (chip->eg_silent || ((chip->op_neg&2) && (ismod1 ? (chip->c_dm&4) : (chip->c_dc&4)))) {
886 exp_shift |= 12;
887 }
888
889 output = chip->op_exp_m>>exp_shift;
890 if (!chip->eg_silent && (chip->op_neg&2)) {
891 output = ~output;
892 }
893
894 level = chip->op_logsin+(chip->eg_out<<4);
895 if (level >= 4096) {
896 level = 4095;
897 }
898
899 chip->op_exp_m = exprom[level & 0xff];
900 chip->op_exp_s = level >> 8;
901
902 phase = (op_mod + chip->pg_out) & 0x3ff;
903 if (phase & 0x100) {
904 phase ^= 0xff;
905 }
906 chip->op_logsin = logsinrom[phase & 0xff];
907 chip->op_neg <<= 1;
908 chip->op_neg |= phase >> 9;
909 chip->op_fbsum = (chip->op_fb1[(chip->cycles + 3) % 9] + chip->op_fb2[(chip->cycles + 3) % 9]) >> 1;
910
911 if (ismod1) {
912 chip->op_fb2[chip->cycles%9] = chip->op_fb1[chip->cycles%9];
913 chip->op_fb1[chip->cycles%9] = output;
914 }
915 chip->op_mod = output&0x1ff;
916
917 if (chip->chip_type == opll_type_ds1001) {
918 routput = 0;
919 } else {
920 switch (chip->cycles) {
921 case 2:
922 routput = chip->ch_out_hh;
923 break;
924 case 3:
925 routput = chip->ch_out_tm;
926 break;
927 case 4:
928 routput = chip->ch_out_bd;
929 break;
930 case 8:
931 routput = chip->ch_out_sd;
932 break;
933 case 9:
934 routput = chip->ch_out_tc;
935 break;
936 default:
937 routput = 0; /* TODO: Not quite true */
938 break;
939 }
940 switch (chip->cycles) {
941 case 15:
942 chip->ch_out_hh = output>>3;
943 break;
944 case 16:
945 chip->ch_out_tm = output>>3;
946 break;
947 case 17:
948 chip->ch_out_bd = output>>3;
949 break;
950 case 0:
951 chip->ch_out_sd = output>>3;
952 break;
953 case 1:
954 chip->ch_out_tc = output>>3;
955 break;
956 default:
957 break;
958 }
959 }
960
961 chip->ch_out = ismod1 ? routput : (output>>3);
962 }
963
OPLL_DoRhythm(opll_t * chip)964 void OPLL_DoRhythm(opll_t *chip) {
965 uint8_t nbit;
966
967 /* Noise */
968 nbit = (chip->rm_noise ^ (chip->rm_noise >> 14)) & 0x01;
969 nbit |= (chip->rm_noise == 0x00) | ((chip->testmode >> 1) & 0x01);
970 chip->rm_noise = (nbit << 22) | (chip->rm_noise >> 1);
971 }
972
OPLL_DoLFO(opll_t * chip)973 void OPLL_DoLFO(opll_t *chip) {
974 uint8_t vib_step;
975 uint8_t am_inc = 0;
976 uint8_t am_bit;
977
978 /* Update counter */
979 if (chip->cycles == 17) {
980 vib_step = ((chip->lfo_counter & 0x3ff) + 1) >> 10;
981 chip->lfo_am_step = ((chip->lfo_counter & 0x3f) + 1) >> 6;
982 vib_step |= (chip->testmode >> 3) & 0x01;
983 chip->lfo_vib_counter += vib_step;
984 chip->lfo_vib_counter &= 0x07;
985 chip->lfo_counter++;
986 }
987
988 /* LFO AM */
989 if ((chip->lfo_am_step || (chip->testmode & 0x08)) && chip->cycles < 9) {
990 am_inc = chip->lfo_am_dir | (chip->cycles == 0);
991 }
992
993 if (chip->cycles >= 9) {
994 chip->lfo_am_car = 0;
995 }
996
997 if (chip->cycles == 0) {
998 if (chip->lfo_am_dir && (chip->lfo_am_counter & 0x7f) == 0) {
999 chip->lfo_am_dir = 0;
1000 } else if (!chip->lfo_am_dir && (chip->lfo_am_counter & 0x69) == 0x69) {
1001 chip->lfo_am_dir = 1;
1002 }
1003 }
1004
1005 am_bit = chip->lfo_am_counter & 0x01;
1006 am_bit += am_inc + chip->lfo_am_car;
1007 chip->lfo_am_car = am_bit >> 1;
1008 am_bit &= 0x01;
1009 chip->lfo_am_counter = (am_bit << 8) | (chip->lfo_am_counter >> 1);
1010
1011
1012 /* Reset LFO */
1013 if (chip->testmode & 0x02) {
1014 chip->lfo_vib_counter = 0;
1015 chip->lfo_counter = 0;
1016 chip->lfo_am_dir = 0;
1017 chip->lfo_am_counter &= 0xff;
1018 }
1019 }
1020
1021
OPLL_Clock(opll_t * chip,int32_t * buffer)1022 void OPLL_Clock(opll_t *chip, int32_t *buffer) {
1023 buffer[0] = chip->output_m;
1024 buffer[1] = chip->output_r;
1025 if (chip->cycles == 0) {
1026 chip->lfo_am_out = (chip->lfo_am_counter >> 3) & 0x0f;
1027 }
1028 chip->rm_enable >>= 1;
1029 OPLL_DoModeWrite(chip);
1030 chip->rm_select++;
1031 if (chip->rm_select > rm_num_tc) {
1032 chip->rm_select = rm_num_tc + 1;
1033 }
1034 if (chip->cycles == 11 && (chip->rm_enable & 0x80) == 0x80) {
1035 chip->rm_select = rm_num_bd0;
1036 }
1037 OPLL_PreparePatch1(chip);
1038
1039 OPLL_Channel(chip);
1040
1041 OPLL_PhaseGenerate(chip);
1042
1043 OPLL_Operator(chip);
1044
1045 OPLL_PhaseCalcIncrement(chip);
1046
1047 OPLL_EnvelopeOutput(chip);
1048 OPLL_EnvelopeKSLTL(chip);
1049 OPLL_EnvelopeGenerate(chip);
1050
1051 OPLL_DoLFO(chip);
1052 OPLL_DoRhythm(chip);
1053 OPLL_PreparePatch2(chip);
1054 OPLL_DoRegWrite(chip);
1055 OPLL_DoIO(chip);
1056 chip->cycles = (chip->cycles + 1) % 18;
1057
1058 }
1059
1060
OPLL_Write(opll_t * chip,uint32_t port,uint8_t data)1061 void OPLL_Write(opll_t *chip, uint32_t port, uint8_t data) {
1062 chip->write_data = data;
1063 if (port & 1) {
1064 /* Data */
1065 chip->write_d |= 1;
1066 } else {
1067 /* Address */
1068 chip->write_a |= 1;
1069 }
1070 }
1071 #endif
1072