1 /*
2 **
3 ** software implementation of Yamaha FM sound generator (YM2612/YM3438)
4 **
5 ** Original code (MAME fm.c)
6 **
7 ** Copyright (C) 2001, 2002, 2003 Jarek Burczynski (bujar at mame dot net)
8 ** Copyright (C) 1998 Tatsuyuki Satoh , MultiArcadeMachineEmulator development
9 **
10 ** Version 1.4 (final beta)
11 **
12 ** Additional code & fixes by Eke-Eke for Genesis Plus GX
13 **
14 ** Huge thanks to Nemesis, most of those fixes came from his tests on Sega Genesis hardware
15 ** Additional info from YM2612 die shot analysis by Sauraen
16 ** See http://gendev.spritesmind.net/forum/viewtopic.php?t=386
17 **
18 */
19
20 /*
21 ** CHANGELOG:
22 **
23 ** 03-12-2017 Eke-Eke (Genesis Plus GX):
24 ** - improved 9-bit DAC emulation accuracy
25 ** - added discrete YM2612 DAC distortion emulation ("ladder effect")
26 ** - replaced configurable DAC depth with configurable chip types (discrete, integrated or enhanced)
27 **
28 ** 26-09-2017 Eke-Eke (Genesis Plus GX):
29 ** - fixed EG counter loopback behavior (verified on YM3438 die)
30 ** - reverted changes to EG rates 2-7 increment values
31 **
32 ** 09-04-2017 Eke-Eke (Genesis Plus GX):
33 ** - fixed LFO PM implementation: block & keyscale code should not be modified by LFO (verified on YM2612 die)
34 ** - fixed Timer B overflow handling
35 **
36 ** 12-03-2017 Eke-Eke (Genesis Plus GX):
37 ** - fixed Op1 self-feedback regression introduced by previous modifications
38 ** - removed one-sample extra delay on Op1 calculated output
39 ** - refactored chan_calc() function
40 **
41 ** 01-09-2012 Eke-Eke (Genesis Plus GX):
42 ** - removed input clock / output samplerate frequency ratio, chip now always run at (original) internal sample frequency
43 ** - removed now uneeded extra bits of precision
44 **
45 ** 2006~2012 Eke-Eke (Genesis Plus GX):
46 ** - removed unused multichip support
47 ** - added YM2612 Context external access functions
48 ** - fixed LFO implementation:
49 ** .added support for CH3 special mode: fixes various sound effects (birds in Warlock, bug sound in Aladdin...)
50 ** .inverted LFO AM waveform: fixes Spider-Man & Venom : Separation Anxiety (intro), California Games (surfing event)
51 ** .improved LFO timing accuracy: now updated AFTER sample output, like EG/PG updates, and without any precision loss anymore.
52 ** - improved internal timers emulation
53 ** - adjusted lowest EG rates increment values
54 ** - fixed Attack Rate not being updated in some specific cases (Batman & Robin intro)
55 ** - fixed EG behavior when Attack Rate is maximal
56 ** - fixed EG behavior when SL=0 (Mega Turrican tracks 03,09...) or/and Key ON occurs at minimal attenuation
57 ** - implemented EG output immediate changes on register writes
58 ** - fixed YM2612 initial values (after the reset): fixes missing intro in B.O.B
59 ** - implemented Detune overflow (Ariel, Comix Zone, Shaq Fu, Spiderman & many other games using GEMS sound engine)
60 ** - implemented accurate CSM mode emulation
61 ** - implemented accurate SSG-EG emulation (Asterix, Beavis&Butthead, Bubba'n Stix & many other games)
62 ** - implemented accurate address/data ports behavior
63 ** - added preliminar support for DAC precision
64 **
65 ** 03-08-2003 Jarek Burczynski:
66 ** - fixed YM2608 initial values (after the reset)
67 ** - fixed flag and irqmask handling (YM2608)
68 ** - fixed BUFRDY flag handling (YM2608)
69 **
70 ** 14-06-2003 Jarek Burczynski:
71 ** - implemented all of the YM2608 status register flags
72 ** - implemented support for external memory read/write via YM2608
73 ** - implemented support for deltat memory limit register in YM2608 emulation
74 **
75 ** 22-05-2003 Jarek Burczynski:
76 ** - fixed LFO PM calculations (copy&paste bugfix)
77 **
78 ** 08-05-2003 Jarek Burczynski:
79 ** - fixed SSG support
80 **
81 ** 22-04-2003 Jarek Burczynski:
82 ** - implemented 100% correct LFO generator (verified on real YM2610 and YM2608)
83 **
84 ** 15-04-2003 Jarek Burczynski:
85 ** - added support for YM2608's register 0x110 - status mask
86 **
87 ** 01-12-2002 Jarek Burczynski:
88 ** - fixed register addressing in YM2608, YM2610, YM2610B chips. (verified on real YM2608)
89 ** The addressing patch used for early Neo-Geo games can be removed now.
90 **
91 ** 26-11-2002 Jarek Burczynski, Nicola Salmoria:
92 ** - recreated YM2608 ADPCM ROM using data from real YM2608's output which leads to:
93 ** - added emulation of YM2608 drums.
94 ** - output of YM2608 is two times lower now - same as YM2610 (verified on real YM2608)
95 **
96 ** 16-08-2002 Jarek Burczynski:
97 ** - binary exact Envelope Generator (verified on real YM2203);
98 ** identical to YM2151
99 ** - corrected 'off by one' error in feedback calculations (when feedback is off)
100 ** - corrected connection (algorithm) calculation (verified on real YM2203 and YM2610)
101 **
102 ** 18-12-2001 Jarek Burczynski:
103 ** - added SSG-EG support (verified on real YM2203)
104 **
105 ** 12-08-2001 Jarek Burczynski:
106 ** - corrected sin_tab and tl_tab data (verified on real chip)
107 ** - corrected feedback calculations (verified on real chip)
108 ** - corrected phase generator calculations (verified on real chip)
109 ** - corrected envelope generator calculations (verified on real chip)
110 ** - corrected FM volume level (YM2610 and YM2610B).
111 ** - changed YMxxxUpdateOne() functions (YM2203, YM2608, YM2610, YM2610B, YM2612) :
112 ** this was needed to calculate YM2610 FM channels output correctly.
113 ** (Each FM channel is calculated as in other chips, but the output of the channel
114 ** gets shifted right by one *before* sending to accumulator. That was impossible to do
115 ** with previous implementation).
116 **
117 ** 23-07-2001 Jarek Burczynski, Nicola Salmoria:
118 ** - corrected YM2610 ADPCM type A algorithm and tables (verified on real chip)
119 **
120 ** 11-06-2001 Jarek Burczynski:
121 ** - corrected end of sample bug in ADPCMA_calc_cha().
122 ** Real YM2610 checks for equality between current and end addresses (only 20 LSB bits).
123 **
124 ** 08-12-98 hiro-shi:
125 ** rename ADPCMA -> ADPCMB, ADPCMB -> ADPCMA
126 ** move ROM limit check.(CALC_CH? -> 2610Write1/2)
127 ** test program (ADPCMB_TEST)
128 ** move ADPCM A/B end check.
129 ** ADPCMB repeat flag(no check)
130 ** change ADPCM volume rate (8->16) (32->48).
131 **
132 ** 09-12-98 hiro-shi:
133 ** change ADPCM volume. (8->16, 48->64)
134 ** replace ym2610 ch0/3 (YM-2610B)
135 ** change ADPCM_SHIFT (10->8) missing bank change 0x4000-0xffff.
136 ** add ADPCM_SHIFT_MASK
137 ** change ADPCMA_DECODE_MIN/MAX.
138 */
139
140 /************************************************************************/
141 /* comment of hiro-shi(Hiromitsu Shioya) */
142 /* YM2610(B) = OPN-B */
143 /* YM2610 : PSG:3ch FM:4ch ADPCM(18.5KHz):6ch DeltaT ADPCM:1ch */
144 /* YM2610B : PSG:3ch FM:6ch ADPCM(18.5KHz):6ch DeltaT ADPCM:1ch */
145 /************************************************************************/
146
147 #include "shared.h"
148
149 /* envelope generator */
150 #define ENV_BITS 10
151 #define ENV_LEN (1<<ENV_BITS)
152 #define ENV_STEP (128.0/ENV_LEN)
153
154 #define MAX_ATT_INDEX (ENV_LEN-1) /* 1023 */
155 #define MIN_ATT_INDEX (0) /* 0 */
156
157 #define EG_ATT 4
158 #define EG_DEC 3
159 #define EG_SUS 2
160 #define EG_REL 1
161 #define EG_OFF 0
162
163 /* phase generator (detune mask) */
164 #define DT_BITS 17
165 #define DT_LEN (1 << DT_BITS)
166 #define DT_MASK (DT_LEN - 1)
167
168 /* operator unit */
169 #define SIN_BITS 10
170 #define SIN_LEN (1<<SIN_BITS)
171 #define SIN_MASK (SIN_LEN-1)
172
173 #define TL_RES_LEN (256) /* 8 bits addressing (real chip) */
174
175 #define TL_BITS 14 /* channel output */
176
177 /* TL_TAB_LEN is calculated as:
178 * 13 - sinus amplitude bits (Y axis)
179 * 2 - sinus sign bit (Y axis)
180 * TL_RES_LEN - sinus resolution (X axis)
181 */
182 #define TL_TAB_LEN (13*2*TL_RES_LEN)
183 static signed int tl_tab[TL_TAB_LEN];
184
185 #define ENV_QUIET (TL_TAB_LEN>>3)
186
187 /* sin waveform table in 'decibel' scale */
188 static unsigned int sin_tab[SIN_LEN];
189
190 /* sustain level table (3dB per step) */
191 /* bit0, bit1, bit2, bit3, bit4, bit5, bit6 */
192 /* 1, 2, 4, 8, 16, 32, 64 (value)*/
193 /* 0.75, 1.5, 3, 6, 12, 24, 48 (dB)*/
194
195 /* 0 - 15: 0, 3, 6, 9,12,15,18,21,24,27,30,33,36,39,42,93 (dB)*/
196 /* attenuation value (10 bits) = (SL << 2) << 3 */
197 #define SC(db) (UINT32) ( db * (4.0/ENV_STEP) )
198 static const UINT32 sl_table[16]={
199 SC( 0),SC( 1),SC( 2),SC(3 ),SC(4 ),SC(5 ),SC(6 ),SC( 7),
200 SC( 8),SC( 9),SC(10),SC(11),SC(12),SC(13),SC(14),SC(31)
201 };
202 #undef SC
203
204
205 #define RATE_STEPS (8)
206 static const UINT8 eg_inc[19*RATE_STEPS]={
207
208 /*cycle:0 1 2 3 4 5 6 7*/
209
210 /* 0 */ 0,1, 0,1, 0,1, 0,1, /* rates 00..11 0 (increment by 0 or 1) */
211 /* 1 */ 0,1, 0,1, 1,1, 0,1, /* rates 00..11 1 */
212 /* 2 */ 0,1, 1,1, 0,1, 1,1, /* rates 00..11 2 */
213 /* 3 */ 0,1, 1,1, 1,1, 1,1, /* rates 00..11 3 */
214
215 /* 4 */ 1,1, 1,1, 1,1, 1,1, /* rate 12 0 (increment by 1) */
216 /* 5 */ 1,1, 1,2, 1,1, 1,2, /* rate 12 1 */
217 /* 6 */ 1,2, 1,2, 1,2, 1,2, /* rate 12 2 */
218 /* 7 */ 1,2, 2,2, 1,2, 2,2, /* rate 12 3 */
219
220 /* 8 */ 2,2, 2,2, 2,2, 2,2, /* rate 13 0 (increment by 2) */
221 /* 9 */ 2,2, 2,4, 2,2, 2,4, /* rate 13 1 */
222 /*10 */ 2,4, 2,4, 2,4, 2,4, /* rate 13 2 */
223 /*11 */ 2,4, 4,4, 2,4, 4,4, /* rate 13 3 */
224
225 /*12 */ 4,4, 4,4, 4,4, 4,4, /* rate 14 0 (increment by 4) */
226 /*13 */ 4,4, 4,8, 4,4, 4,8, /* rate 14 1 */
227 /*14 */ 4,8, 4,8, 4,8, 4,8, /* rate 14 2 */
228 /*15 */ 4,8, 8,8, 4,8, 8,8, /* rate 14 3 */
229
230 /*16 */ 8,8, 8,8, 8,8, 8,8, /* rates 15 0, 15 1, 15 2, 15 3 (increment by 8) */
231 /*17 */ 16,16,16,16,16,16,16,16, /* rates 15 2, 15 3 for attack */
232 /*18 */ 0,0, 0,0, 0,0, 0,0, /* infinity rates for attack and decay(s) */
233 };
234
235
236 #define O(a) (a*RATE_STEPS)
237
238 /*note that there is no O(17) in this table - it's directly in the code */
239 static const UINT8 eg_rate_select[32+64+32]={ /* Envelope Generator rates (32 + 64 rates + 32 RKS) */
240 /* 32 infinite time rates (same as Rate 0) */
241 O(18),O(18),O(18),O(18),O(18),O(18),O(18),O(18),
242 O(18),O(18),O(18),O(18),O(18),O(18),O(18),O(18),
243 O(18),O(18),O(18),O(18),O(18),O(18),O(18),O(18),
244 O(18),O(18),O(18),O(18),O(18),O(18),O(18),O(18),
245
246 /* rates 00-11 */
247 /*
248 O( 0),O( 1)
249 */
250 O(18),O(18), /* from Nemesis's tests on real YM2612 hardware */
251 O( 2),O( 3),
252 O( 0),O( 1),O( 2),O( 3),
253 O( 0),O( 1),O( 2),O( 3),
254 O( 0),O( 1),O( 2),O( 3),
255 O( 0),O( 1),O( 2),O( 3),
256 O( 0),O( 1),O( 2),O( 3),
257 O( 0),O( 1),O( 2),O( 3),
258 O( 0),O( 1),O( 2),O( 3),
259 O( 0),O( 1),O( 2),O( 3),
260 O( 0),O( 1),O( 2),O( 3),
261 O( 0),O( 1),O( 2),O( 3),
262 O( 0),O( 1),O( 2),O( 3),
263
264 /* rate 12 */
265 O( 4),O( 5),O( 6),O( 7),
266
267 /* rate 13 */
268 O( 8),O( 9),O(10),O(11),
269
270 /* rate 14 */
271 O(12),O(13),O(14),O(15),
272
273 /* rate 15 */
274 O(16),O(16),O(16),O(16),
275
276 /* 32 dummy rates (same as 15 3) */
277 O(16),O(16),O(16),O(16),O(16),O(16),O(16),O(16),
278 O(16),O(16),O(16),O(16),O(16),O(16),O(16),O(16),
279 O(16),O(16),O(16),O(16),O(16),O(16),O(16),O(16),
280 O(16),O(16),O(16),O(16),O(16),O(16),O(16),O(16)
281
282 };
283 #undef O
284
285 /*rate 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15*/
286 /*shift 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0, 0, 0, 0, 0 */
287 /*mask 2047, 1023, 511, 255, 127, 63, 31, 15, 7, 3, 1, 0, 0, 0, 0, 0 */
288
289 #define O(a) (a*1)
290 static const UINT8 eg_rate_shift[32+64+32]={ /* Envelope Generator counter shifts (32 + 64 rates + 32 RKS) */
291 /* 32 infinite time rates */
292 /* O(0),O(0),O(0),O(0),O(0),O(0),O(0),O(0),
293 O(0),O(0),O(0),O(0),O(0),O(0),O(0),O(0),
294 O(0),O(0),O(0),O(0),O(0),O(0),O(0),O(0),
295 O(0),O(0),O(0),O(0),O(0),O(0),O(0),O(0), */
296
297 /* fixed (should be the same as rate 0, even if it makes no difference since increment value is 0 for these rates) */
298 O(11),O(11),O(11),O(11),O(11),O(11),O(11),O(11),
299 O(11),O(11),O(11),O(11),O(11),O(11),O(11),O(11),
300 O(11),O(11),O(11),O(11),O(11),O(11),O(11),O(11),
301 O(11),O(11),O(11),O(11),O(11),O(11),O(11),O(11),
302
303 /* rates 00-11 */
304 O(11),O(11),O(11),O(11),
305 O(10),O(10),O(10),O(10),
306 O( 9),O( 9),O( 9),O( 9),
307 O( 8),O( 8),O( 8),O( 8),
308 O( 7),O( 7),O( 7),O( 7),
309 O( 6),O( 6),O( 6),O( 6),
310 O( 5),O( 5),O( 5),O( 5),
311 O( 4),O( 4),O( 4),O( 4),
312 O( 3),O( 3),O( 3),O( 3),
313 O( 2),O( 2),O( 2),O( 2),
314 O( 1),O( 1),O( 1),O( 1),
315 O( 0),O( 0),O( 0),O( 0),
316
317 /* rate 12 */
318 O( 0),O( 0),O( 0),O( 0),
319
320 /* rate 13 */
321 O( 0),O( 0),O( 0),O( 0),
322
323 /* rate 14 */
324 O( 0),O( 0),O( 0),O( 0),
325
326 /* rate 15 */
327 O( 0),O( 0),O( 0),O( 0),
328
329 /* 32 dummy rates (same as 15 3) */
330 O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),
331 O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),
332 O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),
333 O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0)
334
335 };
336 #undef O
337
338 static const UINT8 dt_tab[4 * 32]={
339 /* this is YM2151 and YM2612 phase increment data (in 10.10 fixed point format)*/
340 /* FD=0 */
341 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
342 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
343 /* FD=1 */
344 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2,
345 2, 3, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7, 8, 8, 8, 8,
346 /* FD=2 */
347 1, 1, 1, 1, 2, 2, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5,
348 5, 6, 6, 7, 8, 8, 9,10,11,12,13,14,16,16,16,16,
349 /* FD=3 */
350 2, 2, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7,
351 8 , 8, 9,10,11,12,13,14,16,17,19,20,22,22,22,22
352 };
353
354
355 /* OPN key frequency number -> key code follow table */
356 /* fnum higher 4bit -> keycode lower 2bit */
357 static const UINT8 opn_fktable[16] = {0,0,0,0,0,0,0,1,2,3,3,3,3,3,3,3};
358
359
360 /* 8 LFO speed parameters */
361 /* each value represents number of samples that one LFO level will last for */
362 static const UINT32 lfo_samples_per_step[8] = {108, 77, 71, 67, 62, 44, 8, 5};
363
364
365 /*There are 4 different LFO AM depths available, they are:
366 0 dB, 1.4 dB, 5.9 dB, 11.8 dB
367 Here is how it is generated (in EG steps):
368
369 11.8 dB = 0, 2, 4, 6, 8, 10,12,14,16...126,126,124,122,120,118,....4,2,0
370 5.9 dB = 0, 1, 2, 3, 4, 5, 6, 7, 8....63, 63, 62, 61, 60, 59,.....2,1,0
371 1.4 dB = 0, 0, 0, 0, 1, 1, 1, 1, 2,...15, 15, 15, 15, 14, 14,.....0,0,0
372
373 (1.4 dB is loosing precision as you can see)
374
375 It's implemented as generator from 0..126 with step 2 then a shift
376 right N times, where N is:
377 8 for 0 dB
378 3 for 1.4 dB
379 1 for 5.9 dB
380 0 for 11.8 dB
381 */
382 static const UINT8 lfo_ams_depth_shift[4] = {8, 3, 1, 0};
383
384
385
386 /*There are 8 different LFO PM depths available, they are:
387 0, 3.4, 6.7, 10, 14, 20, 40, 80 (cents)
388
389 Modulation level at each depth depends on F-NUMBER bits: 4,5,6,7,8,9,10
390 (bits 8,9,10 = FNUM MSB from OCT/FNUM register)
391
392 Here we store only first quarter (positive one) of full waveform.
393 Full table (lfo_pm_table) containing all 128 waveforms is build
394 at run (init) time.
395
396 One value in table below represents 4 (four) basic LFO steps
397 (1 PM step = 4 AM steps).
398
399 For example:
400 at LFO SPEED=0 (which is 108 samples per basic LFO step)
401 one value from "lfo_pm_output" table lasts for 432 consecutive
402 samples (4*108=432) and one full LFO waveform cycle lasts for 13824
403 samples (32*432=13824; 32 because we store only a quarter of whole
404 waveform in the table below)
405 */
406 static const UINT8 lfo_pm_output[7*8][8]={
407 /* 7 bits meaningful (of F-NUMBER), 8 LFO output levels per one depth (out of 32), 8 LFO depths */
408 /* FNUM BIT 4: 000 0001xxxx */
409 /* DEPTH 0 */ {0, 0, 0, 0, 0, 0, 0, 0},
410 /* DEPTH 1 */ {0, 0, 0, 0, 0, 0, 0, 0},
411 /* DEPTH 2 */ {0, 0, 0, 0, 0, 0, 0, 0},
412 /* DEPTH 3 */ {0, 0, 0, 0, 0, 0, 0, 0},
413 /* DEPTH 4 */ {0, 0, 0, 0, 0, 0, 0, 0},
414 /* DEPTH 5 */ {0, 0, 0, 0, 0, 0, 0, 0},
415 /* DEPTH 6 */ {0, 0, 0, 0, 0, 0, 0, 0},
416 /* DEPTH 7 */ {0, 0, 0, 0, 1, 1, 1, 1},
417
418 /* FNUM BIT 5: 000 0010xxxx */
419 /* DEPTH 0 */ {0, 0, 0, 0, 0, 0, 0, 0},
420 /* DEPTH 1 */ {0, 0, 0, 0, 0, 0, 0, 0},
421 /* DEPTH 2 */ {0, 0, 0, 0, 0, 0, 0, 0},
422 /* DEPTH 3 */ {0, 0, 0, 0, 0, 0, 0, 0},
423 /* DEPTH 4 */ {0, 0, 0, 0, 0, 0, 0, 0},
424 /* DEPTH 5 */ {0, 0, 0, 0, 0, 0, 0, 0},
425 /* DEPTH 6 */ {0, 0, 0, 0, 1, 1, 1, 1},
426 /* DEPTH 7 */ {0, 0, 1, 1, 2, 2, 2, 3},
427
428 /* FNUM BIT 6: 000 0100xxxx */
429 /* DEPTH 0 */ {0, 0, 0, 0, 0, 0, 0, 0},
430 /* DEPTH 1 */ {0, 0, 0, 0, 0, 0, 0, 0},
431 /* DEPTH 2 */ {0, 0, 0, 0, 0, 0, 0, 0},
432 /* DEPTH 3 */ {0, 0, 0, 0, 0, 0, 0, 0},
433 /* DEPTH 4 */ {0, 0, 0, 0, 0, 0, 0, 1},
434 /* DEPTH 5 */ {0, 0, 0, 0, 1, 1, 1, 1},
435 /* DEPTH 6 */ {0, 0, 1, 1, 2, 2, 2, 3},
436 /* DEPTH 7 */ {0, 0, 2, 3, 4, 4, 5, 6},
437
438 /* FNUM BIT 7: 000 1000xxxx */
439 /* DEPTH 0 */ {0, 0, 0, 0, 0, 0, 0, 0},
440 /* DEPTH 1 */ {0, 0, 0, 0, 0, 0, 0, 0},
441 /* DEPTH 2 */ {0, 0, 0, 0, 0, 0, 1, 1},
442 /* DEPTH 3 */ {0, 0, 0, 0, 1, 1, 1, 1},
443 /* DEPTH 4 */ {0, 0, 0, 1, 1, 1, 1, 2},
444 /* DEPTH 5 */ {0, 0, 1, 1, 2, 2, 2, 3},
445 /* DEPTH 6 */ {0, 0, 2, 3, 4, 4, 5, 6},
446 /* DEPTH 7 */ {0, 0, 4, 6, 8, 8, 0xa, 0xc},
447
448 /* FNUM BIT 8: 001 0000xxxx */
449 /* DEPTH 0 */ {0, 0, 0, 0, 0, 0, 0, 0},
450 /* DEPTH 1 */ {0, 0, 0, 0, 1, 1, 1, 1},
451 /* DEPTH 2 */ {0, 0, 0, 1, 1, 1, 2, 2},
452 /* DEPTH 3 */ {0, 0, 1, 1, 2, 2, 3, 3},
453 /* DEPTH 4 */ {0, 0, 1, 2, 2, 2, 3, 4},
454 /* DEPTH 5 */ {0, 0, 2, 3, 4, 4, 5, 6},
455 /* DEPTH 6 */ {0, 0, 4, 6, 8, 8, 0xa, 0xc},
456 /* DEPTH 7 */ {0, 0, 8, 0xc,0x10,0x10,0x14,0x18},
457
458 /* FNUM BIT 9: 010 0000xxxx */
459 /* DEPTH 0 */ {0, 0, 0, 0, 0, 0, 0, 0},
460 /* DEPTH 1 */ {0, 0, 0, 0, 2, 2, 2, 2},
461 /* DEPTH 2 */ {0, 0, 0, 2, 2, 2, 4, 4},
462 /* DEPTH 3 */ {0, 0, 2, 2, 4, 4, 6, 6},
463 /* DEPTH 4 */ {0, 0, 2, 4, 4, 4, 6, 8},
464 /* DEPTH 5 */ {0, 0, 4, 6, 8, 8, 0xa, 0xc},
465 /* DEPTH 6 */ {0, 0, 8, 0xc,0x10,0x10,0x14,0x18},
466 /* DEPTH 7 */ {0, 0,0x10,0x18,0x20,0x20,0x28,0x30},
467
468 /* FNUM BIT10: 100 0000xxxx */
469 /* DEPTH 0 */ {0, 0, 0, 0, 0, 0, 0, 0},
470 /* DEPTH 1 */ {0, 0, 0, 0, 4, 4, 4, 4},
471 /* DEPTH 2 */ {0, 0, 0, 4, 4, 4, 8, 8},
472 /* DEPTH 3 */ {0, 0, 4, 4, 8, 8, 0xc, 0xc},
473 /* DEPTH 4 */ {0, 0, 4, 8, 8, 8, 0xc,0x10},
474 /* DEPTH 5 */ {0, 0, 8, 0xc,0x10,0x10,0x14,0x18},
475 /* DEPTH 6 */ {0, 0,0x10,0x18,0x20,0x20,0x28,0x30},
476 /* DEPTH 7 */ {0, 0,0x20,0x30,0x40,0x40,0x50,0x60},
477
478 };
479
480 /* all 128 LFO PM waveforms */
481 static INT32 lfo_pm_table[128*8*32]; /* 128 combinations of 7 bits meaningful (of F-NUMBER), 8 LFO depths, 32 LFO output levels per one depth */
482
483 /* register number to channel number , slot offset */
484 #define OPN_CHAN(N) (N&3)
485 #define OPN_SLOT(N) ((N>>2)&3)
486
487 /* slot number */
488 #define SLOT1 0
489 #define SLOT2 2
490 #define SLOT3 1
491 #define SLOT4 3
492
493 /* struct describing a single operator (SLOT) */
494 typedef struct
495 {
496 INT32 *DT; /* detune :dt_tab[DT] */
497 UINT8 KSR; /* key scale rate :3-KSR */
498 UINT32 ar; /* attack rate */
499 UINT32 d1r; /* decay rate */
500 UINT32 d2r; /* sustain rate */
501 UINT32 rr; /* release rate */
502 UINT8 ksr; /* key scale rate :kcode>>(3-KSR) */
503 UINT32 mul; /* multiple :ML_TABLE[ML] */
504
505 /* Phase Generator */
506 UINT32 phase; /* phase counter */
507 INT32 Incr; /* phase step */
508
509 /* Envelope Generator */
510 UINT8 state; /* phase type */
511 UINT32 tl; /* total level: TL << 3 */
512 INT32 volume; /* envelope counter */
513 UINT32 sl; /* sustain level:sl_table[SL] */
514 UINT32 vol_out; /* current output from EG circuit (without AM from LFO) */
515
516 UINT8 eg_sh_ar; /* (attack state) */
517 UINT8 eg_sel_ar; /* (attack state) */
518 UINT8 eg_sh_d1r; /* (decay state) */
519 UINT8 eg_sel_d1r; /* (decay state) */
520 UINT8 eg_sh_d2r; /* (sustain state) */
521 UINT8 eg_sel_d2r; /* (sustain state) */
522 UINT8 eg_sh_rr; /* (release state) */
523 UINT8 eg_sel_rr; /* (release state) */
524
525 UINT8 ssg; /* SSG-EG waveform */
526 UINT8 ssgn; /* SSG-EG negated output */
527
528 UINT8 key; /* 0=last key was KEY OFF, 1=KEY ON */
529
530 /* LFO */
531 UINT32 AMmask; /* AM enable flag */
532
533 } FM_SLOT;
534
535 typedef struct
536 {
537 FM_SLOT SLOT[4]; /* four SLOTs (operators) */
538
539 UINT8 ALGO; /* algorithm */
540 UINT8 FB; /* feedback shift */
541 INT32 op1_out[2]; /* op1 output for feedback */
542
543 INT32 *connect1; /* SLOT1 output pointer */
544 INT32 *connect3; /* SLOT3 output pointer */
545 INT32 *connect2; /* SLOT2 output pointer */
546 INT32 *connect4; /* SLOT4 output pointer */
547
548 INT32 *mem_connect; /* where to put the delayed sample (MEM) */
549 INT32 mem_value; /* delayed sample (MEM) value */
550
551 INT32 pms; /* channel PMS */
552 UINT8 ams; /* channel AMS */
553
554 UINT32 fc; /* fnum,blk */
555 UINT8 kcode; /* key code */
556 UINT32 block_fnum; /* blk/fnum value (for LFO PM calculations) */
557 } FM_CH;
558
559
560 typedef struct
561 {
562 UINT16 address; /* address register */
563 UINT8 status; /* status flag */
564 UINT32 mode; /* mode CSM / 3SLOT */
565 UINT8 fn_h; /* freq latch */
566 INT32 TA; /* timer a value */
567 INT32 TAL; /* timer a base */
568 INT32 TAC; /* timer a counter */
569 INT32 TB; /* timer b value */
570 INT32 TBL; /* timer b base */
571 INT32 TBC; /* timer b counter */
572 INT32 dt_tab[8][32]; /* DeTune table */
573
574 } FM_ST;
575
576
577 /***********************************************************/
578 /* OPN unit */
579 /***********************************************************/
580
581 /* OPN 3slot struct */
582 typedef struct
583 {
584 UINT32 fc[3]; /* fnum3,blk3: calculated */
585 UINT8 fn_h; /* freq3 latch */
586 UINT8 kcode[3]; /* key code */
587 UINT32 block_fnum[3]; /* current fnum value for this slot (can be different betweeen slots of one channel in 3slot mode) */
588 UINT8 key_csm; /* CSM mode Key-ON flag */
589
590 } FM_3SLOT;
591
592 /* OPN/A/B common state */
593 typedef struct
594 {
595 FM_ST ST; /* general state */
596 FM_3SLOT SL3; /* 3 slot mode state */
597 unsigned int pan[6*2]; /* fm channels output masks (0xffffffff = enable) */
598
599 /* EG */
600 UINT32 eg_cnt; /* global envelope generator counter */
601 UINT32 eg_timer; /* global envelope generator counter works at frequency = chipclock/144/3 */
602
603 /* LFO */
604 UINT8 lfo_cnt; /* current LFO phase (out of 128) */
605 UINT32 lfo_timer; /* current LFO phase runs at LFO frequency */
606 UINT32 lfo_timer_overflow; /* LFO timer overflows every N samples (depends on LFO frequency) */
607 UINT32 LFO_AM; /* current LFO AM step */
608 UINT32 LFO_PM; /* current LFO PM step */
609
610 } FM_OPN;
611
612 /***********************************************************/
613 /* YM2612 chip */
614 /***********************************************************/
615 typedef struct
616 {
617 FM_CH CH[6]; /* channel state */
618 UINT8 dacen; /* DAC mode */
619 INT32 dacout; /* DAC output */
620 FM_OPN OPN; /* OPN state */
621
622 } YM2612;
623
624 /* emulated chip */
625 static YM2612 ym2612;
626
627 /* current chip state */
628 static INT32 m2,c1,c2; /* Phase Modulation input for operators 2,3,4 */
629 static INT32 mem; /* one sample delay memory */
630 static INT32 out_fm[6]; /* outputs of working channels */
631
632 /* chip type */
633 static UINT32 op_mask[8][4]; /* operator output bitmasking (DAC quantization) */
634 static int chip_type = YM2612_DISCRETE;
635
636
FM_KEYON(FM_CH * CH,int s)637 INLINE void FM_KEYON(FM_CH *CH , int s )
638 {
639 FM_SLOT *SLOT = &CH->SLOT[s];
640
641 if (!SLOT->key && !ym2612.OPN.SL3.key_csm)
642 {
643 /* restart Phase Generator */
644 SLOT->phase = 0;
645
646 /* reset SSG-EG inversion flag */
647 SLOT->ssgn = 0;
648
649 if ((SLOT->ar + SLOT->ksr) < 94 /*32+62*/)
650 {
651 SLOT->state = (SLOT->volume <= MIN_ATT_INDEX) ? ((SLOT->sl == MIN_ATT_INDEX) ? EG_SUS : EG_DEC) : EG_ATT;
652 }
653 else
654 {
655 /* force attenuation level to 0 */
656 SLOT->volume = MIN_ATT_INDEX;
657
658 /* directly switch to Decay (or Sustain) */
659 SLOT->state = (SLOT->sl == MIN_ATT_INDEX) ? EG_SUS : EG_DEC;
660 }
661
662 /* recalculate EG output */
663 if ((SLOT->ssg&0x08) && (SLOT->ssgn ^ (SLOT->ssg&0x04)))
664 SLOT->vol_out = ((UINT32)(0x200 - SLOT->volume) & MAX_ATT_INDEX) + SLOT->tl;
665 else
666 SLOT->vol_out = (UINT32)SLOT->volume + SLOT->tl;
667 }
668
669 SLOT->key = 1;
670 }
671
FM_KEYOFF(FM_CH * CH,int s)672 INLINE void FM_KEYOFF(FM_CH *CH , int s )
673 {
674 FM_SLOT *SLOT = &CH->SLOT[s];
675
676 if (SLOT->key && !ym2612.OPN.SL3.key_csm)
677 {
678 if (SLOT->state>EG_REL)
679 {
680 SLOT->state = EG_REL; /* phase -> Release */
681
682 /* SSG-EG specific update */
683 if (SLOT->ssg&0x08)
684 {
685 /* convert EG attenuation level */
686 if (SLOT->ssgn ^ (SLOT->ssg&0x04))
687 SLOT->volume = (0x200 - SLOT->volume);
688
689 /* force EG attenuation level */
690 if (SLOT->volume >= 0x200)
691 {
692 SLOT->volume = MAX_ATT_INDEX;
693 SLOT->state = EG_OFF;
694 }
695
696 /* recalculate EG output */
697 SLOT->vol_out = (UINT32)SLOT->volume + SLOT->tl;
698 }
699 }
700 }
701
702 SLOT->key = 0;
703 }
704
FM_KEYON_CSM(FM_CH * CH,int s)705 INLINE void FM_KEYON_CSM(FM_CH *CH , int s )
706 {
707 FM_SLOT *SLOT = &CH->SLOT[s];
708
709 if (!SLOT->key && !ym2612.OPN.SL3.key_csm)
710 {
711 /* restart Phase Generator */
712 SLOT->phase = 0;
713
714 /* reset SSG-EG inversion flag */
715 SLOT->ssgn = 0;
716
717 if ((SLOT->ar + SLOT->ksr) < 94 /*32+62*/)
718 {
719 SLOT->state = (SLOT->volume <= MIN_ATT_INDEX) ? ((SLOT->sl == MIN_ATT_INDEX) ? EG_SUS : EG_DEC) : EG_ATT;
720 }
721 else
722 {
723 /* force attenuation level to 0 */
724 SLOT->volume = MIN_ATT_INDEX;
725
726 /* directly switch to Decay (or Sustain) */
727 SLOT->state = (SLOT->sl == MIN_ATT_INDEX) ? EG_SUS : EG_DEC;
728 }
729
730 /* recalculate EG output */
731 if ((SLOT->ssg&0x08) && (SLOT->ssgn ^ (SLOT->ssg&0x04)))
732 SLOT->vol_out = ((UINT32)(0x200 - SLOT->volume) & MAX_ATT_INDEX) + SLOT->tl;
733 else
734 SLOT->vol_out = (UINT32)SLOT->volume + SLOT->tl;
735 }
736 }
737
FM_KEYOFF_CSM(FM_CH * CH,int s)738 INLINE void FM_KEYOFF_CSM(FM_CH *CH , int s )
739 {
740 FM_SLOT *SLOT = &CH->SLOT[s];
741 if (!SLOT->key)
742 {
743 if (SLOT->state>EG_REL)
744 {
745 SLOT->state = EG_REL; /* phase -> Release */
746
747 /* SSG-EG specific update */
748 if (SLOT->ssg&0x08)
749 {
750 /* convert EG attenuation level */
751 if (SLOT->ssgn ^ (SLOT->ssg&0x04))
752 SLOT->volume = (0x200 - SLOT->volume);
753
754 /* force EG attenuation level */
755 if (SLOT->volume >= 0x200)
756 {
757 SLOT->volume = MAX_ATT_INDEX;
758 SLOT->state = EG_OFF;
759 }
760
761 /* recalculate EG output */
762 SLOT->vol_out = (UINT32)SLOT->volume + SLOT->tl;
763 }
764 }
765 }
766 }
767
768 /* CSM Key Controll */
CSMKeyControll(FM_CH * CH)769 INLINE void CSMKeyControll(FM_CH *CH)
770 {
771 /* all key ON (verified by Nemesis on real hardware) */
772 FM_KEYON_CSM(CH,SLOT1);
773 FM_KEYON_CSM(CH,SLOT2);
774 FM_KEYON_CSM(CH,SLOT3);
775 FM_KEYON_CSM(CH,SLOT4);
776 ym2612.OPN.SL3.key_csm = 1;
777 }
778
INTERNAL_TIMER_A()779 INLINE void INTERNAL_TIMER_A()
780 {
781 if (ym2612.OPN.ST.mode & 0x01)
782 {
783 ym2612.OPN.ST.TAC--;
784 if (ym2612.OPN.ST.TAC <= 0)
785 {
786 /* set status (if enabled) */
787 if (ym2612.OPN.ST.mode & 0x04)
788 ym2612.OPN.ST.status |= 0x01;
789
790 /* reload the counter */
791 ym2612.OPN.ST.TAC = ym2612.OPN.ST.TAL;
792
793 /* CSM mode auto key on */
794 if ((ym2612.OPN.ST.mode & 0xC0) == 0x80)
795 CSMKeyControll(&ym2612.CH[2]);
796 }
797 }
798 }
799
INTERNAL_TIMER_B(int step)800 INLINE void INTERNAL_TIMER_B(int step)
801 {
802 if (ym2612.OPN.ST.mode & 0x02)
803 {
804 ym2612.OPN.ST.TBC-=step;
805 if (ym2612.OPN.ST.TBC <= 0)
806 {
807 /* set status (if enabled) */
808 if (ym2612.OPN.ST.mode & 0x08)
809 ym2612.OPN.ST.status |= 0x02;
810
811 /* reload the counter */
812 do
813 {
814 ym2612.OPN.ST.TBC += ym2612.OPN.ST.TBL;
815 }
816 while (ym2612.OPN.ST.TBC <= 0);
817 }
818 }
819 }
820
821 /* OPN Mode Register Write */
set_timers(int v)822 INLINE void set_timers(int v )
823 {
824 /* b7 = CSM MODE */
825 /* b6 = 3 slot mode */
826 /* b5 = reset b */
827 /* b4 = reset a */
828 /* b3 = timer enable b */
829 /* b2 = timer enable a */
830 /* b1 = load b */
831 /* b0 = load a */
832
833 if ((ym2612.OPN.ST.mode ^ v) & 0xC0)
834 {
835 /* phase increment need to be recalculated */
836 ym2612.CH[2].SLOT[SLOT1].Incr=-1;
837
838 /* CSM mode disabled and CSM key ON active*/
839 if (((v & 0xC0) != 0x80) && ym2612.OPN.SL3.key_csm)
840 {
841 /* CSM Mode Key OFF (verified by Nemesis on real hardware) */
842 FM_KEYOFF_CSM(&ym2612.CH[2],SLOT1);
843 FM_KEYOFF_CSM(&ym2612.CH[2],SLOT2);
844 FM_KEYOFF_CSM(&ym2612.CH[2],SLOT3);
845 FM_KEYOFF_CSM(&ym2612.CH[2],SLOT4);
846 ym2612.OPN.SL3.key_csm = 0;
847 }
848 }
849
850 /* reload Timers */
851 if ((v&1) && !(ym2612.OPN.ST.mode&1))
852 ym2612.OPN.ST.TAC = ym2612.OPN.ST.TAL;
853 if ((v&2) && !(ym2612.OPN.ST.mode&2))
854 ym2612.OPN.ST.TBC = ym2612.OPN.ST.TBL;
855
856 /* reset Timers flags */
857 ym2612.OPN.ST.status &= (~v >> 4);
858
859 ym2612.OPN.ST.mode = v;
860 }
861
862 /* set algorithm connection */
setup_connection(FM_CH * CH,int ch)863 INLINE void setup_connection( FM_CH *CH, int ch )
864 {
865 INT32 *carrier = &out_fm[ch];
866
867 INT32 **om1 = &CH->connect1;
868 INT32 **om2 = &CH->connect3;
869 INT32 **oc1 = &CH->connect2;
870
871 INT32 **memc = &CH->mem_connect;
872
873 switch( CH->ALGO ){
874 case 0:
875 /* M1---C1---MEM---M2---C2---OUT */
876 *om1 = &c1;
877 *oc1 = &mem;
878 *om2 = &c2;
879 *memc= &m2;
880 break;
881 case 1:
882 /* M1------+-MEM---M2---C2---OUT */
883 /* C1-+ */
884 *om1 = &mem;
885 *oc1 = &mem;
886 *om2 = &c2;
887 *memc= &m2;
888 break;
889 case 2:
890 /* M1-----------------+-C2---OUT */
891 /* C1---MEM---M2-+ */
892 *om1 = &c2;
893 *oc1 = &mem;
894 *om2 = &c2;
895 *memc= &m2;
896 break;
897 case 3:
898 /* M1---C1---MEM------+-C2---OUT */
899 /* M2-+ */
900 *om1 = &c1;
901 *oc1 = &mem;
902 *om2 = &c2;
903 *memc= &c2;
904 break;
905 case 4:
906 /* M1---C1-+-OUT */
907 /* M2---C2-+ */
908 /* MEM: not used */
909 *om1 = &c1;
910 *oc1 = carrier;
911 *om2 = &c2;
912 *memc= &mem; /* store it anywhere where it will not be used */
913 break;
914 case 5:
915 /* +----C1----+ */
916 /* M1-+-MEM---M2-+-OUT */
917 /* +----C2----+ */
918 *om1 = 0; /* special mark */
919 *oc1 = carrier;
920 *om2 = carrier;
921 *memc= &m2;
922 break;
923 case 6:
924 /* M1---C1-+ */
925 /* M2-+-OUT */
926 /* C2-+ */
927 /* MEM: not used */
928 *om1 = &c1;
929 *oc1 = carrier;
930 *om2 = carrier;
931 *memc= &mem; /* store it anywhere where it will not be used */
932 break;
933 case 7:
934 /* M1-+ */
935 /* C1-+-OUT */
936 /* M2-+ */
937 /* C2-+ */
938 /* MEM: not used*/
939 *om1 = carrier;
940 *oc1 = carrier;
941 *om2 = carrier;
942 *memc= &mem; /* store it anywhere where it will not be used */
943 break;
944 }
945
946 CH->connect4 = carrier;
947 }
948
949 /* set detune & multiple */
set_det_mul(FM_CH * CH,FM_SLOT * SLOT,int v)950 INLINE void set_det_mul(FM_CH *CH,FM_SLOT *SLOT,int v)
951 {
952 SLOT->mul = (v&0x0f)? (v&0x0f)*2 : 1;
953 SLOT->DT = ym2612.OPN.ST.dt_tab[(v>>4)&7];
954 CH->SLOT[SLOT1].Incr=-1;
955 }
956
957 /* set total level */
set_tl(FM_SLOT * SLOT,int v)958 INLINE void set_tl(FM_SLOT *SLOT , int v)
959 {
960 SLOT->tl = (v&0x7f)<<(ENV_BITS-7); /* 7bit TL */
961
962 /* recalculate EG output */
963 if ((SLOT->ssg&0x08) && (SLOT->ssgn ^ (SLOT->ssg&0x04)) && (SLOT->state > EG_REL))
964 SLOT->vol_out = ((UINT32)(0x200 - SLOT->volume) & MAX_ATT_INDEX) + SLOT->tl;
965 else
966 SLOT->vol_out = (UINT32)SLOT->volume + SLOT->tl;
967 }
968
969 /* set attack rate & key scale */
set_ar_ksr(FM_CH * CH,FM_SLOT * SLOT,int v)970 INLINE void set_ar_ksr(FM_CH *CH,FM_SLOT *SLOT,int v)
971 {
972 UINT8 old_KSR = SLOT->KSR;
973
974 SLOT->ar = (v&0x1f) ? 32 + ((v&0x1f)<<1) : 0;
975
976 SLOT->KSR = 3-(v>>6);
977 if (SLOT->KSR != old_KSR)
978 {
979 CH->SLOT[SLOT1].Incr=-1;
980 }
981
982 /* Even if it seems unnecessary to do it here, it could happen that KSR and KC */
983 /* are modified but the resulted SLOT->ksr value (kc >> SLOT->KSR) remains unchanged. */
984 /* In such case, Attack Rate would not be recalculated by "refresh_fc_eg_slot". */
985 /* This actually fixes the intro of "The Adventures of Batman & Robin" (Eke-Eke) */
986 if ((SLOT->ar + SLOT->ksr) < (32+62))
987 {
988 SLOT->eg_sh_ar = eg_rate_shift [SLOT->ar + SLOT->ksr ];
989 SLOT->eg_sel_ar = eg_rate_select[SLOT->ar + SLOT->ksr ];
990 }
991 else
992 {
993 /* verified by Nemesis on real hardware (Attack phase is blocked) */
994 SLOT->eg_sh_ar = 0;
995 SLOT->eg_sel_ar = 18*RATE_STEPS;
996 }
997 }
998
999 /* set decay rate */
set_dr(FM_SLOT * SLOT,int v)1000 INLINE void set_dr(FM_SLOT *SLOT,int v)
1001 {
1002 SLOT->d1r = (v&0x1f) ? 32 + ((v&0x1f)<<1) : 0;
1003
1004 SLOT->eg_sh_d1r = eg_rate_shift [SLOT->d1r + SLOT->ksr];
1005 SLOT->eg_sel_d1r= eg_rate_select[SLOT->d1r + SLOT->ksr];
1006
1007 }
1008
1009 /* set sustain rate */
set_sr(FM_SLOT * SLOT,int v)1010 INLINE void set_sr(FM_SLOT *SLOT,int v)
1011 {
1012 SLOT->d2r = (v&0x1f) ? 32 + ((v&0x1f)<<1) : 0;
1013
1014 SLOT->eg_sh_d2r = eg_rate_shift [SLOT->d2r + SLOT->ksr];
1015 SLOT->eg_sel_d2r= eg_rate_select[SLOT->d2r + SLOT->ksr];
1016 }
1017
1018 /* set release rate */
set_sl_rr(FM_SLOT * SLOT,int v)1019 INLINE void set_sl_rr(FM_SLOT *SLOT,int v)
1020 {
1021 SLOT->sl = sl_table[ v>>4 ];
1022
1023 /* check EG state changes */
1024 if ((SLOT->state == EG_DEC) && (SLOT->volume >= (INT32)(SLOT->sl)))
1025 SLOT->state = EG_SUS;
1026
1027 SLOT->rr = 34 + ((v&0x0f)<<2);
1028
1029 SLOT->eg_sh_rr = eg_rate_shift [SLOT->rr + SLOT->ksr];
1030 SLOT->eg_sel_rr = eg_rate_select[SLOT->rr + SLOT->ksr];
1031 }
1032
1033 /* advance LFO to next sample */
advance_lfo()1034 INLINE void advance_lfo()
1035 {
1036 if (ym2612.OPN.lfo_timer_overflow) /* LFO enabled ? */
1037 {
1038 /* increment LFO timer (every samples) */
1039 ym2612.OPN.lfo_timer ++;
1040
1041 /* when LFO is enabled, one level will last for 108, 77, 71, 67, 62, 44, 8 or 5 samples */
1042 if (ym2612.OPN.lfo_timer >= ym2612.OPN.lfo_timer_overflow)
1043 {
1044 ym2612.OPN.lfo_timer = 0;
1045
1046 /* There are 128 LFO steps */
1047 ym2612.OPN.lfo_cnt = ( ym2612.OPN.lfo_cnt + 1 ) & 127;
1048
1049 /* triangle (inverted) */
1050 /* AM: from 126 to 0 step -2, 0 to 126 step +2 */
1051 if (ym2612.OPN.lfo_cnt<64)
1052 ym2612.OPN.LFO_AM = (ym2612.OPN.lfo_cnt ^ 63) << 1;
1053 else
1054 ym2612.OPN.LFO_AM = (ym2612.OPN.lfo_cnt & 63) << 1;
1055
1056 /* PM works with 4 times slower clock */
1057 ym2612.OPN.LFO_PM = ym2612.OPN.lfo_cnt >> 2;
1058 }
1059 }
1060 }
1061
1062
advance_eg_channels(FM_CH * CH,unsigned int eg_cnt)1063 INLINE void advance_eg_channels(FM_CH *CH, unsigned int eg_cnt)
1064 {
1065 unsigned int i = 6; /* six channels */
1066 unsigned int j;
1067 FM_SLOT *SLOT;
1068
1069 do
1070 {
1071 SLOT = &CH->SLOT[SLOT1];
1072 j = 4; /* four operators per channel */
1073 do
1074 {
1075 switch(SLOT->state)
1076 {
1077 case EG_ATT: /* attack phase */
1078 {
1079 if (!(eg_cnt & ((1<<SLOT->eg_sh_ar)-1)))
1080 {
1081 /* update attenuation level */
1082 SLOT->volume += (~SLOT->volume * (eg_inc[SLOT->eg_sel_ar + ((eg_cnt>>SLOT->eg_sh_ar)&7)]))>>4;
1083
1084 /* check phase transition*/
1085 if (SLOT->volume <= MIN_ATT_INDEX)
1086 {
1087 SLOT->volume = MIN_ATT_INDEX;
1088 SLOT->state = (SLOT->sl == MIN_ATT_INDEX) ? EG_SUS : EG_DEC; /* special case where SL=0 */
1089 }
1090
1091 /* recalculate EG output */
1092 if ((SLOT->ssg&0x08) && (SLOT->ssgn ^ (SLOT->ssg&0x04))) /* SSG-EG Output Inversion */
1093 SLOT->vol_out = ((UINT32)(0x200 - SLOT->volume) & MAX_ATT_INDEX) + SLOT->tl;
1094 else
1095 SLOT->vol_out = (UINT32)SLOT->volume + SLOT->tl;
1096 }
1097 break;
1098 }
1099
1100 case EG_DEC: /* decay phase */
1101 {
1102 if (!(eg_cnt & ((1<<SLOT->eg_sh_d1r)-1)))
1103 {
1104 /* SSG EG type */
1105 if (SLOT->ssg&0x08)
1106 {
1107 /* update attenuation level */
1108 if (SLOT->volume < 0x200)
1109 {
1110 SLOT->volume += 4 * eg_inc[SLOT->eg_sel_d1r + ((eg_cnt>>SLOT->eg_sh_d1r)&7)];
1111
1112 /* recalculate EG output */
1113 if (SLOT->ssgn ^ (SLOT->ssg&0x04)) /* SSG-EG Output Inversion */
1114 SLOT->vol_out = ((UINT32)(0x200 - SLOT->volume) & MAX_ATT_INDEX) + SLOT->tl;
1115 else
1116 SLOT->vol_out = (UINT32)SLOT->volume + SLOT->tl;
1117 }
1118 }
1119 else
1120 {
1121 /* update attenuation level */
1122 SLOT->volume += eg_inc[SLOT->eg_sel_d1r + ((eg_cnt>>SLOT->eg_sh_d1r)&7)];
1123
1124 /* recalculate EG output */
1125 SLOT->vol_out = (UINT32)SLOT->volume + SLOT->tl;
1126 }
1127
1128 /* check phase transition*/
1129 if (SLOT->volume >= (INT32)(SLOT->sl))
1130 SLOT->state = EG_SUS;
1131 }
1132 break;
1133 }
1134
1135 case EG_SUS: /* sustain phase */
1136 {
1137 if (!(eg_cnt & ((1<<SLOT->eg_sh_d2r)-1)))
1138 {
1139 /* SSG EG type */
1140 if (SLOT->ssg&0x08)
1141 {
1142 /* update attenuation level */
1143 if (SLOT->volume < 0x200)
1144 {
1145 SLOT->volume += 4 * eg_inc[SLOT->eg_sel_d2r + ((eg_cnt>>SLOT->eg_sh_d2r)&7)];
1146
1147 /* recalculate EG output */
1148 if (SLOT->ssgn ^ (SLOT->ssg&0x04)) /* SSG-EG Output Inversion */
1149 SLOT->vol_out = ((UINT32)(0x200 - SLOT->volume) & MAX_ATT_INDEX) + SLOT->tl;
1150 else
1151 SLOT->vol_out = (UINT32)SLOT->volume + SLOT->tl;
1152 }
1153 }
1154 else
1155 {
1156 /* update attenuation level */
1157 SLOT->volume += eg_inc[SLOT->eg_sel_d2r + ((eg_cnt>>SLOT->eg_sh_d2r)&7)];
1158
1159 /* check phase transition*/
1160 if ( SLOT->volume >= MAX_ATT_INDEX )
1161 SLOT->volume = MAX_ATT_INDEX;
1162 /* do not change SLOT->state (verified on real chip) */
1163
1164 /* recalculate EG output */
1165 SLOT->vol_out = (UINT32)SLOT->volume + SLOT->tl;
1166 }
1167 }
1168 break;
1169 }
1170
1171 case EG_REL: /* release phase */
1172 {
1173 if (!(eg_cnt & ((1<<SLOT->eg_sh_rr)-1)))
1174 {
1175 /* SSG EG type */
1176 if (SLOT->ssg&0x08)
1177 {
1178 /* update attenuation level */
1179 if (SLOT->volume < 0x200)
1180 SLOT->volume += 4 * eg_inc[SLOT->eg_sel_rr + ((eg_cnt>>SLOT->eg_sh_rr)&7)];
1181
1182 /* check phase transition */
1183 if (SLOT->volume >= 0x200)
1184 {
1185 SLOT->volume = MAX_ATT_INDEX;
1186 SLOT->state = EG_OFF;
1187 }
1188 }
1189 else
1190 {
1191 /* update attenuation level */
1192 SLOT->volume += eg_inc[SLOT->eg_sel_rr + ((eg_cnt>>SLOT->eg_sh_rr)&7)];
1193
1194 /* check phase transition*/
1195 if (SLOT->volume >= MAX_ATT_INDEX)
1196 {
1197 SLOT->volume = MAX_ATT_INDEX;
1198 SLOT->state = EG_OFF;
1199 }
1200 }
1201
1202 /* recalculate EG output */
1203 SLOT->vol_out = (UINT32)SLOT->volume + SLOT->tl;
1204
1205 }
1206 break;
1207 }
1208 }
1209
1210 /* next slot */
1211 SLOT++;
1212 } while (--j);
1213
1214 /* next channel */
1215 CH++;
1216 } while (--i);
1217 }
1218
1219 /* SSG-EG update process */
1220 /* The behavior is based upon Nemesis tests on real hardware */
1221 /* This is actually executed before each samples */
update_ssg_eg_channels(FM_CH * CH)1222 INLINE void update_ssg_eg_channels(FM_CH *CH)
1223 {
1224 unsigned int i = 6; /* six channels */
1225 unsigned int j;
1226 FM_SLOT *SLOT;
1227
1228 do
1229 {
1230 j = 4; /* four operators per channel */
1231 SLOT = &CH->SLOT[SLOT1];
1232
1233 do
1234 {
1235 /* detect SSG-EG transition */
1236 /* this is not required during release phase as the attenuation has been forced to MAX and output invert flag is not used */
1237 /* if an Attack Phase is programmed, inversion can occur on each sample */
1238 if ((SLOT->ssg & 0x08) && (SLOT->volume >= 0x200) && (SLOT->state > EG_REL))
1239 {
1240 if (SLOT->ssg & 0x01) /* bit 0 = hold SSG-EG */
1241 {
1242 /* set inversion flag */
1243 if (SLOT->ssg & 0x02)
1244 SLOT->ssgn = 4;
1245
1246 /* force attenuation level during decay phases */
1247 if ((SLOT->state != EG_ATT) && !(SLOT->ssgn ^ (SLOT->ssg & 0x04)))
1248 SLOT->volume = MAX_ATT_INDEX;
1249 }
1250 else /* loop SSG-EG */
1251 {
1252 /* toggle output inversion flag or reset Phase Generator */
1253 if (SLOT->ssg & 0x02)
1254 SLOT->ssgn ^= 4;
1255 else
1256 SLOT->phase = 0;
1257
1258 /* same as Key ON */
1259 if (SLOT->state != EG_ATT)
1260 {
1261 if ((SLOT->ar + SLOT->ksr) < 94 /*32+62*/)
1262 {
1263 SLOT->state = (SLOT->volume <= MIN_ATT_INDEX) ? ((SLOT->sl == MIN_ATT_INDEX) ? EG_SUS : EG_DEC) : EG_ATT;
1264 }
1265 else
1266 {
1267 /* Attack Rate is maximal: directly switch to Decay or Substain */
1268 SLOT->volume = MIN_ATT_INDEX;
1269 SLOT->state = (SLOT->sl == MIN_ATT_INDEX) ? EG_SUS : EG_DEC;
1270 }
1271 }
1272 }
1273
1274 /* recalculate EG output */
1275 if (SLOT->ssgn ^ (SLOT->ssg&0x04))
1276 SLOT->vol_out = ((UINT32)(0x200 - SLOT->volume) & MAX_ATT_INDEX) + SLOT->tl;
1277 else
1278 SLOT->vol_out = (UINT32)SLOT->volume + SLOT->tl;
1279 }
1280
1281 /* next slot */
1282 SLOT++;
1283 } while (--j);
1284
1285 /* next channel */
1286 CH++;
1287 } while (--i);
1288 }
1289
update_phase_lfo_slot(FM_SLOT * SLOT,UINT32 pm,UINT8 kc,UINT32 fc)1290 INLINE void update_phase_lfo_slot(FM_SLOT *SLOT, UINT32 pm, UINT8 kc, UINT32 fc)
1291 {
1292 INT32 lfo_fn_offset = lfo_pm_table[((fc & 0x7f0) << 4) + pm];
1293
1294 if (lfo_fn_offset) /* LFO phase modulation active */
1295 {
1296 /* block is not modified by LFO PM */
1297 UINT8 blk = fc >> 11;
1298
1299 /* LFO works with one more bit of a precision (12-bit) */
1300 fc = ((fc << 1) + lfo_fn_offset) & 0xfff;
1301
1302 /* (frequency) phase increment counter (17-bit) */
1303 fc = (((fc << blk) >> 2) + SLOT->DT[kc]) & DT_MASK;
1304
1305 /* update phase */
1306 SLOT->phase += ((fc * SLOT->mul) >> 1);
1307 }
1308 else /* LFO phase modulation = zero */
1309 {
1310 SLOT->phase += SLOT->Incr;
1311 }
1312 }
1313
update_phase_lfo_channel(FM_CH * CH)1314 INLINE void update_phase_lfo_channel(FM_CH *CH)
1315 {
1316 UINT32 fc = CH->block_fnum;
1317
1318 INT32 lfo_fn_offset = lfo_pm_table[((fc & 0x7f0) << 4) + CH->pms + ym2612.OPN.LFO_PM];
1319
1320 if (lfo_fn_offset) /* LFO phase modulation active */
1321 {
1322 UINT32 finc;
1323
1324 /* block & keyscale code are not modified by LFO PM */
1325 UINT8 blk = fc >> 11;
1326 UINT8 kc = CH->kcode;
1327
1328 /* LFO works with one more bit of a precision (12-bit) */
1329 fc = ((fc << 1) + lfo_fn_offset) & 0xfff;
1330
1331 /* (frequency) phase increment counter (17-bit) */
1332 fc = (fc << blk) >> 2;
1333
1334 /* apply DETUNE & MUL operator specific values */
1335 finc = (fc + CH->SLOT[SLOT1].DT[kc]) & DT_MASK;
1336 CH->SLOT[SLOT1].phase += ((finc * CH->SLOT[SLOT1].mul) >> 1);
1337
1338 finc = (fc + CH->SLOT[SLOT2].DT[kc]) & DT_MASK;
1339 CH->SLOT[SLOT2].phase += ((finc * CH->SLOT[SLOT2].mul) >> 1);
1340
1341 finc = (fc + CH->SLOT[SLOT3].DT[kc]) & DT_MASK;
1342 CH->SLOT[SLOT3].phase += ((finc * CH->SLOT[SLOT3].mul) >> 1);
1343
1344 finc = (fc + CH->SLOT[SLOT4].DT[kc]) & DT_MASK;
1345 CH->SLOT[SLOT4].phase += ((finc * CH->SLOT[SLOT4].mul) >> 1);
1346 }
1347 else /* LFO phase modulation = zero */
1348 {
1349 CH->SLOT[SLOT1].phase += CH->SLOT[SLOT1].Incr;
1350 CH->SLOT[SLOT2].phase += CH->SLOT[SLOT2].Incr;
1351 CH->SLOT[SLOT3].phase += CH->SLOT[SLOT3].Incr;
1352 CH->SLOT[SLOT4].phase += CH->SLOT[SLOT4].Incr;
1353 }
1354 }
1355
1356 /* update phase increment and envelope generator */
refresh_fc_eg_slot(FM_SLOT * SLOT,unsigned int fc,unsigned int kc)1357 INLINE void refresh_fc_eg_slot(FM_SLOT *SLOT , unsigned int fc , unsigned int kc )
1358 {
1359 /* add detune value */
1360 fc += SLOT->DT[kc];
1361
1362 /* (frequency) phase overflow (credits to Nemesis) */
1363 fc &= DT_MASK;
1364
1365 /* (frequency) phase increment counter */
1366 SLOT->Incr = (fc * SLOT->mul) >> 1;
1367
1368 /* ksr */
1369 kc = kc >> SLOT->KSR;
1370
1371 if( SLOT->ksr != kc )
1372 {
1373 SLOT->ksr = kc;
1374
1375 /* recalculate envelope generator rates */
1376 if ((SLOT->ar + kc) < (32+62))
1377 {
1378 SLOT->eg_sh_ar = eg_rate_shift [SLOT->ar + kc ];
1379 SLOT->eg_sel_ar = eg_rate_select[SLOT->ar + kc ];
1380 }
1381 else
1382 {
1383 /* verified by Nemesis on real hardware (Attack phase is blocked) */
1384 SLOT->eg_sh_ar = 0;
1385 SLOT->eg_sel_ar = 18*RATE_STEPS;
1386 }
1387
1388 SLOT->eg_sh_d1r = eg_rate_shift [SLOT->d1r + kc];
1389 SLOT->eg_sel_d1r= eg_rate_select[SLOT->d1r + kc];
1390
1391 SLOT->eg_sh_d2r = eg_rate_shift [SLOT->d2r + kc];
1392 SLOT->eg_sel_d2r= eg_rate_select[SLOT->d2r + kc];
1393
1394 SLOT->eg_sh_rr = eg_rate_shift [SLOT->rr + kc];
1395 SLOT->eg_sel_rr = eg_rate_select[SLOT->rr + kc];
1396 }
1397 }
1398
1399 /* update phase increment counters */
refresh_fc_eg_chan(FM_CH * CH)1400 INLINE void refresh_fc_eg_chan(FM_CH *CH )
1401 {
1402 if( CH->SLOT[SLOT1].Incr==-1)
1403 {
1404 int fc = CH->fc;
1405 int kc = CH->kcode;
1406 refresh_fc_eg_slot(&CH->SLOT[SLOT1] , fc , kc );
1407 refresh_fc_eg_slot(&CH->SLOT[SLOT2] , fc , kc );
1408 refresh_fc_eg_slot(&CH->SLOT[SLOT3] , fc , kc );
1409 refresh_fc_eg_slot(&CH->SLOT[SLOT4] , fc , kc );
1410 }
1411 }
1412
1413 #define volume_calc(OP) ((OP)->vol_out + (AM & (OP)->AMmask))
1414
op_calc(UINT32 phase,unsigned int env,unsigned int pm,unsigned int opmask)1415 INLINE signed int op_calc(UINT32 phase, unsigned int env, unsigned int pm, unsigned int opmask)
1416 {
1417 UINT32 p = (env<<3) + sin_tab[ ( (phase >> SIN_BITS) + (pm >> 1) ) & SIN_MASK ];
1418
1419 if (p >= TL_TAB_LEN)
1420 return 0;
1421 return (tl_tab[p] & opmask);
1422 }
1423
op_calc1(UINT32 phase,unsigned int env,unsigned int pm,unsigned int opmask)1424 INLINE signed int op_calc1(UINT32 phase, unsigned int env, unsigned int pm, unsigned int opmask)
1425 {
1426 UINT32 p = (env<<3) + sin_tab[ ( ( phase >> SIN_BITS ) + pm ) & SIN_MASK ];
1427
1428 if (p >= TL_TAB_LEN)
1429 return 0;
1430 return (tl_tab[p] & opmask);
1431 }
1432
chan_calc(FM_CH * CH,int num)1433 INLINE void chan_calc(FM_CH *CH, int num)
1434 {
1435 do
1436 {
1437 INT32 out = 0;
1438 UINT32 AM = ym2612.OPN.LFO_AM >> CH->ams;
1439 unsigned int eg_out = volume_calc(&CH->SLOT[SLOT1]);
1440 UINT32 *mask = op_mask[CH->ALGO];
1441
1442 m2 = c1 = c2 = mem = 0;
1443
1444 *CH->mem_connect = CH->mem_value; /* restore delayed sample (MEM) value to m2 or c2 */
1445
1446 if( eg_out < ENV_QUIET ) /* SLOT 1 */
1447 {
1448 if (CH->FB < SIN_BITS)
1449 out = (CH->op1_out[0] + CH->op1_out[1]) >> CH->FB;
1450
1451 out = op_calc1(CH->SLOT[SLOT1].phase, eg_out, out, mask[0]);
1452 }
1453
1454 CH->op1_out[0] = CH->op1_out[1];
1455 CH->op1_out[1] = out;
1456
1457 if( !CH->connect1 ){
1458 /* algorithm 5 */
1459 mem = c1 = c2 = out;
1460 }else{
1461 /* other algorithms */
1462 *CH->connect1 = out;
1463 }
1464
1465 eg_out = volume_calc(&CH->SLOT[SLOT3]);
1466 if( eg_out < ENV_QUIET ) /* SLOT 3 */
1467 *CH->connect3 += op_calc(CH->SLOT[SLOT3].phase, eg_out, m2, mask[2]);
1468
1469 eg_out = volume_calc(&CH->SLOT[SLOT2]);
1470 if( eg_out < ENV_QUIET ) /* SLOT 2 */
1471 *CH->connect2 += op_calc(CH->SLOT[SLOT2].phase, eg_out, c1, mask[1]);
1472
1473 eg_out = volume_calc(&CH->SLOT[SLOT4]);
1474 if( eg_out < ENV_QUIET ) /* SLOT 4 */
1475 *CH->connect4 += op_calc(CH->SLOT[SLOT4].phase, eg_out, c2, mask[3]);
1476
1477 /* store current MEM */
1478 CH->mem_value = mem;
1479
1480 /* update phase counters AFTER output calculations */
1481 if (CH->pms)
1482 {
1483 /* 3-slot mode */
1484 if ((ym2612.OPN.ST.mode & 0xC0) && (CH == &ym2612.CH[2]))
1485 {
1486 /* keyscale code is not modifiedby LFO */
1487 UINT8 kc = ym2612.CH[2].kcode;
1488 UINT32 pm = ym2612.CH[2].pms + ym2612.OPN.LFO_PM;
1489 update_phase_lfo_slot(&ym2612.CH[2].SLOT[SLOT1], pm, kc, ym2612.OPN.SL3.block_fnum[1]);
1490 update_phase_lfo_slot(&ym2612.CH[2].SLOT[SLOT2], pm, kc, ym2612.OPN.SL3.block_fnum[2]);
1491 update_phase_lfo_slot(&ym2612.CH[2].SLOT[SLOT3], pm, kc, ym2612.OPN.SL3.block_fnum[0]);
1492 update_phase_lfo_slot(&ym2612.CH[2].SLOT[SLOT4], pm, kc, ym2612.CH[2].block_fnum);
1493 }
1494 else
1495 {
1496 update_phase_lfo_channel(CH);
1497 }
1498 }
1499 else /* no LFO phase modulation */
1500 {
1501 CH->SLOT[SLOT1].phase += CH->SLOT[SLOT1].Incr;
1502 CH->SLOT[SLOT2].phase += CH->SLOT[SLOT2].Incr;
1503 CH->SLOT[SLOT3].phase += CH->SLOT[SLOT3].Incr;
1504 CH->SLOT[SLOT4].phase += CH->SLOT[SLOT4].Incr;
1505 }
1506
1507 /* next channel */
1508 CH++;
1509 } while (--num);
1510 }
1511
1512 /* write a OPN mode register 0x20-0x2f */
OPNWriteMode(int r,int v)1513 INLINE void OPNWriteMode(int r, int v)
1514 {
1515 UINT8 c;
1516 FM_CH *CH;
1517
1518 switch(r){
1519 case 0x21: /* Test */
1520 break;
1521
1522 case 0x22: /* LFO FREQ */
1523 if (v&8) /* LFO enabled ? */
1524 {
1525 ym2612.OPN.lfo_timer_overflow = lfo_samples_per_step[v&7];
1526 }
1527 else
1528 {
1529 /* hold LFO waveform in reset state */
1530 ym2612.OPN.lfo_timer_overflow = 0;
1531 ym2612.OPN.lfo_timer = 0;
1532 ym2612.OPN.lfo_cnt = 0;
1533 ym2612.OPN.LFO_PM = 0;
1534 ym2612.OPN.LFO_AM = 126;
1535 }
1536 break;
1537 case 0x24: /* timer A High */
1538 ym2612.OPN.ST.TA = (ym2612.OPN.ST.TA & 0x03)|(((int)v)<<2);
1539 ym2612.OPN.ST.TAL = 1024 - ym2612.OPN.ST.TA;
1540 break;
1541 case 0x25: /* timer A Low */
1542 ym2612.OPN.ST.TA = (ym2612.OPN.ST.TA & 0x3fc)|(v&3);
1543 ym2612.OPN.ST.TAL = 1024 - ym2612.OPN.ST.TA;
1544 break;
1545 case 0x26: /* timer B */
1546 ym2612.OPN.ST.TB = v;
1547 ym2612.OPN.ST.TBL = (256 - v) << 4;
1548 break;
1549 case 0x27: /* mode, timer control */
1550 set_timers(v);
1551 break;
1552 case 0x28: /* key on / off */
1553 c = v & 0x03;
1554 if( c == 3 ) break;
1555 if (v&0x04) c+=3; /* CH 4-6 */
1556 CH = &ym2612.CH[c];
1557 if (v&0x10) FM_KEYON(CH,SLOT1); else FM_KEYOFF(CH,SLOT1);
1558 if (v&0x20) FM_KEYON(CH,SLOT2); else FM_KEYOFF(CH,SLOT2);
1559 if (v&0x40) FM_KEYON(CH,SLOT3); else FM_KEYOFF(CH,SLOT3);
1560 if (v&0x80) FM_KEYON(CH,SLOT4); else FM_KEYOFF(CH,SLOT4);
1561 break;
1562 }
1563 }
1564
1565 /* write a OPN register (0x30-0xff) */
OPNWriteReg(int r,int v)1566 INLINE void OPNWriteReg(int r, int v)
1567 {
1568 FM_CH *CH;
1569 FM_SLOT *SLOT;
1570
1571 UINT8 c = OPN_CHAN(r);
1572
1573 if (c == 3) return; /* 0xX3,0xX7,0xXB,0xXF */
1574
1575 if (r >= 0x100) c+=3;
1576
1577 CH = &ym2612.CH[c];
1578
1579 SLOT = &(CH->SLOT[OPN_SLOT(r)]);
1580
1581 switch( r & 0xf0 ) {
1582 case 0x30: /* DET , MUL */
1583 set_det_mul(CH,SLOT,v);
1584 break;
1585
1586 case 0x40: /* TL */
1587 set_tl(SLOT,v);
1588 break;
1589
1590 case 0x50: /* KS, AR */
1591 set_ar_ksr(CH,SLOT,v);
1592 break;
1593
1594 case 0x60: /* bit7 = AM ENABLE, DR */
1595 set_dr(SLOT,v);
1596 SLOT->AMmask = (v&0x80) ? ~0 : 0;
1597 break;
1598
1599 case 0x70: /* SR */
1600 set_sr(SLOT,v);
1601 break;
1602
1603 case 0x80: /* SL, RR */
1604 set_sl_rr(SLOT,v);
1605 break;
1606
1607 case 0x90: /* SSG-EG */
1608 SLOT->ssg = v&0x0f;
1609
1610 /* recalculate EG output */
1611 if (SLOT->state > EG_REL)
1612 {
1613 if ((SLOT->ssg&0x08) && (SLOT->ssgn ^ (SLOT->ssg&0x04)))
1614 SLOT->vol_out = ((UINT32)(0x200 - SLOT->volume) & MAX_ATT_INDEX) + SLOT->tl;
1615 else
1616 SLOT->vol_out = (UINT32)SLOT->volume + SLOT->tl;
1617 }
1618
1619 /* SSG-EG envelope shapes :
1620
1621 E AtAlH
1622 1 0 0 0 \\\\
1623
1624 1 0 0 1 \___
1625
1626 1 0 1 0 \/\/
1627 ___
1628 1 0 1 1 \
1629
1630 1 1 0 0 ////
1631 ___
1632 1 1 0 1 /
1633
1634 1 1 1 0 /\/\
1635
1636 1 1 1 1 /___
1637
1638
1639 E = SSG-EG enable
1640
1641
1642 The shapes are generated using Attack, Decay and Sustain phases.
1643
1644 Each single character in the diagrams above represents this whole
1645 sequence:
1646
1647 - when KEY-ON = 1, normal Attack phase is generated (*without* any
1648 difference when compared to normal mode),
1649
1650 - later, when envelope level reaches minimum level (max volume),
1651 the EG switches to Decay phase (which works with bigger steps
1652 when compared to normal mode - see below),
1653
1654 - later when envelope level passes the SL level,
1655 the EG swithes to Sustain phase (which works with bigger steps
1656 when compared to normal mode - see below),
1657
1658 - finally when envelope level reaches maximum level (min volume),
1659 the EG switches to Attack phase again (depends on actual waveform).
1660
1661 Important is that when switch to Attack phase occurs, the phase counter
1662 of that operator will be zeroed-out (as in normal KEY-ON) but not always.
1663 (I havent found the rule for that - perhaps only when the output level is low)
1664
1665 The difference (when compared to normal Envelope Generator mode) is
1666 that the resolution in Decay and Sustain phases is 4 times lower;
1667 this results in only 256 steps instead of normal 1024.
1668 In other words:
1669 when SSG-EG is disabled, the step inside of the EG is one,
1670 when SSG-EG is enabled, the step is four (in Decay and Sustain phases).
1671
1672 Times between the level changes are the same in both modes.
1673
1674
1675 Important:
1676 Decay 1 Level (so called SL) is compared to actual SSG-EG output, so
1677 it is the same in both SSG and no-SSG modes, with this exception:
1678
1679 when the SSG-EG is enabled and is generating raising levels
1680 (when the EG output is inverted) the SL will be found at wrong level !!!
1681 For example, when SL=02:
1682 0 -6 = -6dB in non-inverted EG output
1683 96-6 = -90dB in inverted EG output
1684 Which means that EG compares its level to SL as usual, and that the
1685 output is simply inverted afterall.
1686
1687
1688 The Yamaha's manuals say that AR should be set to 0x1f (max speed).
1689 That is not necessary, but then EG will be generating Attack phase.
1690
1691 */
1692 break;
1693
1694 case 0xa0:
1695 switch( OPN_SLOT(r) ){
1696 case 0: /* 0xa0-0xa2 : FNUM1 */
1697 {
1698 UINT32 fn = (((UINT32)((ym2612.OPN.ST.fn_h)&7))<<8) + v;
1699 UINT8 blk = ym2612.OPN.ST.fn_h>>3;
1700 /* keyscale code */
1701 CH->kcode = (blk<<2) | opn_fktable[fn >> 7];
1702 /* phase increment counter */
1703 CH->fc = (fn<<blk)>>1;
1704
1705 /* store fnum in clear form for LFO PM calculations */
1706 CH->block_fnum = (blk<<11) | fn;
1707
1708 CH->SLOT[SLOT1].Incr=-1;
1709 break;
1710 }
1711 case 1: /* 0xa4-0xa6 : FNUM2,BLK */
1712 ym2612.OPN.ST.fn_h = v&0x3f;
1713 break;
1714 case 2: /* 0xa8-0xaa : 3CH FNUM1 */
1715 if(r < 0x100)
1716 {
1717 UINT32 fn = (((UINT32)(ym2612.OPN.SL3.fn_h&7))<<8) + v;
1718 UINT8 blk = ym2612.OPN.SL3.fn_h>>3;
1719 /* keyscale code */
1720 ym2612.OPN.SL3.kcode[c]= (blk<<2) | opn_fktable[fn >> 7];
1721 /* phase increment counter */
1722 ym2612.OPN.SL3.fc[c] = (fn<<blk)>>1;
1723 ym2612.OPN.SL3.block_fnum[c] = (blk<<11) | fn;
1724 ym2612.CH[2].SLOT[SLOT1].Incr=-1;
1725 }
1726 break;
1727 case 3: /* 0xac-0xae : 3CH FNUM2,BLK */
1728 if(r < 0x100)
1729 ym2612.OPN.SL3.fn_h = v&0x3f;
1730 break;
1731 }
1732 break;
1733
1734 case 0xb0:
1735 switch( OPN_SLOT(r) ){
1736 case 0: /* 0xb0-0xb2 : FB,ALGO */
1737 {
1738 CH->ALGO = v&7;
1739 CH->FB = SIN_BITS - ((v>>3)&7);
1740 setup_connection( CH, c );
1741 break;
1742 }
1743 case 1: /* 0xb4-0xb6 : L , R , AMS , PMS */
1744 /* b0-2 PMS */
1745 CH->pms = (v & 7) * 32; /* CH->pms = PM depth * 32 (index in lfo_pm_table) */
1746
1747 /* b4-5 AMS */
1748 CH->ams = lfo_ams_depth_shift[(v>>4) & 0x03];
1749
1750 /* PAN : b7 = L, b6 = R */
1751 ym2612.OPN.pan[ c*2 ] = (v & 0x80) ? 0xffffffff : 0;
1752 ym2612.OPN.pan[ c*2+1 ] = (v & 0x40) ? 0xffffffff : 0;
1753 break;
1754 }
1755 break;
1756 }
1757 }
1758
reset_channels(FM_CH * CH,int num)1759 static void reset_channels(FM_CH *CH , int num )
1760 {
1761 int c,s;
1762
1763 for( c = 0 ; c < num ; c++ )
1764 {
1765 CH[c].mem_value = 0;
1766 CH[c].op1_out[0] = 0;
1767 CH[c].op1_out[1] = 0;
1768 for(s = 0 ; s < 4 ; s++ )
1769 {
1770 CH[c].SLOT[s].Incr = -1;
1771 CH[c].SLOT[s].key = 0;
1772 CH[c].SLOT[s].phase = 0;
1773 CH[c].SLOT[s].ssgn = 0;
1774 CH[c].SLOT[s].state = EG_OFF;
1775 CH[c].SLOT[s].volume = MAX_ATT_INDEX;
1776 CH[c].SLOT[s].vol_out = MAX_ATT_INDEX;
1777 }
1778 }
1779 }
1780
1781 /* initialize generic tables */
init_tables(void)1782 static void init_tables(void)
1783 {
1784 signed int d,i,x;
1785 signed int n;
1786 double o,m;
1787
1788 /* build Linear Power Table */
1789 for (x=0; x<TL_RES_LEN; x++)
1790 {
1791 m = (1<<16) / pow(2,(x+1) * (ENV_STEP/4.0) / 8.0);
1792 m = floor(m);
1793
1794 /* we never reach (1<<16) here due to the (x+1) */
1795 /* result fits within 16 bits at maximum */
1796
1797 n = (int)m; /* 16 bits here */
1798 n >>= 4; /* 12 bits here */
1799 if (n&1) /* round to nearest */
1800 n = (n>>1)+1;
1801 else
1802 n = n>>1;
1803 /* 11 bits here (rounded) */
1804 n <<= 2; /* 13 bits here (as in real chip) */
1805
1806 /* 14 bits (with sign bit) */
1807 tl_tab[ x*2 + 0 ] = n;
1808 tl_tab[ x*2 + 1 ] = -tl_tab[ x*2 + 0 ];
1809
1810 /* one entry in the 'Power' table use the following format, xxxxxyyyyyyyys with: */
1811 /* s = sign bit */
1812 /* yyyyyyyy = 8-bits decimal part (0-TL_RES_LEN) */
1813 /* xxxxx = 5-bits integer 'shift' value (0-31) but, since Power table output is 13 bits, */
1814 /* any value above 13 (included) would be discarded. */
1815 for (i=1; i<13; i++)
1816 {
1817 tl_tab[ x*2+0 + i*2*TL_RES_LEN ] = tl_tab[ x*2+0 ]>>i;
1818 tl_tab[ x*2+1 + i*2*TL_RES_LEN ] = -tl_tab[ x*2+0 + i*2*TL_RES_LEN ];
1819 }
1820 }
1821
1822 /* build Logarithmic Sinus table */
1823 for (i=0; i<SIN_LEN; i++)
1824 {
1825 /* non-standard sinus */
1826 m = sin( ((i*2)+1) * M_PI / SIN_LEN ); /* checked against the real chip */
1827 /* we never reach zero here due to ((i*2)+1) */
1828
1829 if (m>0.0)
1830 o = 8*log(1.0/m)/log(2); /* convert to 'decibels' */
1831 else
1832 o = 8*log(-1.0/m)/log(2); /* convert to 'decibels' */
1833
1834 o = o / (ENV_STEP/4);
1835
1836 n = (int)(2.0*o);
1837 if (n&1) /* round to nearest */
1838 n = (n>>1)+1;
1839 else
1840 n = n>>1;
1841
1842 /* 13-bits (8.5) value is formatted for above 'Power' table */
1843 sin_tab[ i ] = n*2 + (m>=0.0? 0: 1 );
1844 }
1845
1846 /* build LFO PM modulation table */
1847 for(i = 0; i < 8; i++) /* 8 PM depths */
1848 {
1849 UINT8 fnum;
1850 for (fnum=0; fnum<128; fnum++) /* 7 bits meaningful of F-NUMBER */
1851 {
1852 UINT8 value;
1853 UINT8 step;
1854 UINT32 offset_depth = i;
1855 UINT32 offset_fnum_bit;
1856 UINT32 bit_tmp;
1857
1858 for (step=0; step<8; step++)
1859 {
1860 value = 0;
1861 for (bit_tmp=0; bit_tmp<7; bit_tmp++) /* 7 bits */
1862 {
1863 if (fnum & (1<<bit_tmp)) /* only if bit "bit_tmp" is set */
1864 {
1865 offset_fnum_bit = bit_tmp * 8;
1866 value += lfo_pm_output[offset_fnum_bit + offset_depth][step];
1867 }
1868 }
1869 /* 32 steps for LFO PM (sinus) */
1870 lfo_pm_table[(fnum*32*8) + (i*32) + step + 0] = value;
1871 lfo_pm_table[(fnum*32*8) + (i*32) +(step^7)+ 8] = value;
1872 lfo_pm_table[(fnum*32*8) + (i*32) + step +16] = -value;
1873 lfo_pm_table[(fnum*32*8) + (i*32) +(step^7)+24] = -value;
1874 }
1875 }
1876 }
1877
1878 /* build DETUNE table */
1879 for (d = 0;d <= 3;d++)
1880 {
1881 for (i = 0;i <= 31;i++)
1882 {
1883 ym2612.OPN.ST.dt_tab[d][i] = (INT32) dt_tab[d*32 + i];
1884 ym2612.OPN.ST.dt_tab[d+4][i] = -ym2612.OPN.ST.dt_tab[d][i];
1885 }
1886 }
1887
1888 /* build default OP mask table */
1889 for (i = 0;i < 8;i++)
1890 {
1891 for (d = 0;d < 4;d++)
1892 {
1893 op_mask[i][d] = 0xffffffff;
1894 }
1895 }
1896
1897 }
1898
1899
1900
1901 /* initialize ym2612 emulator */
YM2612Init(void)1902 void YM2612Init(void)
1903 {
1904 memset(&ym2612,0,sizeof(YM2612));
1905 init_tables();
1906 }
1907
1908 /* reset OPN registers */
YM2612ResetChip(void)1909 void YM2612ResetChip(void)
1910 {
1911 int i;
1912
1913 ym2612.OPN.eg_timer = 0;
1914 ym2612.OPN.eg_cnt = 0;
1915
1916 ym2612.OPN.lfo_timer_overflow = 0;
1917 ym2612.OPN.lfo_timer = 0;
1918 ym2612.OPN.lfo_cnt = 0;
1919 ym2612.OPN.LFO_AM = 126;
1920 ym2612.OPN.LFO_PM = 0;
1921
1922 ym2612.OPN.ST.TAC = 0;
1923 ym2612.OPN.ST.TBC = 0;
1924
1925 ym2612.OPN.SL3.key_csm = 0;
1926
1927 ym2612.dacen = 0;
1928 ym2612.dacout = 0;
1929
1930 set_timers(0x30);
1931 ym2612.OPN.ST.TB = 0;
1932 ym2612.OPN.ST.TBL = 256 << 4;
1933 ym2612.OPN.ST.TA = 0;
1934 ym2612.OPN.ST.TAL = 1024;
1935
1936 reset_channels(&ym2612.CH[0] , 6 );
1937
1938 for(i = 0xb6 ; i >= 0xb4 ; i-- )
1939 {
1940 OPNWriteReg(i ,0xc0);
1941 OPNWriteReg(i|0x100,0xc0);
1942 }
1943 for(i = 0xb2 ; i >= 0x30 ; i-- )
1944 {
1945 OPNWriteReg(i ,0);
1946 OPNWriteReg(i|0x100,0);
1947 }
1948 }
1949
1950 /* ym2612 write */
1951 /* n = number */
1952 /* a = address */
1953 /* v = value */
YM2612Write(unsigned int a,unsigned int v)1954 void YM2612Write(unsigned int a, unsigned int v)
1955 {
1956 v &= 0xff; /* adjust to 8 bit bus */
1957
1958 switch( a )
1959 {
1960 case 0: /* address port 0 */
1961 ym2612.OPN.ST.address = v;
1962 break;
1963
1964 case 2: /* address port 1 */
1965 ym2612.OPN.ST.address = v | 0x100;
1966 break;
1967
1968 default: /* data port */
1969 {
1970 int addr = ym2612.OPN.ST.address; /* verified by Nemesis on real YM2612 */
1971 switch( addr & 0x1f0 )
1972 {
1973 case 0x20: /* 0x20-0x2f Mode */
1974 switch( addr )
1975 {
1976 case 0x2a: /* DAC data (ym2612) */
1977 ym2612.dacout = ((int)v - 0x80) << 6; /* convert to 14-bit output */
1978 break;
1979 case 0x2b: /* DAC Sel (ym2612) */
1980 /* b7 = dac enable */
1981 ym2612.dacen = v & 0x80;
1982 break;
1983 default: /* OPN section */
1984 /* write register */
1985 OPNWriteMode(addr,v);
1986 }
1987 break;
1988 default: /* 0x30-0xff OPN section */
1989 /* write register */
1990 OPNWriteReg(addr,v);
1991 }
1992 break;
1993 }
1994 }
1995 }
1996
YM2612Read(void)1997 unsigned int YM2612Read(void)
1998 {
1999 return ym2612.OPN.ST.status;
2000 }
2001
2002 /* Generate samples for ym2612 */
YM2612Update(int * buffer,int length)2003 void YM2612Update(int *buffer, int length)
2004 {
2005 int i;
2006 int lt,rt;
2007
2008 /* refresh PG increments and EG rates if required */
2009 refresh_fc_eg_chan(&ym2612.CH[0]);
2010 refresh_fc_eg_chan(&ym2612.CH[1]);
2011
2012 if (!(ym2612.OPN.ST.mode & 0xC0))
2013 {
2014 refresh_fc_eg_chan(&ym2612.CH[2]);
2015 }
2016 else
2017 {
2018 /* 3SLOT MODE (operator order is 0,1,3,2) */
2019 if(ym2612.CH[2].SLOT[SLOT1].Incr==-1)
2020 {
2021 refresh_fc_eg_slot(&ym2612.CH[2].SLOT[SLOT1] , ym2612.OPN.SL3.fc[1] , ym2612.OPN.SL3.kcode[1] );
2022 refresh_fc_eg_slot(&ym2612.CH[2].SLOT[SLOT2] , ym2612.OPN.SL3.fc[2] , ym2612.OPN.SL3.kcode[2] );
2023 refresh_fc_eg_slot(&ym2612.CH[2].SLOT[SLOT3] , ym2612.OPN.SL3.fc[0] , ym2612.OPN.SL3.kcode[0] );
2024 refresh_fc_eg_slot(&ym2612.CH[2].SLOT[SLOT4] , ym2612.CH[2].fc , ym2612.CH[2].kcode );
2025 }
2026 }
2027
2028 refresh_fc_eg_chan(&ym2612.CH[3]);
2029 refresh_fc_eg_chan(&ym2612.CH[4]);
2030 refresh_fc_eg_chan(&ym2612.CH[5]);
2031
2032 /* buffering */
2033 for(i=0; i<length; i++)
2034 {
2035 /* clear outputs */
2036 out_fm[0] = 0;
2037 out_fm[1] = 0;
2038 out_fm[2] = 0;
2039 out_fm[3] = 0;
2040 out_fm[4] = 0;
2041 out_fm[5] = 0;
2042
2043 /* update SSG-EG output */
2044 update_ssg_eg_channels(&ym2612.CH[0]);
2045
2046 /* calculate FM */
2047 if (!ym2612.dacen)
2048 {
2049 chan_calc(&ym2612.CH[0],6);
2050 }
2051 else
2052 {
2053 /* DAC Mode */
2054 out_fm[5] = ym2612.dacout;
2055 chan_calc(&ym2612.CH[0],5);
2056 }
2057
2058 /* advance LFO */
2059 advance_lfo();
2060
2061 /* EG is updated every 3 samples */
2062 ym2612.OPN.eg_timer++;
2063 if (ym2612.OPN.eg_timer >= 3)
2064 {
2065 /* reset EG timer */
2066 ym2612.OPN.eg_timer = 0;
2067
2068 /* increment EG counter */
2069 ym2612.OPN.eg_cnt++;
2070
2071 /* EG counter is 12-bit only and zero value is skipped (verified on real hardware) */
2072 if (ym2612.OPN.eg_cnt == 4096)
2073 ym2612.OPN.eg_cnt = 1;
2074
2075 /* advance envelope generator */
2076 advance_eg_channels(&ym2612.CH[0], ym2612.OPN.eg_cnt);
2077 }
2078
2079 /* channels accumulator output clipping (14-bit max) */
2080 if (out_fm[0] > 8191) out_fm[0] = 8191;
2081 else if (out_fm[0] < -8192) out_fm[0] = -8192;
2082 if (out_fm[1] > 8191) out_fm[1] = 8191;
2083 else if (out_fm[1] < -8192) out_fm[1] = -8192;
2084 if (out_fm[2] > 8191) out_fm[2] = 8191;
2085 else if (out_fm[2] < -8192) out_fm[2] = -8192;
2086 if (out_fm[3] > 8191) out_fm[3] = 8191;
2087 else if (out_fm[3] < -8192) out_fm[3] = -8192;
2088 if (out_fm[4] > 8191) out_fm[4] = 8191;
2089 else if (out_fm[4] < -8192) out_fm[4] = -8192;
2090 if (out_fm[5] > 8191) out_fm[5] = 8191;
2091 else if (out_fm[5] < -8192) out_fm[5] = -8192;
2092
2093 #ifdef USE_PER_SOUND_CHANNELS_CONFIG
2094 /* apply user volume scaling */
2095 if (config.md_ch_volumes[0] < 100) out_fm[0] = (out_fm[0] * config.md_ch_volumes[0]) / 100;
2096 if (config.md_ch_volumes[1] < 100) out_fm[1] = (out_fm[1] * config.md_ch_volumes[1]) / 100;
2097 if (config.md_ch_volumes[2] < 100) out_fm[2] = (out_fm[2] * config.md_ch_volumes[2]) / 100;
2098 if (config.md_ch_volumes[3] < 100) out_fm[3] = (out_fm[3] * config.md_ch_volumes[3]) / 100;
2099 if (config.md_ch_volumes[4] < 100) out_fm[4] = (out_fm[4] * config.md_ch_volumes[4]) / 100;
2100 if (config.md_ch_volumes[5] < 100) out_fm[5] = (out_fm[5] * config.md_ch_volumes[5]) / 100;
2101 #endif
2102
2103 /* stereo DAC output panning & mixing */
2104 lt = ((out_fm[0]) & ym2612.OPN.pan[0]);
2105 rt = ((out_fm[0]) & ym2612.OPN.pan[1]);
2106 lt += ((out_fm[1]) & ym2612.OPN.pan[2]);
2107 rt += ((out_fm[1]) & ym2612.OPN.pan[3]);
2108 lt += ((out_fm[2]) & ym2612.OPN.pan[4]);
2109 rt += ((out_fm[2]) & ym2612.OPN.pan[5]);
2110 lt += ((out_fm[3]) & ym2612.OPN.pan[6]);
2111 rt += ((out_fm[3]) & ym2612.OPN.pan[7]);
2112 lt += ((out_fm[4]) & ym2612.OPN.pan[8]);
2113 rt += ((out_fm[4]) & ym2612.OPN.pan[9]);
2114 lt += ((out_fm[5]) & ym2612.OPN.pan[10]);
2115 rt += ((out_fm[5]) & ym2612.OPN.pan[11]);
2116
2117 /* discrete YM2612 DAC */
2118 if (chip_type == YM2612_DISCRETE)
2119 {
2120 int i;
2121
2122 /* DAC 'ladder effect' */
2123 for (i=0; i<6; i++)
2124 {
2125 if (out_fm[i] < 0)
2126 {
2127 /* -4 offset (-3 when not muted) on negative channel output (9-bit) */
2128 lt -= ((4 - (ym2612.OPN.pan[(2*i)+0] & 1)) << 5);
2129 rt -= ((4 - (ym2612.OPN.pan[(2*i)+1] & 1)) << 5);
2130 }
2131 else
2132 {
2133 /* +4 offset (when muted or not) on positive channel output (9-bit) */
2134 lt += (4 << 5);
2135 rt += (4 << 5);
2136 }
2137 }
2138 }
2139
2140 /* buffering */
2141 *buffer++ = lt;
2142 *buffer++ = rt;
2143
2144 /* CSM mode: if CSM Key ON has occurred, CSM Key OFF need to be sent */
2145 /* only if Timer A does not overflow again (i.e CSM Key ON not set again) */
2146 ym2612.OPN.SL3.key_csm <<= 1;
2147
2148 /* timer A control */
2149 INTERNAL_TIMER_A();
2150
2151 /* CSM Mode Key ON still disabled */
2152 if (ym2612.OPN.SL3.key_csm & 2)
2153 {
2154 /* CSM Mode Key OFF (verified by Nemesis on real hardware) */
2155 FM_KEYOFF_CSM(&ym2612.CH[2],SLOT1);
2156 FM_KEYOFF_CSM(&ym2612.CH[2],SLOT2);
2157 FM_KEYOFF_CSM(&ym2612.CH[2],SLOT3);
2158 FM_KEYOFF_CSM(&ym2612.CH[2],SLOT4);
2159 ym2612.OPN.SL3.key_csm = 0;
2160 }
2161 }
2162
2163 /* timer B control */
2164 INTERNAL_TIMER_B(length);
2165 }
2166
YM2612Config(int type)2167 void YM2612Config(int type)
2168 {
2169 /* YM2612 chip type */
2170 chip_type = type;
2171
2172 /* carrier operator outputs bitmask */
2173 if (chip_type < YM2612_ENHANCED)
2174 {
2175 /* 9-bit DAC */
2176 op_mask[0][3] = 0xffffffe0;
2177 op_mask[1][3] = 0xffffffe0;
2178 op_mask[2][3] = 0xffffffe0;
2179 op_mask[3][3] = 0xffffffe0;
2180 op_mask[4][1] = 0xffffffe0;
2181 op_mask[4][3] = 0xffffffe0;
2182 op_mask[5][1] = 0xffffffe0;
2183 op_mask[5][2] = 0xffffffe0;
2184 op_mask[5][3] = 0xffffffe0;
2185 op_mask[6][1] = 0xffffffe0;
2186 op_mask[6][2] = 0xffffffe0;
2187 op_mask[6][3] = 0xffffffe0;
2188 op_mask[7][0] = 0xffffffe0;
2189 op_mask[7][1] = 0xffffffe0;
2190 op_mask[7][2] = 0xffffffe0;
2191 op_mask[7][3] = 0xffffffe0;
2192 }
2193 else
2194 {
2195 /* 14-bit DAC */
2196 op_mask[0][3] = 0xffffffff;
2197 op_mask[1][3] = 0xffffffff;
2198 op_mask[2][3] = 0xffffffff;
2199 op_mask[3][3] = 0xffffffff;
2200 op_mask[4][1] = 0xffffffff;
2201 op_mask[4][3] = 0xffffffff;
2202 op_mask[5][1] = 0xffffffff;
2203 op_mask[5][2] = 0xffffffff;
2204 op_mask[5][3] = 0xffffffff;
2205 op_mask[6][1] = 0xffffffff;
2206 op_mask[6][2] = 0xffffffff;
2207 op_mask[6][3] = 0xffffffff;
2208 op_mask[7][0] = 0xffffffff;
2209 op_mask[7][1] = 0xffffffff;
2210 op_mask[7][2] = 0xffffffff;
2211 op_mask[7][3] = 0xffffffff;
2212 }
2213 }
2214
YM2612LoadContext(unsigned char * state)2215 int YM2612LoadContext(unsigned char *state)
2216 {
2217 int c,s;
2218 uint8 index;
2219 int bufferptr = 0;
2220
2221 /* restore YM2612 context */
2222 load_param(&ym2612, sizeof(ym2612));
2223
2224 /* restore DT table address pointer for each channel slots */
2225 for (c=0; c<6; c++)
2226 {
2227 for (s=0; s<4; s++)
2228 {
2229 load_param(&index,sizeof(index));
2230 bufferptr += sizeof(index);
2231 ym2612.CH[c].SLOT[s].DT = ym2612.OPN.ST.dt_tab[index&7];
2232 }
2233 }
2234
2235 /* restore outputs connections */
2236 setup_connection(&ym2612.CH[0],0);
2237 setup_connection(&ym2612.CH[1],1);
2238 setup_connection(&ym2612.CH[2],2);
2239 setup_connection(&ym2612.CH[3],3);
2240 setup_connection(&ym2612.CH[4],4);
2241 setup_connection(&ym2612.CH[5],5);
2242
2243 return bufferptr;
2244 }
2245
YM2612SaveContext(unsigned char * state)2246 int YM2612SaveContext(unsigned char *state)
2247 {
2248 int c,s;
2249 uint8 index;
2250 int bufferptr = 0;
2251
2252 /* save YM2612 context */
2253 save_param(&ym2612, sizeof(ym2612));
2254
2255 /* save DT table index for each channel slots */
2256 for (c=0; c<6; c++)
2257 {
2258 for (s=0; s<4; s++)
2259 {
2260 index = (ym2612.CH[c].SLOT[s].DT - ym2612.OPN.ST.dt_tab[0]) >> 5;
2261 save_param(&index,sizeof(index));
2262 bufferptr += sizeof(index);
2263 }
2264 }
2265
2266 return bufferptr;
2267 }
2268