1 /* gameplaySP
2 *
3 * Copyright (C) 2006 Exophase <exophase@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
18 */
19
20 #include "common.h"
21
22 /* Sound */
23 #define gbc_sound_tone_control_low(channel, address) \
24 { \
25 u32 initial_volume = (value >> 12) & 0x0F; \
26 u32 envelope_ticks = ((value >> 8) & 0x07) * 4; \
27 gbc_sound_channel[channel].length_ticks = 64 - (value & 0x3F); \
28 gbc_sound_channel[channel].sample_data = \
29 square_pattern_duty[(value >> 6) & 0x03]; \
30 gbc_sound_channel[channel].envelope_direction = (value >> 11) & 0x01; \
31 gbc_sound_channel[channel].envelope_initial_volume = initial_volume; \
32 gbc_sound_channel[channel].envelope_volume = initial_volume; \
33 gbc_sound_channel[channel].envelope_initial_ticks = envelope_ticks; \
34 gbc_sound_channel[channel].envelope_ticks = envelope_ticks; \
35 gbc_sound_channel[channel].envelope_status = (envelope_ticks != 0); \
36 gbc_sound_channel[channel].envelope_volume = initial_volume; \
37 gbc_sound_update = 1; \
38 address16(io_registers, address) = value; \
39 } \
40
41 #define gbc_sound_tone_control_high(channel, address) \
42 { \
43 u32 rate = value & 0x7FF; \
44 gbc_sound_channel[channel].rate = rate; \
45 gbc_sound_channel[channel].frequency_step = \
46 float_to_fp16_16(((131072.0 / (2048 - rate)) * 8.0) / sound_frequency); \
47 gbc_sound_channel[channel].length_status = (value >> 14) & 0x01; \
48 if(value & 0x8000) \
49 { \
50 gbc_sound_channel[channel].active_flag = 1; \
51 gbc_sound_channel[channel].sample_index -= float_to_fp16_16(1.0 / 12.0); \
52 gbc_sound_channel[channel].envelope_ticks = \
53 gbc_sound_channel[channel].envelope_initial_ticks; \
54 gbc_sound_channel[channel].envelope_volume = \
55 gbc_sound_channel[channel].envelope_initial_volume; \
56 } \
57 \
58 gbc_sound_update = 1; \
59 address16(io_registers, address) = value; \
60 } \
61
62 #define gbc_sound_tone_control_sweep() \
63 { \
64 u32 sweep_ticks = ((value >> 4) & 0x07) * 2; \
65 gbc_sound_channel[0].sweep_shift = value & 0x07; \
66 gbc_sound_channel[0].sweep_direction = (value >> 3) & 0x01; \
67 gbc_sound_channel[0].sweep_status = (value != 8); \
68 gbc_sound_channel[0].sweep_ticks = sweep_ticks; \
69 gbc_sound_channel[0].sweep_initial_ticks = sweep_ticks; \
70 gbc_sound_update = 1; \
71 address16(io_registers, 0x60) = value; \
72 } \
73
74 #define gbc_sound_wave_control() \
75 { \
76 gbc_sound_channel[2].wave_type = (value >> 5) & 0x01; \
77 gbc_sound_channel[2].wave_bank = (value >> 6) & 0x01; \
78 gbc_sound_channel[2].master_enable = 0; \
79 if(value & 0x80) \
80 gbc_sound_channel[2].master_enable = 1; \
81 \
82 gbc_sound_update = 1; \
83 address16(io_registers, 0x70) = value; \
84 } \
85
86 static u32 gbc_sound_wave_volume[4] = { 0, 16384, 8192, 4096 };
87
88 #define gbc_sound_tone_control_low_wave() \
89 { \
90 gbc_sound_channel[2].length_ticks = 256 - (value & 0xFF); \
91 if((value >> 15) & 0x01) \
92 gbc_sound_channel[2].wave_volume = 12288; \
93 else \
94 gbc_sound_channel[2].wave_volume = \
95 gbc_sound_wave_volume[(value >> 13) & 0x03]; \
96 gbc_sound_update = 1; \
97 address16(io_registers, 0x72) = value; \
98 } \
99
100 #define gbc_sound_tone_control_high_wave() \
101 { \
102 u32 rate = value & 0x7FF; \
103 gbc_sound_channel[2].rate = rate; \
104 gbc_sound_channel[2].frequency_step = \
105 float_to_fp16_16((2097152.0 / (2048 - rate)) / sound_frequency); \
106 gbc_sound_channel[2].length_status = (value >> 14) & 0x01; \
107 if(value & 0x8000) \
108 { \
109 gbc_sound_channel[2].sample_index = 0; \
110 gbc_sound_channel[2].active_flag = 1; \
111 } \
112 gbc_sound_update = 1; \
113 address16(io_registers, 0x74) = value; \
114 } \
115
116 #define gbc_sound_noise_control() \
117 { \
118 u32 dividing_ratio = value & 0x07; \
119 u32 frequency_shift = (value >> 4) & 0x0F; \
120 if(dividing_ratio == 0) \
121 { \
122 gbc_sound_channel[3].frequency_step = \
123 float_to_fp16_16(1048576.0 / (1 << (frequency_shift + 1)) / \
124 sound_frequency); \
125 } \
126 else \
127 { \
128 gbc_sound_channel[3].frequency_step = \
129 float_to_fp16_16(524288.0 / (dividing_ratio * \
130 (1 << (frequency_shift + 1))) / sound_frequency); \
131 } \
132 gbc_sound_channel[3].noise_type = (value >> 3) & 0x01; \
133 gbc_sound_channel[3].length_status = (value >> 14) & 0x01; \
134 if(value & 0x8000) \
135 { \
136 gbc_sound_channel[3].sample_index = 0; \
137 gbc_sound_channel[3].active_flag = 1; \
138 gbc_sound_channel[3].envelope_ticks = \
139 gbc_sound_channel[3].envelope_initial_ticks; \
140 gbc_sound_channel[3].envelope_volume = \
141 gbc_sound_channel[3].envelope_initial_volume; \
142 } \
143 gbc_sound_update = 1; \
144 address16(io_registers, 0x7C) = value; \
145 } \
146
gbc_trigger_sound(u32 value)147 static void gbc_trigger_sound(u32 value)
148 {
149 u32 channel;
150
151 /* Trigger all 4 GBC sound channels */
152 for (channel = 0; channel < 4; channel++)
153 {
154 gbc_sound_master_volume_right = value & 0x07;
155 gbc_sound_master_volume_left = (value >> 4) & 0x07;
156 gbc_sound_channel[channel].status =
157 ((value >> (channel + 8)) & 0x01) | ((value >> (channel + 11)) & 0x03);
158 }
159 address16(io_registers, 0x80) = value;
160 }
161
162 #define trigger_sound() \
163 { \
164 timer[0].direct_sound_channels = (((value >> 10) & 0x01) == 0) | \
165 ((((value >> 14) & 0x01) == 0) << 1); \
166 timer[1].direct_sound_channels = (((value >> 10) & 0x01) == 1) | \
167 ((((value >> 14) & 0x01) == 1) << 1); \
168 direct_sound_channel[0].volume = (value >> 2) & 0x01; \
169 direct_sound_channel[0].status = (value >> 8) & 0x03; \
170 direct_sound_channel[1].volume = (value >> 3) & 0x01; \
171 direct_sound_channel[1].status = (value >> 12) & 0x03; \
172 gbc_sound_master_volume = value & 0x03; \
173 \
174 if((value >> 11) & 0x01) \
175 sound_reset_fifo(0); \
176 if((value >> 15) & 0x01) \
177 sound_reset_fifo(1); \
178 address16(io_registers, 0x82) = value; \
179 } \
180
sound_control_x(u32 value)181 static void sound_control_x(u32 value)
182 {
183 if (value & 0x80)
184 {
185 if (sound_on != 1)
186 sound_on = 1;
187 }
188 else
189 {
190 u32 i;
191 for (i = 0; i < 4; i++)
192 gbc_sound_channel[i].active_flag = 0;
193 sound_on = 0;
194 }
195
196 address16(io_registers, 0x84) =
197 (address16(io_registers, 0x84) & 0x000F) | (value & 0xFFF0);
198 }
199
200 #define sound_update_frequency_step(timer_number) \
201 timer[timer_number].frequency_step = \
202 float_to_fp8_24(GBC_BASE_RATE / (timer_reload * sound_frequency)) \
203
204 /* Main */
205 extern timer_type timer[4];
206 static u32 prescale_table[] = { 0, 6, 8, 10 };
207
208 #define count_timer(timer_number) \
209 timer[timer_number].reload = 0x10000 - value; \
210 if(timer_number < 2) \
211 { \
212 u32 timer_reload = \
213 timer[timer_number].reload << timer[timer_number].prescale; \
214 sound_update_frequency_step(timer_number); \
215 } \
216
217 #define adjust_sound_buffer(timer_number, channel) \
218 if(timer[timer_number].direct_sound_channels & (0x01 << channel)) \
219 { \
220 direct_sound_channel[channel].buffer_index = \
221 (gbc_sound_buffer_index + buffer_adjust) % BUFFER_SIZE; \
222 } \
223
trigger_timer(u32 timer_number,u32 value)224 static void trigger_timer(u32 timer_number, u32 value)
225 {
226 if (value & 0x80)
227 {
228 if(timer[timer_number].status == TIMER_INACTIVE)
229 {
230 u32 prescale = prescale_table[value & 0x03];
231 u32 timer_reload = timer[timer_number].reload;
232
233 if((value >> 2) & 0x01)
234 timer[timer_number].status = TIMER_CASCADE;
235 else
236 timer[timer_number].status = TIMER_PRESCALE;
237
238 timer[timer_number].prescale = prescale;
239 timer[timer_number].irq = (value >> 6) & 0x01;
240
241 address16(io_registers, 0x100 + (timer_number * 4)) = -timer_reload;
242
243 timer_reload <<= prescale;
244 timer[timer_number].count = timer_reload;
245
246 if(timer_reload < execute_cycles)
247 execute_cycles = timer_reload;
248
249 if(timer_number < 2)
250 {
251 u32 buffer_adjust =
252 (u32)(((float)(cpu_ticks - gbc_sound_last_cpu_ticks) *
253 sound_frequency) / GBC_BASE_RATE) * 2;
254
255 sound_update_frequency_step(timer_number);
256 adjust_sound_buffer(timer_number, 0);
257 adjust_sound_buffer(timer_number, 1);
258 }
259 }
260 }
261 else
262 {
263 if(timer[timer_number].status != TIMER_INACTIVE)
264 {
265 timer[timer_number].status = TIMER_INACTIVE;
266 timer[timer_number].stop_cpu_ticks = cpu_ticks;
267 }
268 }
269 address16(io_registers, 0x102 + (timer_number * 4)) = value;
270 }
271
272 // This table is configured for sequential access on system defaults
273
274 u32 waitstate_cycles_sequential[16][3] =
275 {
276 { 1, 1, 1 }, // BIOS
277 { 1, 1, 1 }, // Invalid
278 { 3, 3, 6 }, // EWRAM (default settings)
279 { 1, 1, 1 }, // IWRAM
280 { 1, 1, 1 }, // IO Registers
281 { 1, 1, 2 }, // Palette RAM
282 { 1, 1, 2 }, // VRAM
283 { 1, 1, 2 }, // OAM
284 { 3, 3, 6 }, // Gamepak (wait 0)
285 { 3, 3, 6 }, // Gamepak (wait 0)
286 { 5, 5, 9 }, // Gamepak (wait 1)
287 { 5, 5, 9 }, // Gamepak (wait 1)
288 { 9, 9, 17 }, // Gamepak (wait 2)
289 { 9, 9, 17 }, // Gamepak (wait 2)
290 };
291
292 // Different settings for gamepak ws0-2 sequential (2nd) access
293
294 u32 gamepak_waitstate_sequential[2][3][3] =
295 {
296 {
297 { 3, 3, 6 },
298 { 5, 5, 9 },
299 { 9, 9, 17 }
300 },
301 {
302 { 2, 2, 3 },
303 { 2, 2, 3 },
304 { 2, 2, 3 }
305 }
306 };
307
308 u16 palette_ram[512];
309 u16 oam_ram[512];
310 u16 palette_ram_converted[512];
311 u16 io_registers[1024 * 16];
312 u8 ewram[1024 * 256 * 2];
313 u8 iwram[1024 * 32 * 2];
314 u8 vram[1024 * 96];
315
316 u8 bios_rom[1024 * 16 * 2];
317 u32 bios_read_protect;
318
319 // Up to 128kb, store SRAM, flash ROM, or EEPROM here.
320 u8 gamepak_backup[1024 * 128];
321
322 // Keeps us knowing how much we have left.
323 u8 *gamepak_rom;
324 u32 gamepak_size;
325
326 dma_transfer_type dma[4];
327
328 u8 *memory_regions[16];
329 u32 memory_limits[16];
330
331 typedef struct
332 {
333 u32 page_timestamp;
334 u32 physical_index;
335 } gamepak_swap_entry_type;
336
337 u32 gamepak_ram_buffer_size;
338 u32 gamepak_ram_pages;
339
340 // Enough to map the gamepak RAM space.
341 gamepak_swap_entry_type *gamepak_memory_map;
342
343 // This is global so that it can be kept open for large ROMs to swap
344 // pages from, so there's no slowdown with opening and closing the file
345 // a lot.
346 #ifdef PSP
347
348 file_tag_type gamepak_file_large = -1;
349
350 #else
351
352 file_tag_type gamepak_file_large = NULL;
353
354 #endif
355
356 u32 direct_map_vram = 0;
357
358 // Writes to these respective locations should trigger an update
359 // so the related subsystem may react to it.
360
361 // If OAM is written to:
362 u32 oam_update = 1;
363
364 // If GBC audio is written to:
365 u32 gbc_sound_update = 0;
366
367 // If the GBC audio waveform is modified:
368 u32 gbc_sound_wave_update = 0;
369
370 // Keep it 32KB until the upper 64KB is accessed, then make it 64KB.
371
372 backup_type_type backup_type = BACKUP_NONE;
373 sram_size_type sram_size = SRAM_SIZE_32KB;
374
375 flash_mode_type flash_mode = FLASH_BASE_MODE;
376 u32 flash_command_position = 0;
377 u8 *flash_bank_ptr = gamepak_backup;
378
379 flash_device_id_type flash_device_id = FLASH_DEVICE_MACRONIX_64KB;
380 flash_manufacturer_id_type flash_manufacturer_id =
381 FLASH_MANUFACTURER_MACRONIX;
382 flash_size_type flash_size = FLASH_SIZE_64KB;
383
read_backup(u32 address)384 u8 read_backup(u32 address)
385 {
386 u8 value = 0;
387
388 if(backup_type == BACKUP_NONE)
389 backup_type = BACKUP_SRAM;
390
391 if(backup_type == BACKUP_SRAM)
392 value = gamepak_backup[address];
393 else if(flash_mode == FLASH_ID_MODE)
394 {
395 if (flash_size == FLASH_SIZE_128KB)
396 {
397 /* ID manufacturer type */
398 if(address == 0x0000)
399 value = FLASH_MANUFACTURER_MACRONIX;
400 /* ID device type */
401 else if(address == 0x0001)
402 value = FLASH_DEVICE_MACRONIX_128KB;
403 }
404 else
405 {
406 /* ID manufacturer type */
407 if(address == 0x0000)
408 value = FLASH_MANUFACTURER_PANASONIC;
409 /* ID device type */
410 else if(address == 0x0001)
411 value = FLASH_DEVICE_PANASONIC_64KB;
412 }
413 }
414 else
415 value = flash_bank_ptr[address];
416
417 return value;
418 }
419
420 #define read_backup8() \
421 value = read_backup(address & 0xFFFF) \
422
423 #define read_backup16() \
424 value = 0 \
425
426 #define read_backup32() \
427 value = 0 \
428
429
430 // EEPROM is 512 bytes by default; it is autodetecte as 8KB if
431 // 14bit address DMAs are made (this is done in the DMA handler).
432
433 eeprom_size_type eeprom_size = EEPROM_512_BYTE;
434 eeprom_mode_type eeprom_mode = EEPROM_BASE_MODE;
435 u32 eeprom_address_length;
436 u32 eeprom_address = 0;
437 s32 eeprom_counter = 0;
438 u8 eeprom_buffer[8];
439
write_eeprom(u32 address,u32 value)440 void write_eeprom(u32 address, u32 value)
441 {
442 switch(eeprom_mode)
443 {
444 case EEPROM_BASE_MODE:
445 backup_type = BACKUP_EEPROM;
446 eeprom_buffer[0] |= (value & 0x01) << (1 - eeprom_counter);
447 eeprom_counter++;
448 if(eeprom_counter == 2)
449 {
450 if(eeprom_size == EEPROM_512_BYTE)
451 eeprom_address_length = 6;
452 else
453 eeprom_address_length = 14;
454
455 eeprom_counter = 0;
456
457 switch(eeprom_buffer[0] & 0x03)
458 {
459 case 0x02:
460 eeprom_mode = EEPROM_WRITE_ADDRESS_MODE;
461 break;
462
463 case 0x03:
464 eeprom_mode = EEPROM_ADDRESS_MODE;
465 break;
466 }
467 address16(eeprom_buffer, 0) = 0;
468 }
469 break;
470
471 case EEPROM_ADDRESS_MODE:
472 case EEPROM_WRITE_ADDRESS_MODE:
473 eeprom_buffer[eeprom_counter / 8]
474 |= (value & 0x01) << (7 - (eeprom_counter % 8));
475 eeprom_counter++;
476 if(eeprom_counter == eeprom_address_length)
477 {
478 if(eeprom_size == EEPROM_512_BYTE)
479 {
480 eeprom_address =
481 (address16(eeprom_buffer, 0) >> 2) * 8;
482 }
483 else
484 {
485 eeprom_address = (((u32)eeprom_buffer[1] >> 2) |
486 ((u32)eeprom_buffer[0] << 6)) * 8;
487 }
488
489 address16(eeprom_buffer, 0) = 0;
490 eeprom_counter = 0;
491
492 if(eeprom_mode == EEPROM_ADDRESS_MODE)
493 eeprom_mode = EEPROM_ADDRESS_FOOTER_MODE;
494 else
495 {
496 eeprom_mode = EEPROM_WRITE_MODE;
497 memset(gamepak_backup + eeprom_address, 0, 8);
498 }
499 }
500 break;
501
502 case EEPROM_WRITE_MODE:
503 gamepak_backup[eeprom_address + (eeprom_counter / 8)] |=
504 (value & 0x01) << (7 - (eeprom_counter % 8));
505 eeprom_counter++;
506 if(eeprom_counter == 64)
507 {
508 eeprom_counter = 0;
509 eeprom_mode = EEPROM_WRITE_FOOTER_MODE;
510 }
511 break;
512
513 case EEPROM_ADDRESS_FOOTER_MODE:
514 case EEPROM_WRITE_FOOTER_MODE:
515 eeprom_counter = 0;
516 if(eeprom_mode == EEPROM_ADDRESS_FOOTER_MODE)
517 eeprom_mode = EEPROM_READ_HEADER_MODE;
518 else
519 eeprom_mode = EEPROM_BASE_MODE;
520 break;
521
522 default:
523 break;
524 }
525 }
526
527 #define read_memory_gamepak(type) \
528 u32 gamepak_index = address >> 15; \
529 u8 *map = memory_map_read[gamepak_index]; \
530 \
531 if(!map) \
532 map = load_gamepak_page(gamepak_index & 0x3FF); \
533 \
534 value = address##type(map, address & 0x7FFF) \
535
536 #define read_open8() \
537 if(!(reg[REG_CPSR] & 0x20)) \
538 value = read_memory8(reg[REG_PC] + 4 + (address & 0x03)); \
539 else \
540 value = read_memory8(reg[REG_PC] + 2 + (address & 0x01)) \
541
542 #define read_open16() \
543 if(!(reg[REG_CPSR] & 0x20)) \
544 value = read_memory16(reg[REG_PC] + 4 + (address & 0x02)); \
545 else \
546 value = read_memory16(reg[REG_PC] + 2) \
547
548 #define read_open32() \
549 if(!(reg[REG_CPSR] & 0x20)) \
550 value = read_memory32(reg[REG_PC] + 4); \
551 else \
552 { \
553 u32 current_instruction = read_memory16(reg[REG_PC] + 2); \
554 value = current_instruction | (current_instruction << 16); \
555 } \
556
read_eeprom(void)557 u32 read_eeprom(void)
558 {
559 u32 value;
560
561 switch(eeprom_mode)
562 {
563 case EEPROM_BASE_MODE:
564 value = 1;
565 break;
566
567 case EEPROM_READ_MODE:
568 value = (gamepak_backup[eeprom_address + (eeprom_counter / 8)] >>
569 (7 - (eeprom_counter % 8))) & 0x01;
570 eeprom_counter++;
571 if(eeprom_counter == 64)
572 {
573 eeprom_counter = 0;
574 eeprom_mode = EEPROM_BASE_MODE;
575 }
576 break;
577
578 case EEPROM_READ_HEADER_MODE:
579 value = 0;
580 eeprom_counter++;
581 if(eeprom_counter == 4)
582 {
583 eeprom_mode = EEPROM_READ_MODE;
584 eeprom_counter = 0;
585 }
586 break;
587
588 default:
589 value = 0;
590 break;
591 }
592
593 return value;
594 }
595
596
597 #define read_memory(type) \
598 switch(address >> 24) \
599 { \
600 case 0x00: \
601 /* BIOS */ \
602 if(reg[REG_PC] >= 0x4000) \
603 value = address##type(&bios_read_protect, address & 0x03); \
604 else \
605 value = address##type(bios_rom, address & 0x3FFF); \
606 break; \
607 \
608 case 0x02: \
609 /* external work RAM */ \
610 address = (address & 0x7FFF) + ((address & 0x38000) * 2) + 0x8000; \
611 value = address##type(ewram, address); \
612 break; \
613 \
614 case 0x03: \
615 /* internal work RAM */ \
616 value = address##type(iwram, (address & 0x7FFF) + 0x8000); \
617 break; \
618 \
619 case 0x04: \
620 /* I/O registers */ \
621 value = address##type(io_registers, address & 0x3FF); \
622 break; \
623 \
624 case 0x05: \
625 /* palette RAM */ \
626 value = address##type(palette_ram, address & 0x3FF); \
627 break; \
628 \
629 case 0x06: \
630 /* VRAM */ \
631 address &= 0x1FFFF; \
632 if(address > 0x18000) \
633 address -= 0x8000; \
634 \
635 value = address##type(vram, address); \
636 break; \
637 \
638 case 0x07: \
639 /* OAM RAM */ \
640 value = address##type(oam_ram, address & 0x3FF); \
641 break; \
642 \
643 case 0x08: \
644 case 0x09: \
645 case 0x0A: \
646 case 0x0B: \
647 case 0x0C: \
648 /* gamepak ROM */ \
649 if((address & 0x1FFFFFF) >= gamepak_size) \
650 value = 0; \
651 else \
652 { \
653 read_memory_gamepak(type); \
654 } \
655 break; \
656 \
657 case 0x0D: \
658 if((address & 0x1FFFFFF) < gamepak_size) \
659 { \
660 read_memory_gamepak(type); \
661 } \
662 else \
663 value = read_eeprom(); \
664 \
665 break; \
666 \
667 case 0x0E: \
668 case 0x0F: \
669 read_backup##type(); \
670 break; \
671 \
672 default: \
673 read_open##type(); \
674 break; \
675 } \
676
trigger_dma(u32 dma_number,u32 value)677 static cpu_alert_type trigger_dma(u32 dma_number, u32 value)
678 {
679 if(value & 0x8000)
680 {
681 if(dma[dma_number].start_type == DMA_INACTIVE)
682 {
683 u32 start_type = (value >> 12) & 0x03;
684 u32 dest_address = address32(io_registers, (dma_number * 12) + 0xB4) &
685 0xFFFFFFF;
686
687 dma[dma_number].dma_channel = dma_number;
688 dma[dma_number].source_address =
689 address32(io_registers, (dma_number * 12) + 0xB0) & 0xFFFFFFF;
690 dma[dma_number].dest_address = dest_address;
691 dma[dma_number].source_direction = (value >> 7) & 0x03;
692 dma[dma_number].repeat_type = (value >> 9) & 0x01;
693 dma[dma_number].start_type = start_type;
694 dma[dma_number].irq = (value >> 14) & 0x01;
695
696 /* If it is sound FIFO DMA make sure the settings are a certain way */
697 if((dma_number >= 1) && (dma_number <= 2) &&
698 (start_type == DMA_START_SPECIAL))
699 {
700 dma[dma_number].length_type = DMA_32BIT;
701 dma[dma_number].length = 4;
702 dma[dma_number].dest_direction = DMA_FIXED;
703 if(dest_address == 0x40000A4)
704 dma[dma_number].direct_sound_channel = DMA_DIRECT_SOUND_B;
705 else
706 dma[dma_number].direct_sound_channel = DMA_DIRECT_SOUND_A;
707 }
708 else
709 {
710 u32 length = address16(io_registers, (dma_number * 12) + 0xB8);
711
712 if((dma_number == 3) && ((dest_address >> 24) == 0x0D) &&
713 ((length & 0x1F) == 17))
714 eeprom_size = EEPROM_8_KBYTE;
715
716 if(dma_number < 3)
717 length &= 0x3FFF;
718
719 if(length == 0)
720 {
721 if(dma_number == 3)
722 length = 0x10000;
723 else
724 length = 0x04000;
725 }
726
727 dma[dma_number].length = length;
728 dma[dma_number].length_type = (value >> 10) & 0x01;
729 dma[dma_number].dest_direction = (value >> 5) & 0x03;
730 }
731
732 address16(io_registers, (dma_number * 12) + 0xBA) = value;
733 if(start_type == DMA_START_IMMEDIATELY)
734 return dma_transfer(dma + dma_number);
735 }
736 }
737 else
738 {
739 dma[dma_number].start_type = DMA_INACTIVE;
740 dma[dma_number].direct_sound_channel = DMA_NO_DIRECT_SOUND;
741 address16(io_registers, (dma_number * 12) + 0xBA) = value;
742 }
743
744 return CPU_ALERT_NONE;
745 }
746
747
748 #define access_register8_high(address) \
749 value = (value << 8) | (address8(io_registers, address)) \
750
751 #define access_register8_low(address) \
752 value = ((address8(io_registers, address + 1)) << 8) | value \
753
754 #define access_register16_high(address) \
755 value = (value << 16) | (address16(io_registers, address)) \
756
757 #define access_register16_low(address) \
758 value = ((address16(io_registers, address + 2)) << 16) | value \
759
write_io_register8(u32 address,u32 value)760 cpu_alert_type write_io_register8(u32 address, u32 value)
761 {
762 switch(address)
763 {
764 case 0x00:
765 {
766 u32 dispcnt = io_registers[REG_DISPCNT];
767
768 if((value & 0x07) != (dispcnt & 0x07))
769 oam_update = 1;
770
771 address8(io_registers, 0x00) = value;
772 break;
773 }
774
775 // DISPSTAT (lower byte)
776 case 0x04:
777 address8(io_registers, 0x04) =
778 (address8(io_registers, 0x04) & 0x07) | (value & ~0x07);
779 break;
780
781 // VCOUNT
782 case 0x06:
783 case 0x07:
784 break;
785
786 // BG2 reference X
787 case 0x28:
788 access_register8_low(0x28);
789 access_register16_low(0x28);
790 affine_reference_x[0] = (s32)(value << 4) >> 4;
791 address32(io_registers, 0x28) = value;
792 break;
793
794 case 0x29:
795 access_register8_high(0x28);
796 access_register16_low(0x28);
797 affine_reference_x[0] = (s32)(value << 4) >> 4;
798 address32(io_registers, 0x28) = value;
799 break;
800
801 case 0x2A:
802 access_register8_low(0x2A);
803 access_register16_high(0x28);
804 affine_reference_x[0] = (s32)(value << 4) >> 4;
805 address32(io_registers, 0x28) = value;
806 break;
807
808 case 0x2B:
809 access_register8_high(0x2A);
810 access_register16_high(0x28);
811 affine_reference_x[0] = (s32)(value << 4) >> 4;
812 address32(io_registers, 0x28) = value;
813 break;
814
815 // BG2 reference Y
816 case 0x2C:
817 access_register8_low(0x2C);
818 access_register16_low(0x2C);
819 affine_reference_y[0] = (s32)(value << 4) >> 4;
820 address32(io_registers, 0x2C) = value;
821 break;
822
823 case 0x2D:
824 access_register8_high(0x2C);
825 access_register16_low(0x2C);
826 affine_reference_y[0] = (s32)(value << 4) >> 4;
827 address32(io_registers, 0x2C) = value;
828 break;
829
830 case 0x2E:
831 access_register8_low(0x2E);
832 access_register16_high(0x2C);
833 affine_reference_y[0] = (s32)(value << 4) >> 4;
834 address32(io_registers, 0x2C) = value;
835 break;
836
837 case 0x2F:
838 access_register8_high(0x2E);
839 access_register16_high(0x2C);
840 affine_reference_y[0] = (s32)(value << 4) >> 4;
841 address32(io_registers, 0x2C) = value;
842 break;
843
844 // BG3 reference X
845 case 0x38:
846 access_register8_low(0x38);
847 access_register16_low(0x38);
848 affine_reference_x[1] = (s32)(value << 4) >> 4;
849 address32(io_registers, 0x38) = value;
850 break;
851
852 case 0x39:
853 access_register8_high(0x38);
854 access_register16_low(0x38);
855 affine_reference_x[1] = (s32)(value << 4) >> 4;
856 address32(io_registers, 0x38) = value;
857 break;
858
859 case 0x3A:
860 access_register8_low(0x3A);
861 access_register16_high(0x38);
862 affine_reference_x[1] = (s32)(value << 4) >> 4;
863 address32(io_registers, 0x38) = value;
864 break;
865
866 case 0x3B:
867 access_register8_high(0x3A);
868 access_register16_high(0x38);
869 affine_reference_x[1] = (s32)(value << 4) >> 4;
870 address32(io_registers, 0x38) = value;
871 break;
872
873 // BG3 reference Y
874 case 0x3C:
875 access_register8_low(0x3C);
876 access_register16_low(0x3C);
877 affine_reference_y[1] = (s32)(value << 4) >> 4;
878 address32(io_registers, 0x3C) = value;
879 break;
880
881 case 0x3D:
882 access_register8_high(0x3C);
883 access_register16_low(0x3C);
884 affine_reference_y[1] = (s32)(value << 4) >> 4;
885 address32(io_registers, 0x3C) = value;
886 break;
887
888 case 0x3E:
889 access_register8_low(0x3E);
890 access_register16_high(0x3C);
891 affine_reference_y[1] = (s32)(value << 4) >> 4;
892 address32(io_registers, 0x3C) = value;
893 break;
894
895 case 0x3F:
896 access_register8_high(0x3E);
897 access_register16_high(0x3C);
898 affine_reference_y[1] = (s32)(value << 4) >> 4;
899 address32(io_registers, 0x3C) = value;
900 break;
901
902 // Sound 1 control sweep
903 case 0x60:
904 access_register8_low(0x60);
905 gbc_sound_tone_control_sweep();
906 break;
907
908 case 0x61:
909 access_register8_low(0x60);
910 gbc_sound_tone_control_sweep();
911 break;
912
913 // Sound 1 control duty/length/envelope
914 case 0x62:
915 access_register8_low(0x62);
916 gbc_sound_tone_control_low(0, 0x62);
917 break;
918
919 case 0x63:
920 access_register8_high(0x62);
921 gbc_sound_tone_control_low(0, 0x62);
922 break;
923
924 // Sound 1 control frequency
925 case 0x64:
926 access_register8_low(0x64);
927 gbc_sound_tone_control_high(0, 0x64);
928 break;
929
930 case 0x65:
931 access_register8_high(0x64);
932 gbc_sound_tone_control_high(0, 0x64);
933 break;
934
935 // Sound 2 control duty/length/envelope
936 case 0x68:
937 access_register8_low(0x68);
938 gbc_sound_tone_control_low(1, 0x68);
939 break;
940
941 case 0x69:
942 access_register8_high(0x68);
943 gbc_sound_tone_control_low(1, 0x68);
944 break;
945
946 // Sound 2 control frequency
947 case 0x6C:
948 access_register8_low(0x6C);
949 gbc_sound_tone_control_high(1, 0x6C);
950 break;
951
952 case 0x6D:
953 access_register8_high(0x6C);
954 gbc_sound_tone_control_high(1, 0x6C);
955 break;
956
957 // Sound 3 control wave
958 case 0x70:
959 access_register8_low(0x70);
960 gbc_sound_wave_control();
961 break;
962
963 case 0x71:
964 access_register8_high(0x70);
965 gbc_sound_wave_control();
966 break;
967
968 // Sound 3 control length/volume
969 case 0x72:
970 access_register8_low(0x72);
971 gbc_sound_tone_control_low_wave();
972 break;
973
974 case 0x73:
975 access_register8_high(0x72);
976 gbc_sound_tone_control_low_wave();
977 break;
978
979 // Sound 3 control frequency
980 case 0x74:
981 access_register8_low(0x74);
982 gbc_sound_tone_control_high_wave();
983 break;
984
985 case 0x75:
986 access_register8_high(0x74);
987 gbc_sound_tone_control_high_wave();
988 break;
989
990 // Sound 4 control length/envelope
991 case 0x78:
992 access_register8_low(0x78);
993 gbc_sound_tone_control_low(3, 0x78);
994 break;
995
996 case 0x79:
997 access_register8_high(0x78);
998 gbc_sound_tone_control_low(3, 0x78);
999 break;
1000
1001 // Sound 4 control frequency
1002 case 0x7C:
1003 access_register8_low(0x7C);
1004 gbc_sound_noise_control();
1005 break;
1006
1007 case 0x7D:
1008 access_register8_high(0x7C);
1009 gbc_sound_noise_control();
1010 break;
1011
1012 // Sound control L
1013 case 0x80:
1014 access_register8_low(0x80);
1015 gbc_trigger_sound(value);
1016 break;
1017
1018 case 0x81:
1019 access_register8_high(0x80);
1020 gbc_trigger_sound(value);
1021 break;
1022
1023 // Sound control H
1024 case 0x82:
1025 access_register8_low(0x82);
1026 trigger_sound();
1027 break;
1028
1029 case 0x83:
1030 access_register8_high(0x82);
1031 trigger_sound();
1032 break;
1033
1034 // Sound control X
1035 case 0x84:
1036 sound_control_x(value);
1037 break;
1038
1039 // Sound wave RAM
1040 case 0x90:
1041 case 0x91:
1042 case 0x92:
1043 case 0x93:
1044 case 0x94:
1045 case 0x95:
1046 case 0x96:
1047 case 0x97:
1048 case 0x98:
1049 case 0x99:
1050 case 0x9A:
1051 case 0x9B:
1052 case 0x9C:
1053 case 0x9D:
1054 case 0x9E:
1055 case 0x9F:
1056 gbc_sound_wave_update = 1;
1057 address8(io_registers, address) = value;
1058 break;
1059
1060 // Sound FIFO A
1061 case 0xA0:
1062 sound_timer_queue8(0, value);
1063 break;
1064
1065 // Sound FIFO B
1066 case 0xA4:
1067 sound_timer_queue8(1, value);
1068 break;
1069
1070 // DMA control (trigger byte)
1071 case 0xBB:
1072 access_register8_low(0xBA);
1073 return trigger_dma(0, value);
1074
1075 case 0xC7:
1076 access_register8_low(0xC6);
1077 return trigger_dma(1, value);
1078
1079 case 0xD3:
1080 access_register8_low(0xD2);
1081 return trigger_dma(2, value);
1082
1083 case 0xDF:
1084 access_register8_low(0xDE);
1085 return trigger_dma(3, value);
1086
1087 // Timer counts
1088 case 0x100:
1089 access_register8_low(0x100);
1090 count_timer(0);
1091 break;
1092
1093 case 0x101:
1094 access_register8_high(0x100);
1095 count_timer(0);
1096 break;
1097
1098 case 0x104:
1099 access_register8_low(0x104);
1100 count_timer(1);
1101 break;
1102
1103 case 0x105:
1104 access_register8_high(0x104);
1105 count_timer(1);
1106 break;
1107
1108 case 0x108:
1109 access_register8_low(0x108);
1110 count_timer(2);
1111 break;
1112
1113 case 0x109:
1114 access_register8_high(0x108);
1115 count_timer(2);
1116 break;
1117
1118 case 0x10C:
1119 access_register8_low(0x10C);
1120 count_timer(3);
1121 break;
1122
1123 case 0x10D:
1124 access_register8_high(0x10C);
1125 count_timer(3);
1126 break;
1127
1128 // Timer control (trigger byte)
1129 case 0x103:
1130 access_register8_low(0x102);
1131 trigger_timer(0, value);
1132 break;
1133
1134 case 0x107:
1135 access_register8_low(0x106);
1136 trigger_timer(1, value);
1137 break;
1138
1139 case 0x10B:
1140 access_register8_low(0x10A);
1141 trigger_timer(2, value);
1142 break;
1143
1144 case 0x10F:
1145 access_register8_low(0x10E);
1146 trigger_timer(3, value);
1147 break;
1148
1149 // IF
1150 case 0x202:
1151 address8(io_registers, 0x202) &= ~value;
1152 break;
1153
1154 case 0x203:
1155 address8(io_registers, 0x203) &= ~value;
1156 break;
1157
1158 // Halt
1159 case 0x301:
1160 if((value & 0x01) == 0)
1161 reg[CPU_HALT_STATE] = CPU_HALT;
1162 else
1163 reg[CPU_HALT_STATE] = CPU_STOP;
1164
1165 return CPU_ALERT_HALT;
1166 break;
1167
1168 default:
1169 address8(io_registers, address) = value;
1170 break;
1171 }
1172
1173 return CPU_ALERT_NONE;
1174 }
1175
write_io_register16(u32 address,u32 value)1176 cpu_alert_type write_io_register16(u32 address, u32 value)
1177 {
1178 switch(address)
1179 {
1180 case 0x00:
1181 {
1182 u32 dispcnt = io_registers[REG_DISPCNT];
1183 if((value & 0x07) != (dispcnt & 0x07))
1184 oam_update = 1;
1185
1186 address16(io_registers, 0x00) = value;
1187 break;
1188 }
1189
1190 // DISPSTAT
1191 case 0x04:
1192 address16(io_registers, 0x04) =
1193 (address16(io_registers, 0x04) & 0x07) | (value & ~0x07);
1194 break;
1195
1196 // VCOUNT
1197 case 0x06:
1198 break;
1199
1200 // BG2 reference X
1201 case 0x28:
1202 access_register16_low(0x28);
1203 affine_reference_x[0] = (s32)(value << 4) >> 4;
1204 address32(io_registers, 0x28) = value;
1205 break;
1206
1207 case 0x2A:
1208 access_register16_high(0x28);
1209 affine_reference_x[0] = (s32)(value << 4) >> 4;
1210 address32(io_registers, 0x28) = value;
1211 break;
1212
1213 // BG2 reference Y
1214 case 0x2C:
1215 access_register16_low(0x2C);
1216 affine_reference_y[0] = (s32)(value << 4) >> 4;
1217 address32(io_registers, 0x2C) = value;
1218 break;
1219
1220 case 0x2E:
1221 access_register16_high(0x2C);
1222 affine_reference_y[0] = (s32)(value << 4) >> 4;
1223 address32(io_registers, 0x2C) = value;
1224 break;
1225
1226 // BG3 reference X
1227
1228 case 0x38:
1229 access_register16_low(0x38);
1230 affine_reference_x[1] = (s32)(value << 4) >> 4;
1231 address32(io_registers, 0x38) = value;
1232 break;
1233
1234 case 0x3A:
1235 access_register16_high(0x38);
1236 affine_reference_x[1] = (s32)(value << 4) >> 4;
1237 address32(io_registers, 0x38) = value;
1238 break;
1239
1240 // BG3 reference Y
1241 case 0x3C:
1242 access_register16_low(0x3C);
1243 affine_reference_y[1] = (s32)(value << 4) >> 4;
1244 address32(io_registers, 0x3C) = value;
1245 break;
1246
1247 case 0x3E:
1248 access_register16_high(0x3C);
1249 affine_reference_y[1] = (s32)(value << 4) >> 4;
1250 address32(io_registers, 0x3C) = value;
1251 break;
1252
1253 // Sound 1 control sweep
1254 case 0x60:
1255 gbc_sound_tone_control_sweep();
1256 break;
1257
1258 // Sound 1 control duty/length/envelope
1259 case 0x62:
1260 gbc_sound_tone_control_low(0, 0x62);
1261 break;
1262
1263 // Sound 1 control frequency
1264 case 0x64:
1265 gbc_sound_tone_control_high(0, 0x64);
1266 break;
1267
1268 // Sound 2 control duty/length/envelope
1269 case 0x68:
1270 gbc_sound_tone_control_low(1, 0x68);
1271 break;
1272
1273 // Sound 2 control frequency
1274 case 0x6C:
1275 gbc_sound_tone_control_high(1, 0x6C);
1276 break;
1277
1278 // Sound 3 control wave
1279 case 0x70:
1280 gbc_sound_wave_control();
1281 break;
1282
1283 // Sound 3 control length/volume
1284 case 0x72:
1285 gbc_sound_tone_control_low_wave();
1286 break;
1287
1288 // Sound 3 control frequency
1289 case 0x74:
1290 gbc_sound_tone_control_high_wave();
1291 break;
1292
1293 // Sound 4 control length/envelope
1294 case 0x78:
1295 gbc_sound_tone_control_low(3, 0x78);
1296 break;
1297
1298 // Sound 4 control frequency
1299 case 0x7C:
1300 gbc_sound_noise_control();
1301 break;
1302
1303 // Sound control L
1304 case 0x80:
1305 gbc_trigger_sound(value);
1306 break;
1307
1308 // Sound control H
1309 case 0x82:
1310 trigger_sound();
1311 break;
1312
1313 // Sound control X
1314 case 0x84:
1315 sound_control_x(value);
1316 break;
1317
1318 // Sound wave RAM
1319 case 0x90:
1320 case 0x91:
1321 case 0x92:
1322 case 0x93:
1323 case 0x94:
1324 case 0x95:
1325 case 0x96:
1326 case 0x97:
1327 case 0x98:
1328 case 0x99:
1329 case 0x9A:
1330 case 0x9B:
1331 case 0x9C:
1332 case 0x9D:
1333 case 0x9E:
1334 gbc_sound_wave_update = 1;
1335 address16(io_registers, address) = value;
1336 break;
1337
1338 // Sound FIFO A
1339 case 0xA0:
1340 sound_timer_queue16(0, value);
1341 break;
1342
1343 // Sound FIFO B
1344 case 0xA4:
1345 sound_timer_queue16(1, value);
1346 break;
1347
1348 // DMA control
1349 case 0xBA:
1350 return trigger_dma(0, value);
1351
1352 case 0xC6:
1353 return trigger_dma(1, value);
1354
1355 case 0xD2:
1356 return trigger_dma(2, value);
1357
1358 case 0xDE:
1359 return trigger_dma(3, value);
1360
1361 // Timer counts
1362 case 0x100:
1363 count_timer(0);
1364 break;
1365
1366 case 0x104:
1367 count_timer(1);
1368 break;
1369
1370 case 0x108:
1371 count_timer(2);
1372 break;
1373
1374 case 0x10C:
1375 count_timer(3);
1376 break;
1377
1378 /* Timer control 0 */
1379 case 0x102:
1380 trigger_timer(0, value);
1381 break;
1382
1383 /* Timer control 1 */
1384 case 0x106:
1385 trigger_timer(1, value);
1386 break;
1387
1388 /* Timer control 2 */
1389 case 0x10A:
1390 trigger_timer(2, value);
1391 break;
1392
1393 /* Timer control 3 */
1394 case 0x10E:
1395 trigger_timer(3, value);
1396 break;
1397
1398 // P1
1399 case 0x130:
1400 break;
1401
1402 // Interrupt flag
1403 case 0x202:
1404 address16(io_registers, 0x202) &= ~value;
1405 break;
1406
1407 // WAITCNT
1408 case 0x204:
1409 break;
1410
1411 // Halt
1412 case 0x300:
1413 if(((value >> 8) & 0x01) == 0)
1414 reg[CPU_HALT_STATE] = CPU_HALT;
1415 else
1416 reg[CPU_HALT_STATE] = CPU_STOP;
1417
1418 return CPU_ALERT_HALT;
1419
1420 default:
1421 address16(io_registers, address) = value;
1422 break;
1423 }
1424
1425 return CPU_ALERT_NONE;
1426 }
1427
1428
write_io_register32(u32 address,u32 value)1429 cpu_alert_type write_io_register32(u32 address, u32 value)
1430 {
1431 switch(address)
1432 {
1433 // BG2 reference X
1434 case 0x28:
1435 affine_reference_x[0] = (s32)(value << 4) >> 4;
1436 address32(io_registers, 0x28) = value;
1437 break;
1438
1439 // BG2 reference Y
1440 case 0x2C:
1441 affine_reference_y[0] = (s32)(value << 4) >> 4;
1442 address32(io_registers, 0x2C) = value;
1443 break;
1444
1445 // BG3 reference X
1446 case 0x38:
1447 affine_reference_x[1] = (s32)(value << 4) >> 4;
1448 address32(io_registers, 0x38) = value;
1449 break;
1450
1451 // BG3 reference Y
1452 case 0x3C:
1453 affine_reference_y[1] = (s32)(value << 4) >> 4;
1454 address32(io_registers, 0x3C) = value;
1455 break;
1456
1457 // Sound FIFO A
1458 case 0xA0:
1459 sound_timer_queue32(0, value);
1460 break;
1461
1462 // Sound FIFO B
1463 case 0xA4:
1464 sound_timer_queue32(1, value);
1465 break;
1466
1467 default:
1468 {
1469 cpu_alert_type alert_low =
1470 write_io_register16(address, value & 0xFFFF);
1471
1472 cpu_alert_type alert_high =
1473 write_io_register16(address + 2, value >> 16);
1474
1475 if(alert_high)
1476 return alert_high;
1477
1478 return alert_low;
1479 }
1480 }
1481
1482 return CPU_ALERT_NONE;
1483 }
1484
1485 #define write_palette8(address, value) \
1486
1487 #define write_palette16(address, value) \
1488 { \
1489 u32 palette_address = address; \
1490 address16(palette_ram, palette_address) = value; \
1491 convert_palette(value); \
1492 address16(palette_ram_converted, palette_address) = value; \
1493 } \
1494
1495 #define write_palette32(address, value) \
1496 { \
1497 u32 palette_address = address; \
1498 u32 value_high = value >> 16; \
1499 u32 value_low = value & 0xFFFF; \
1500 address32(palette_ram, palette_address) = value; \
1501 convert_palette(value_high); \
1502 convert_palette(value_low); \
1503 value = (value_high << 16) | value_low; \
1504 address32(palette_ram_converted, palette_address) = value; \
1505 } \
1506
1507
write_backup(u32 address,u32 value)1508 void write_backup(u32 address, u32 value)
1509 {
1510 value &= 0xFF;
1511
1512 if(backup_type == BACKUP_NONE)
1513 backup_type = BACKUP_SRAM;
1514
1515
1516 // gamepak SRAM or Flash ROM
1517 if((address == 0x5555) && (flash_mode != FLASH_WRITE_MODE))
1518 {
1519 if((flash_command_position == 0) && (value == 0xAA))
1520 {
1521 backup_type = BACKUP_FLASH;
1522 flash_command_position = 1;
1523 }
1524
1525 if(flash_command_position == 2)
1526 {
1527 switch(value)
1528 {
1529 case 0x90:
1530 // Enter ID mode, this also tells the emulator that we're using
1531 // flash, not SRAM
1532
1533 if(flash_mode == FLASH_BASE_MODE)
1534 flash_mode = FLASH_ID_MODE;
1535
1536 break;
1537
1538 case 0x80:
1539 // Enter erase mode
1540 if(flash_mode == FLASH_BASE_MODE)
1541 flash_mode = FLASH_ERASE_MODE;
1542 break;
1543
1544 case 0xF0:
1545 // Terminate ID mode
1546 if(flash_mode == FLASH_ID_MODE)
1547 flash_mode = FLASH_BASE_MODE;
1548 break;
1549
1550 case 0xA0:
1551 // Write mode
1552 if(flash_mode == FLASH_BASE_MODE)
1553 flash_mode = FLASH_WRITE_MODE;
1554 break;
1555
1556 case 0xB0:
1557 // Bank switch
1558 // Here the chip is now officially 128KB.
1559 flash_size = FLASH_SIZE_128KB;
1560 if(flash_mode == FLASH_BASE_MODE)
1561 flash_mode = FLASH_BANKSWITCH_MODE;
1562 break;
1563
1564 case 0x10:
1565 // Erase chip
1566 if(flash_mode == FLASH_ERASE_MODE)
1567 {
1568 if(flash_size == FLASH_SIZE_64KB)
1569 memset(gamepak_backup, 0xFF, 1024 * 64);
1570 else
1571 memset(gamepak_backup, 0xFF, 1024 * 128);
1572 flash_mode = FLASH_BASE_MODE;
1573 }
1574 break;
1575
1576 default:
1577 break;
1578 }
1579 flash_command_position = 0;
1580 }
1581 if(backup_type == BACKUP_SRAM)
1582 gamepak_backup[0x5555] = value;
1583 }
1584 else
1585
1586 if((address == 0x2AAA) && (value == 0x55) &&
1587 (flash_command_position == 1))
1588 flash_command_position = 2;
1589 else
1590 {
1591 if((flash_command_position == 2) &&
1592 (flash_mode == FLASH_ERASE_MODE) && (value == 0x30))
1593 {
1594 // Erase sector
1595 memset(flash_bank_ptr + (address & 0xF000), 0xFF, 1024 * 4);
1596 flash_mode = FLASH_BASE_MODE;
1597 flash_command_position = 0;
1598 }
1599 else
1600
1601 if((flash_command_position == 0) &&
1602 (flash_mode == FLASH_BANKSWITCH_MODE) && (address == 0x0000) &&
1603 (flash_size == FLASH_SIZE_128KB))
1604 {
1605 flash_bank_ptr = gamepak_backup + ((value & 0x01) * (1024 * 64));
1606 flash_mode = FLASH_BASE_MODE;
1607 }
1608 else
1609
1610 if((flash_command_position == 0) && (flash_mode == FLASH_WRITE_MODE))
1611 {
1612 // Write value to flash ROM
1613 flash_bank_ptr[address] = value;
1614 flash_mode = FLASH_BASE_MODE;
1615 }
1616 else
1617
1618 if(backup_type == BACKUP_SRAM)
1619 {
1620 // Write value to SRAM
1621 // Hit 64KB territory?
1622 if(address >= 0x8000)
1623 sram_size = SRAM_SIZE_64KB;
1624 gamepak_backup[address] = value;
1625 }
1626 }
1627 }
1628
1629 #define write_backup8() \
1630 write_backup(address & 0xFFFF, value) \
1631
1632 #define write_backup16() \
1633
1634 #define write_backup32() \
1635
1636 #define write_vram8() \
1637 address &= ~0x01; \
1638 address16(vram, address) = ((value << 8) | value) \
1639
1640 #define write_vram16() \
1641 address16(vram, address) = value \
1642
1643 #define write_vram32() \
1644 address32(vram, address) = value \
1645
1646 // RTC code derived from VBA's (due to lack of any real publically available
1647 // documentation...)
1648
1649 typedef enum
1650 {
1651 RTC_DISABLED,
1652 RTC_IDLE,
1653 RTC_COMMAND,
1654 RTC_OUTPUT_DATA,
1655 RTC_INPUT_DATA
1656 } rtc_state_type;
1657
1658 typedef enum
1659 {
1660 RTC_COMMAND_RESET = 0x60,
1661 RTC_COMMAND_WRITE_STATUS = 0x62,
1662 RTC_COMMAND_READ_STATUS = 0x63,
1663 RTC_COMMAND_OUTPUT_TIME_FULL = 0x65,
1664 RTC_COMMAND_OUTPUT_TIME = 0x67
1665 } rtc_command_type;
1666
1667 typedef enum
1668 {
1669 RTC_WRITE_TIME,
1670 RTC_WRITE_TIME_FULL,
1671 RTC_WRITE_STATUS
1672 } rtc_write_mode_type;
1673
1674 rtc_state_type rtc_state = RTC_DISABLED;
1675 rtc_write_mode_type rtc_write_mode;
1676 u8 rtc_registers[3];
1677 u32 rtc_command;
1678 u32 rtc_data[12];
1679 u32 rtc_status = 0x40;
1680 u32 rtc_data_bytes;
1681 s32 rtc_bit_count;
1682
encode_bcd(u8 value)1683 static u32 encode_bcd(u8 value)
1684 {
1685 int l = 0;
1686 int h = 0;
1687
1688 value = value % 100;
1689 l = value % 10;
1690 h = value / 10;
1691
1692 return h * 16 + l;
1693 }
1694
1695 #define write_rtc_register(index, _value) \
1696 update_address = 0x80000C4 + (index * 2); \
1697 rtc_registers[index] = _value; \
1698 rtc_page_index = update_address >> 15; \
1699 map = memory_map_read[rtc_page_index]; \
1700 \
1701 if(!map) \
1702 map = load_gamepak_page(rtc_page_index & 0x3FF); \
1703 \
1704 address16(map, update_address & 0x7FFF) = _value \
1705
write_rtc(u32 address,u32 value)1706 void write_rtc(u32 address, u32 value)
1707 {
1708 u32 rtc_page_index;
1709 u32 update_address;
1710 u8 *map;
1711
1712 value &= 0xFFFF;
1713
1714 switch(address)
1715 {
1716 // RTC command
1717 // Bit 0: SCHK, perform action
1718 // Bit 1: IO, input/output command data
1719 // Bit 2: CS, select input/output? If high make I/O write only
1720 case 0xC4:
1721 if(rtc_state == RTC_DISABLED)
1722 rtc_state = RTC_IDLE;
1723 if(!(rtc_registers[0] & 0x04))
1724 value = (rtc_registers[0] & 0x02) | (value & ~0x02);
1725 if(rtc_registers[2] & 0x01)
1726 {
1727 // To begin writing a command 1, 5 must be written to the command
1728 // registers.
1729 if((rtc_state == RTC_IDLE) && (rtc_registers[0] == 0x01) &&
1730 (value == 0x05))
1731 {
1732 // We're now ready to begin receiving a command.
1733 write_rtc_register(0, value);
1734 rtc_state = RTC_COMMAND;
1735 rtc_command = 0;
1736 rtc_bit_count = 7;
1737 }
1738 else
1739 {
1740 write_rtc_register(0, value);
1741 switch(rtc_state)
1742 {
1743 // Accumulate RTC command by receiving the next bit, and if we
1744 // have accumulated enough bits to form a complete command
1745 // execute it.
1746 case RTC_COMMAND:
1747 if(rtc_registers[0] & 0x01)
1748 {
1749 rtc_command |= ((value & 0x02) >> 1) << rtc_bit_count;
1750 rtc_bit_count--;
1751 }
1752
1753 // Have we received a full RTC command? If so execute it.
1754 if(rtc_bit_count < 0)
1755 {
1756 switch(rtc_command)
1757 {
1758 // Resets RTC
1759 case RTC_COMMAND_RESET:
1760 rtc_state = RTC_IDLE;
1761 memset(rtc_registers, 0, sizeof(rtc_registers));
1762 break;
1763
1764 // Sets status of RTC
1765 case RTC_COMMAND_WRITE_STATUS:
1766 rtc_state = RTC_INPUT_DATA;
1767 rtc_data_bytes = 1;
1768 rtc_write_mode = RTC_WRITE_STATUS;
1769 break;
1770
1771 // Outputs current status of RTC
1772 case RTC_COMMAND_READ_STATUS:
1773 rtc_state = RTC_OUTPUT_DATA;
1774 rtc_data_bytes = 1;
1775 rtc_data[0] = rtc_status;
1776 break;
1777
1778 // Actually outputs the time, all of it
1779 case RTC_COMMAND_OUTPUT_TIME_FULL:
1780 {
1781 struct tm *current_time;
1782 time_t current_time_flat;
1783
1784 time(¤t_time_flat);
1785 current_time = localtime(¤t_time_flat);
1786
1787 rtc_state = RTC_OUTPUT_DATA;
1788 rtc_data_bytes = 7;
1789 rtc_data[0] = encode_bcd(current_time->tm_year);
1790 rtc_data[1] = encode_bcd(current_time->tm_mon + 1);
1791 rtc_data[2] = encode_bcd(current_time->tm_mday);
1792 rtc_data[3] = encode_bcd(current_time->tm_wday);
1793 rtc_data[4] = encode_bcd(current_time->tm_hour);
1794 rtc_data[5] = encode_bcd(current_time->tm_min);
1795 rtc_data[6] = encode_bcd(current_time->tm_sec);
1796
1797 break;
1798 }
1799
1800 // Only outputs the current time of day.
1801 case RTC_COMMAND_OUTPUT_TIME:
1802 {
1803 struct tm *current_time;
1804 time_t current_time_flat;
1805
1806 time(¤t_time_flat);
1807 current_time = localtime(¤t_time_flat);
1808
1809 rtc_state = RTC_OUTPUT_DATA;
1810 rtc_data_bytes = 3;
1811 rtc_data[0] = encode_bcd(current_time->tm_hour);
1812 rtc_data[1] = encode_bcd(current_time->tm_min);
1813 rtc_data[2] = encode_bcd(current_time->tm_sec);
1814 break;
1815 }
1816 }
1817 rtc_bit_count = 0;
1818 }
1819 break;
1820
1821 // Receive parameters from the game as input to the RTC
1822 // for a given command. Read one bit at a time.
1823 case RTC_INPUT_DATA:
1824 // Bit 1 of parameter A must be high for input
1825 if(rtc_registers[1] & 0x02)
1826 {
1827 // Read next bit for input
1828 if(!(value & 0x01))
1829 {
1830 rtc_data[rtc_bit_count >> 3] |=
1831 ((value & 0x01) << (7 - (rtc_bit_count & 0x07)));
1832 }
1833 else
1834 {
1835 rtc_bit_count++;
1836
1837 if(rtc_bit_count == (rtc_data_bytes * 8))
1838 {
1839 rtc_state = RTC_IDLE;
1840 switch(rtc_write_mode)
1841 {
1842 case RTC_WRITE_STATUS:
1843 rtc_status = rtc_data[0];
1844 break;
1845
1846 default:
1847 break;
1848 }
1849 }
1850 }
1851 }
1852 break;
1853
1854 case RTC_OUTPUT_DATA:
1855 // Bit 1 of parameter A must be low for output
1856 if(!(rtc_registers[1] & 0x02))
1857 {
1858 // Write next bit to output, on bit 1 of parameter B
1859 if(!(value & 0x01))
1860 {
1861 u8 current_output_byte = rtc_registers[2];
1862
1863 current_output_byte =
1864 (current_output_byte & ~0x02) |
1865 (((rtc_data[rtc_bit_count >> 3] >>
1866 (rtc_bit_count & 0x07)) & 0x01) << 1);
1867
1868 write_rtc_register(0, current_output_byte);
1869
1870 }
1871 else
1872 {
1873 rtc_bit_count++;
1874
1875 if(rtc_bit_count == (rtc_data_bytes * 8))
1876 {
1877 rtc_state = RTC_IDLE;
1878 memset(rtc_registers, 0, sizeof(rtc_registers));
1879 }
1880 }
1881 }
1882 break;
1883
1884 default:
1885 break;
1886 }
1887 }
1888 }
1889 else
1890 {
1891 write_rtc_register(2, value);
1892 }
1893 break;
1894
1895 // Write parameter A
1896 case 0xC6:
1897 write_rtc_register(1, value);
1898 break;
1899
1900 // Write parameter B
1901 case 0xC8:
1902 write_rtc_register(2, value);
1903 break;
1904 }
1905 }
1906
1907 #define write_rtc8() \
1908
1909 #define write_rtc16() \
1910 write_rtc(address & 0xFF, value) \
1911
1912 #define write_rtc32() \
1913
1914 #define write_memory(type) \
1915 switch(address >> 24) \
1916 { \
1917 case 0x02: \
1918 /* external work RAM */ \
1919 address = (address & 0x7FFF) + ((address & 0x38000) * 2) + 0x8000; \
1920 address##type(ewram, address) = value; \
1921 break; \
1922 \
1923 case 0x03: \
1924 /* internal work RAM */ \
1925 address##type(iwram, (address & 0x7FFF) + 0x8000) = value; \
1926 break; \
1927 \
1928 case 0x04: \
1929 /* I/O registers */ \
1930 return write_io_register##type(address & 0x3FF, value); \
1931 \
1932 case 0x05: \
1933 /* palette RAM */ \
1934 write_palette##type(address & 0x3FF, value); \
1935 break; \
1936 \
1937 case 0x06: \
1938 /* VRAM */ \
1939 address &= 0x1FFFF; \
1940 if(address >= 0x18000) \
1941 address -= 0x8000; \
1942 \
1943 write_vram##type(); \
1944 break; \
1945 \
1946 case 0x07: \
1947 /* OAM RAM */ \
1948 oam_update = 1; \
1949 address##type(oam_ram, address & 0x3FF) = value; \
1950 break; \
1951 \
1952 case 0x08: \
1953 /* gamepak ROM or RTC */ \
1954 write_rtc##type(); \
1955 break; \
1956 \
1957 case 0x09: \
1958 case 0x0A: \
1959 case 0x0B: \
1960 case 0x0C: \
1961 /* gamepak ROM space */ \
1962 break; \
1963 \
1964 case 0x0D: \
1965 write_eeprom(address, value); \
1966 break; \
1967 \
1968 case 0x0E: \
1969 write_backup##type(); \
1970 break; \
1971 } \
1972
read_memory8(u32 address)1973 u8 read_memory8(u32 address)
1974 {
1975 u8 value;
1976 read_memory(8);
1977 return value;
1978 }
1979
read_memory16_signed(u32 address)1980 u16 read_memory16_signed(u32 address)
1981 {
1982 u16 value;
1983
1984 if(address & 0x01)
1985 return (s8)read_memory8(address);
1986
1987 read_memory(16);
1988
1989 return value;
1990 }
1991
1992 // unaligned reads are actually 32bit
1993
read_memory16(u32 address)1994 u32 read_memory16(u32 address)
1995 {
1996 u32 value;
1997
1998 if(address & 0x01)
1999 {
2000 address &= ~0x01;
2001 read_memory(16);
2002 ror(value, value, 8);
2003 }
2004 else
2005 {
2006 read_memory(16);
2007 }
2008
2009 return value;
2010 }
2011
2012
read_memory32(u32 address)2013 u32 read_memory32(u32 address)
2014 {
2015 u32 value;
2016 if(address & 0x03)
2017 {
2018 u32 rotate = (address & 0x03) * 8;
2019 address &= ~0x03;
2020 read_memory(32);
2021 ror(value, value, rotate);
2022 }
2023 else
2024 {
2025 read_memory(32);
2026 }
2027
2028 return value;
2029 }
2030
write_memory8(u32 address,u8 value)2031 cpu_alert_type write_memory8(u32 address, u8 value)
2032 {
2033 write_memory(8);
2034 return CPU_ALERT_NONE;
2035 }
2036
write_memory16(u32 address,u16 value)2037 cpu_alert_type write_memory16(u32 address, u16 value)
2038 {
2039 write_memory(16);
2040 return CPU_ALERT_NONE;
2041 }
2042
write_memory32(u32 address,u32 value)2043 cpu_alert_type write_memory32(u32 address, u32 value)
2044 {
2045 write_memory(32);
2046 return CPU_ALERT_NONE;
2047 }
2048
2049 char backup_filename[512];
2050
load_backup(char * name)2051 u32 load_backup(char *name)
2052 {
2053 file_open(backup_file, name, read);
2054
2055 if(file_check_valid(backup_file))
2056 {
2057 u32 backup_size = file_length(name, backup_file);
2058
2059 file_read(backup_file, gamepak_backup, backup_size);
2060
2061 file_close(backup_file);
2062
2063 // The size might give away what kind of backup it is.
2064 switch(backup_size)
2065 {
2066 case 0x200:
2067 backup_type = BACKUP_EEPROM;
2068 eeprom_size = EEPROM_512_BYTE;
2069 break;
2070
2071 case 0x2000:
2072 backup_type = BACKUP_EEPROM;
2073 eeprom_size = EEPROM_8_KBYTE;
2074 break;
2075
2076 case 0x8000:
2077 backup_type = BACKUP_SRAM;
2078 sram_size = SRAM_SIZE_32KB;
2079 break;
2080
2081 // Could be either flash or SRAM, go with flash
2082 case 0x10000:
2083 backup_type = BACKUP_FLASH;
2084 sram_size = (sram_size_type)FLASH_SIZE_64KB;
2085 break;
2086
2087 case 0x20000:
2088 backup_type = BACKUP_FLASH;
2089 flash_size = FLASH_SIZE_128KB;
2090 break;
2091 }
2092 return 1;
2093 }
2094 else
2095 {
2096 backup_type = BACKUP_NONE;
2097 memset(gamepak_backup, 0xFF, 1024 * 128);
2098 }
2099
2100 return 0;
2101 }
2102
save_backup(char * name)2103 u32 save_backup(char *name)
2104 {
2105 if(backup_type != BACKUP_NONE)
2106 {
2107 file_open(backup_file, name, write);
2108
2109 if(file_check_valid(backup_file))
2110 {
2111 u32 backup_size = 0;
2112
2113 switch(backup_type)
2114 {
2115 case BACKUP_SRAM:
2116 if(sram_size == SRAM_SIZE_32KB)
2117 backup_size = 0x8000;
2118 else
2119 backup_size = 0x10000;
2120 break;
2121
2122 case BACKUP_FLASH:
2123 if(flash_size == FLASH_SIZE_64KB)
2124 backup_size = 0x10000;
2125 else
2126 backup_size = 0x20000;
2127 break;
2128
2129 case BACKUP_EEPROM:
2130 if(eeprom_size == EEPROM_512_BYTE)
2131 backup_size = 0x200;
2132 else
2133 backup_size = 0x2000;
2134 break;
2135
2136 default:
2137 break;
2138 }
2139
2140 file_write(backup_file, gamepak_backup, backup_size);
2141
2142 file_close(backup_file);
2143 return 1;
2144 }
2145 }
2146
2147 return 0;
2148 }
2149
update_backup(void)2150 void update_backup(void)
2151 {
2152 if (!use_libretro_save_method)
2153 save_backup(backup_filename);
2154 }
2155
2156 #define CONFIG_FILENAME "game_config.txt"
2157
skip_spaces(char * line_ptr)2158 static char *skip_spaces(char *line_ptr)
2159 {
2160 while(*line_ptr == ' ')
2161 line_ptr++;
2162
2163 return line_ptr;
2164 }
2165
parse_config_line(char * current_line,char * current_variable,char * current_value)2166 static s32 parse_config_line(char *current_line, char *current_variable, char *current_value)
2167 {
2168 char *line_ptr = current_line;
2169 char *line_ptr_new;
2170
2171 if((current_line[0] == 0) || (current_line[0] == '#'))
2172 return -1;
2173
2174 line_ptr_new = strchr(line_ptr, ' ');
2175 if(!line_ptr_new)
2176 return -1;
2177
2178 *line_ptr_new = 0;
2179 strcpy(current_variable, line_ptr);
2180 line_ptr_new = skip_spaces(line_ptr_new + 1);
2181
2182 if(*line_ptr_new != '=')
2183 return -1;
2184
2185 line_ptr_new = skip_spaces(line_ptr_new + 1);
2186 strcpy(current_value, line_ptr_new);
2187 line_ptr_new = current_value + strlen(current_value) - 1;
2188 if(*line_ptr_new == '\n')
2189 {
2190 line_ptr_new--;
2191 *line_ptr_new = 0;
2192 }
2193
2194 if(*line_ptr_new == '\r')
2195 *line_ptr_new = 0;
2196
2197 return 0;
2198 }
2199
2200 typedef struct
2201 {
2202 char romtitle[256];
2203 char gamepak_title[256];
2204 char gamepak_code[256];
2205 char gamepak_maker[256];
2206 int flash_size;
2207 flash_device_id_type flash_device_id;
2208 int save_type;
2209 int rtc_enabled;
2210 int mirroring_enabled;
2211 int use_bios;
2212 u32 idle_loop_target_pc;
2213 u32 iwram_stack_optimize;
2214 u32 translation_gate_target_1;
2215 u32 translation_gate_target_2;
2216 u32 translation_gate_target_3;
2217 } ini_t;
2218
2219 #include "gba_over.h"
2220
load_game_config_over(char * gamepak_title,char * gamepak_code,char * gamepak_maker)2221 static s32 load_game_config_over(char *gamepak_title, char *gamepak_code, char *gamepak_maker)
2222 {
2223 unsigned i = 0;
2224
2225 for (i = 0; i < 256; i++)
2226 {
2227 if (gbaover[i].romtitle[0] == '\0')
2228 return -1;
2229
2230 if (strcmp(gbaover[i].gamepak_code, gamepak_code))
2231 continue;
2232
2233 if (strcmp(gbaover[i].gamepak_title, gamepak_title))
2234 continue;
2235
2236 printf("romtitle : %s\n", gbaover[i].romtitle);
2237 printf("gamepak title: %s\n", gbaover[i].gamepak_title);
2238 printf("gamepak code : %s\n", gbaover[i].gamepak_code);
2239 printf("gamepak maker: %s\n", gbaover[i].gamepak_maker);
2240
2241 printf("INPUT gamepak title: %s\n", gamepak_title);
2242 printf("INPUT gamepak code : %s\n", gamepak_code);
2243 printf("INPUT gamepak maker: %s\n", gamepak_maker);
2244
2245 if (gbaover[i].idle_loop_target_pc != 0)
2246 idle_loop_target_pc = gbaover[i].idle_loop_target_pc;
2247
2248 iwram_stack_optimize = gbaover[i].iwram_stack_optimize;
2249
2250 flash_device_id = gbaover[i].flash_device_id;
2251 if (flash_device_id == FLASH_DEVICE_MACRONIX_128KB)
2252 flash_size = FLASH_SIZE_128KB;
2253
2254 if (gbaover[i].translation_gate_target_1 != 0)
2255 {
2256 translation_gate_target_pc[translation_gate_targets] = gbaover[i].translation_gate_target_1;
2257 translation_gate_targets++;
2258 }
2259
2260 if (gbaover[i].translation_gate_target_2 != 0)
2261 {
2262 translation_gate_target_pc[translation_gate_targets] = gbaover[i].translation_gate_target_2;
2263 translation_gate_targets++;
2264 }
2265
2266 if (gbaover[i].translation_gate_target_3 != 0)
2267 {
2268 translation_gate_target_pc[translation_gate_targets] = gbaover[i].translation_gate_target_3;
2269 translation_gate_targets++;
2270 }
2271
2272 printf("found entry in over ini file.\n");
2273
2274 return 0;
2275 }
2276
2277 return -1;
2278 }
2279
load_game_config(char * gamepak_title,char * gamepak_code,char * gamepak_maker)2280 static s32 load_game_config(char *gamepak_title, char *gamepak_code, char *gamepak_maker)
2281 {
2282 char current_line[256];
2283 char current_variable[256];
2284 char current_value[256];
2285 char config_path[512];
2286 FILE *config_file;
2287
2288 sprintf(config_path, "%s" PATH_SEPARATOR "%s", main_path, CONFIG_FILENAME);
2289
2290 printf("config_path is : %s\n", config_path);
2291
2292 config_file = fopen(config_path, "rb");
2293
2294 if(config_file)
2295 {
2296 while(fgets(current_line, 256, config_file))
2297 {
2298 if(parse_config_line(current_line, current_variable, current_value)
2299 != -1)
2300 {
2301 if(strcmp(current_variable, "game_name") ||
2302 strcmp(current_value, gamepak_title))
2303 continue;
2304
2305 if(!fgets(current_line, 256, config_file) ||
2306 (parse_config_line(current_line, current_variable,
2307 current_value) == -1) ||
2308 strcmp(current_variable, "game_code") ||
2309 strcmp(current_value, gamepak_code))
2310 continue;
2311
2312 if(!fgets(current_line, 256, config_file) ||
2313 (parse_config_line(current_line, current_variable,
2314 current_value) == -1) ||
2315 strcmp(current_variable, "vender_code") ||
2316 strcmp(current_value, gamepak_maker))
2317 continue;
2318
2319 while(fgets(current_line, 256, config_file))
2320 {
2321 if(parse_config_line(current_line, current_variable, current_value)
2322 != -1)
2323 {
2324 if(!strcmp(current_variable, "game_name"))
2325 {
2326 fclose(config_file);
2327 return 0;
2328 }
2329
2330 if(!strcmp(current_variable, "idle_loop_eliminate_target"))
2331 idle_loop_target_pc = strtol(current_value, NULL, 16);
2332
2333 if(!strcmp(current_variable, "translation_gate_target"))
2334 {
2335 if(translation_gate_targets < MAX_TRANSLATION_GATES)
2336 {
2337 translation_gate_target_pc[translation_gate_targets] =
2338 strtol(current_value, NULL, 16);
2339 translation_gate_targets++;
2340 }
2341 }
2342
2343 if(!strcmp(current_variable, "iwram_stack_optimize") &&
2344 !strcmp(current_value, "no\0")) /* \0 for broken toolchain workaround */
2345 iwram_stack_optimize = 0;
2346
2347 if(!strcmp(current_variable, "flash_rom_type") &&
2348 !strcmp(current_value, "128KB"))
2349 flash_device_id = FLASH_DEVICE_MACRONIX_128KB;
2350 }
2351 }
2352
2353 fclose(config_file);
2354 return 0;
2355 }
2356 }
2357
2358 fclose(config_file);
2359 }
2360
2361 printf("game config missing\n");
2362 return -1;
2363 }
2364
load_gamepak_raw(const char * name)2365 static s32 load_gamepak_raw(const char *name)
2366 {
2367 file_open(gamepak_file, name, read);
2368
2369 if(file_check_valid(gamepak_file))
2370 {
2371 u32 file_size = file_length(name, gamepak_file);
2372
2373 // First, close the last one if it was open, we won't
2374 // be needing it anymore.
2375 if(file_check_valid(gamepak_file_large))
2376 file_close(gamepak_file_large);
2377
2378 // If it's a big file size keep it, don't close it, we'll
2379 // probably want to load from it more later.
2380 if(file_size <= gamepak_ram_buffer_size)
2381 {
2382 file_read(gamepak_file, gamepak_rom, file_size);
2383
2384 file_close(gamepak_file);
2385
2386 #ifdef PSP
2387 gamepak_file_large = -1;
2388 #else
2389 gamepak_file_large = NULL;
2390 #endif
2391 }
2392 else
2393 {
2394 // Read in just enough for the header
2395 file_read(gamepak_file, gamepak_rom, 0x100);
2396 gamepak_file_large = gamepak_file;
2397 }
2398
2399 return file_size;
2400 }
2401
2402 return -1;
2403 }
2404
2405 char gamepak_title[13];
2406 char gamepak_code[5];
2407 char gamepak_maker[3];
2408 char gamepak_filename[512];
2409
load_gamepak(const struct retro_game_info * info,const char * name)2410 u32 load_gamepak(const struct retro_game_info* info, const char *name)
2411 {
2412 char cheats_filename[256];
2413 char *p;
2414
2415 s32 file_size = load_gamepak_raw(name);
2416
2417 if(file_size == -1)
2418 return -1;
2419
2420 gamepak_size = (file_size + 0x7FFF) & ~0x7FFF;
2421
2422 strncpy(gamepak_filename, name, sizeof(gamepak_filename));
2423 gamepak_filename[sizeof(gamepak_filename) - 1] = 0;
2424
2425 p = strrchr(gamepak_filename, PATH_SEPARATOR_CHAR);
2426 if (p)
2427 p++;
2428 else
2429 p = gamepak_filename;
2430
2431 snprintf(backup_filename, sizeof(backup_filename), "%s%c%s", save_path, PATH_SEPARATOR_CHAR, p);
2432 p = strrchr(backup_filename, '.');
2433 if (p)
2434 strcpy(p, ".sav");
2435
2436 if (!use_libretro_save_method)
2437 load_backup(backup_filename);
2438
2439 memcpy(gamepak_title, gamepak_rom + 0xA0, 12);
2440 memcpy(gamepak_code, gamepak_rom + 0xAC, 4);
2441 memcpy(gamepak_maker, gamepak_rom + 0xB0, 2);
2442 gamepak_title[12] = 0;
2443 gamepak_code[4] = 0;
2444 gamepak_maker[2] = 0;
2445
2446 idle_loop_target_pc = 0xFFFFFFFF;
2447 iwram_stack_optimize = 1;
2448 translation_gate_targets = 0;
2449 flash_device_id = FLASH_DEVICE_MACRONIX_64KB;
2450 flash_size = FLASH_SIZE_64KB;
2451
2452 if ((load_game_config_over(gamepak_title, gamepak_code, gamepak_maker)) == -1)
2453 load_game_config(gamepak_title, gamepak_code, gamepak_maker);
2454
2455 change_ext(gamepak_filename, cheats_filename, ".cht");
2456 add_cheats(cheats_filename);
2457
2458 return 0;
2459 }
2460
load_bios(char * name)2461 s32 load_bios(char *name)
2462 {
2463 file_open(bios_file, name, read);
2464
2465 if(!(file_check_valid(bios_file)))
2466 return -1;
2467
2468 file_read(bios_file, bios_rom, 0x4000);
2469
2470 // This is a hack to get Zelda working, because emulating
2471 // the proper memory read behavior here is much too expensive.
2472 file_close(bios_file);
2473 return 0;
2474 }
2475
2476 // DMA memory regions can be one of the following:
2477 // IWRAM - 32kb offset from the contiguous iwram region.
2478 // EWRAM - like segmented but with self modifying code check.
2479 // VRAM - 96kb offset from the contiguous vram region, should take care
2480 // Palette RAM - Converts palette entries when written to.
2481 // OAM RAM - Sets OAM modified flag to true.
2482 // I/O registers - Uses the I/O register function.
2483 // of mirroring properly.
2484 // Segmented RAM/ROM - a region >= 32kb, the translated address has to
2485 // be reloaded if it wraps around the limit (cartride ROM)
2486 // Ext - should be handled by the memory read/write function.
2487
2488 // The following map determines the region of each (assumes DMA access
2489 // is not done out of bounds)
2490
2491 typedef enum
2492 {
2493 DMA_REGION_IWRAM,
2494 DMA_REGION_EWRAM,
2495 DMA_REGION_VRAM,
2496 DMA_REGION_PALETTE_RAM,
2497 DMA_REGION_OAM_RAM,
2498 DMA_REGION_IO,
2499 DMA_REGION_GAMEPAK,
2500 DMA_REGION_EXT,
2501 DMA_REGION_BIOS,
2502 DMA_REGION_NULL
2503 } dma_region_type;
2504
2505 dma_region_type dma_region_map[16] =
2506 {
2507 DMA_REGION_BIOS, // 0x00 - BIOS
2508 DMA_REGION_NULL, // 0x01 - Nothing
2509 DMA_REGION_EWRAM, // 0x02 - EWRAM
2510 DMA_REGION_IWRAM, // 0x03 - IWRAM
2511 DMA_REGION_IO, // 0x04 - I/O registers
2512 DMA_REGION_PALETTE_RAM, // 0x05 - palette RAM
2513 DMA_REGION_VRAM, // 0x06 - VRAM
2514 DMA_REGION_OAM_RAM, // 0x07 - OAM RAM
2515 DMA_REGION_GAMEPAK, // 0x08 - gamepak ROM
2516 DMA_REGION_GAMEPAK, // 0x09 - gamepak ROM
2517 DMA_REGION_GAMEPAK, // 0x0A - gamepak ROM
2518 DMA_REGION_GAMEPAK, // 0x0B - gamepak ROM
2519 DMA_REGION_GAMEPAK, // 0x0C - gamepak ROM
2520 DMA_REGION_EXT, // 0x0D - EEPROM
2521 DMA_REGION_EXT, // 0x0E - gamepak SRAM/flash ROM
2522 DMA_REGION_EXT // 0x0F - gamepak SRAM/flash ROM
2523 };
2524
2525 #define dma_adjust_ptr_inc(ptr, size) \
2526 ptr += (size / 8) \
2527
2528 #define dma_adjust_ptr_dec(ptr, size) \
2529 ptr -= (size / 8) \
2530
2531 #define dma_adjust_ptr_fix(ptr, size) \
2532
2533 #define dma_adjust_ptr_writeback() \
2534 dma->dest_address = dest_ptr \
2535
2536 #define dma_adjust_ptr_reload() \
2537
2538 #define dma_print(src_op, dest_op, transfer_size, wb) \
2539 printf("dma from %x (%s) to %x (%s) for %x (%s) (%s) (%d) (pc %x)\n", \
2540 src_ptr, #src_op, dest_ptr, #dest_op, length, #transfer_size, #wb, \
2541 dma->irq, reg[15]); \
2542
2543 #define dma_smc_vars_src() \
2544
2545 #define dma_smc_vars_dest() \
2546 u32 smc_trigger = 0 \
2547
2548 #define dma_vars_iwram(type) \
2549 dma_smc_vars_##type() \
2550
2551 #define dma_vars_vram(type) \
2552
2553 #define dma_vars_palette_ram(type) \
2554
2555 #define dma_oam_ram_src() \
2556
2557 #define dma_oam_ram_dest() \
2558 oam_update = 1 \
2559
2560 #define dma_vars_oam_ram(type) \
2561 dma_oam_ram_##type() \
2562
2563 #define dma_vars_io(type) \
2564
2565 #define dma_segmented_load_src() \
2566 memory_map_read[src_current_region] \
2567
2568 #define dma_segmented_load_dest() \
2569 memory_map_write[dest_current_region] \
2570
2571 #define dma_vars_gamepak(type) \
2572 u32 type##_new_region; \
2573 u32 type##_current_region = type##_ptr >> 15; \
2574 u8 *type##_address_block = dma_segmented_load_##type(); \
2575 if(type##_address_block == NULL) \
2576 { \
2577 if((type##_ptr & 0x1FFFFFF) >= gamepak_size) \
2578 break; \
2579 type##_address_block = load_gamepak_page(type##_current_region & 0x3FF); \
2580 } \
2581
2582 #define dma_vars_ewram(type) \
2583 dma_smc_vars_##type(); \
2584 u32 type##_new_region; \
2585 u32 type##_current_region = type##_ptr >> 15; \
2586 u8 *type##_address_block = dma_segmented_load_##type() \
2587
2588 #define dma_vars_bios(type) \
2589
2590 #define dma_vars_ext(type) \
2591
2592 #define dma_ewram_check_region(type) \
2593 type##_new_region = (type##_ptr >> 15); \
2594 if(type##_new_region != type##_current_region) \
2595 { \
2596 type##_current_region = type##_new_region; \
2597 type##_address_block = dma_segmented_load_##type(); \
2598 } \
2599
2600 #define dma_gamepak_check_region(type) \
2601 type##_new_region = (type##_ptr >> 15); \
2602 if(type##_new_region != type##_current_region) \
2603 { \
2604 type##_current_region = type##_new_region; \
2605 type##_address_block = dma_segmented_load_##type(); \
2606 if(type##_address_block == NULL) \
2607 { \
2608 type##_address_block = \
2609 load_gamepak_page(type##_current_region & 0x3FF); \
2610 } \
2611 } \
2612
2613 #define dma_read_iwram(type, transfer_size) \
2614 read_value = address##transfer_size(iwram + 0x8000, type##_ptr & 0x7FFF) \
2615
2616 #define dma_read_vram(type, transfer_size) \
2617 read_value = address##transfer_size(vram, type##_ptr & 0x1FFFF) \
2618
2619 #define dma_read_io(type, transfer_size) \
2620 read_value = address##transfer_size(io_registers, type##_ptr & 0x7FFF) \
2621
2622 #define dma_read_oam_ram(type, transfer_size) \
2623 read_value = address##transfer_size(oam_ram, type##_ptr & 0x3FF) \
2624
2625 #define dma_read_palette_ram(type, transfer_size) \
2626 read_value = address##transfer_size(palette_ram, type##_ptr & 0x3FF) \
2627
2628 #define dma_read_ewram(type, transfer_size) \
2629 dma_ewram_check_region(type); \
2630 read_value = address##transfer_size(type##_address_block, \
2631 type##_ptr & 0x7FFF) \
2632
2633 #define dma_read_gamepak(type, transfer_size) \
2634 dma_gamepak_check_region(type); \
2635 read_value = address##transfer_size(type##_address_block, \
2636 type##_ptr & 0x7FFF) \
2637
2638 // DMAing from the BIOS is funny, just returns 0..
2639
2640 #define dma_read_bios(type, transfer_size) \
2641 read_value = 0 \
2642
2643 #define dma_read_ext(type, transfer_size) \
2644 read_value = read_memory##transfer_size(type##_ptr) \
2645
2646 #define dma_write_iwram(type, transfer_size) \
2647 address##transfer_size(iwram + 0x8000, type##_ptr & 0x7FFF) = read_value; \
2648 smc_trigger |= address##transfer_size(iwram, type##_ptr & 0x7FFF) \
2649
2650 #define dma_write_vram(type, transfer_size) \
2651 address##transfer_size(vram, type##_ptr & 0x1FFFF) = read_value \
2652
2653 #define dma_write_io(type, transfer_size) \
2654 write_io_register##transfer_size(type##_ptr & 0x3FF, read_value) \
2655
2656 #define dma_write_oam_ram(type, transfer_size) \
2657 address##transfer_size(oam_ram, type##_ptr & 0x3FF) = read_value \
2658
2659 #define dma_write_palette_ram(type, transfer_size) \
2660 write_palette##transfer_size(type##_ptr & 0x3FF, read_value) \
2661
2662 #define dma_write_ext(type, transfer_size) \
2663 write_memory##transfer_size(type##_ptr, read_value) \
2664
2665 #define dma_write_ewram(type, transfer_size) \
2666 dma_ewram_check_region(type); \
2667 \
2668 address##transfer_size(type##_address_block, type##_ptr & 0x7FFF) = \
2669 read_value; \
2670 smc_trigger |= address##transfer_size(type##_address_block, \
2671 (type##_ptr & 0x7FFF) - 0x8000) \
2672
2673 #define dma_epilogue_iwram() \
2674 if(smc_trigger) \
2675 { \
2676 /* Special return code indicating to retranslate to the CPU code */ \
2677 return_value = CPU_ALERT_SMC; \
2678 } \
2679
2680 #define dma_epilogue_ewram() \
2681 if(smc_trigger) \
2682 { \
2683 /* Special return code indicating to retranslate to the CPU code */ \
2684 return_value = CPU_ALERT_SMC; \
2685 } \
2686
2687 #define dma_epilogue_vram() \
2688
2689 #define dma_epilogue_io() \
2690
2691 #define dma_epilogue_oam_ram() \
2692
2693 #define dma_epilogue_palette_ram() \
2694
2695 #define dma_epilogue_GAMEPAK() \
2696
2697 #define dma_epilogue_ext() \
2698
2699 #define print_line() \
2700 dma_print(src_op, dest_op, transfer_size, wb); \
2701
2702 #define dma_transfer_loop_region(src_region_type, dest_region_type, src_op, \
2703 dest_op, transfer_size, wb) \
2704 { \
2705 dma_vars_##src_region_type(src); \
2706 dma_vars_##dest_region_type(dest); \
2707 \
2708 for(i = 0; i < length; i++) \
2709 { \
2710 dma_read_##src_region_type(src, transfer_size); \
2711 dma_write_##dest_region_type(dest, transfer_size); \
2712 dma_adjust_ptr_##src_op(src_ptr, transfer_size); \
2713 dma_adjust_ptr_##dest_op(dest_ptr, transfer_size); \
2714 } \
2715 dma->source_address = src_ptr; \
2716 dma_adjust_ptr_##wb(); \
2717 dma_epilogue_##dest_region_type(); \
2718 break; \
2719 } \
2720
2721 #define dma_transfer_loop(src_op, dest_op, transfer_size, wb); \
2722 { \
2723 u32 src_region = src_ptr >> 24; \
2724 u32 dest_region = dest_ptr >> 24; \
2725 dma_region_type src_region_type = dma_region_map[src_region]; \
2726 dma_region_type dest_region_type = dma_region_map[dest_region]; \
2727 \
2728 switch(src_region_type | (dest_region_type << 4)) \
2729 { \
2730 case (DMA_REGION_BIOS | (DMA_REGION_IWRAM << 4)): \
2731 dma_transfer_loop_region(bios, iwram, src_op, dest_op, \
2732 transfer_size, wb); \
2733 \
2734 case (DMA_REGION_IWRAM | (DMA_REGION_IWRAM << 4)): \
2735 dma_transfer_loop_region(iwram, iwram, src_op, dest_op, \
2736 transfer_size, wb); \
2737 \
2738 case (DMA_REGION_EWRAM | (DMA_REGION_IWRAM << 4)): \
2739 dma_transfer_loop_region(ewram, iwram, src_op, dest_op, \
2740 transfer_size, wb); \
2741 \
2742 case (DMA_REGION_VRAM | (DMA_REGION_IWRAM << 4)): \
2743 dma_transfer_loop_region(vram, iwram, src_op, dest_op, \
2744 transfer_size, wb); \
2745 \
2746 case (DMA_REGION_PALETTE_RAM | (DMA_REGION_IWRAM << 4)): \
2747 dma_transfer_loop_region(palette_ram, iwram, src_op, dest_op, \
2748 transfer_size, wb); \
2749 \
2750 case (DMA_REGION_OAM_RAM | (DMA_REGION_IWRAM << 4)): \
2751 dma_transfer_loop_region(oam_ram, iwram, src_op, dest_op, \
2752 transfer_size, wb); \
2753 \
2754 case (DMA_REGION_IO | (DMA_REGION_IWRAM << 4)): \
2755 dma_transfer_loop_region(io, iwram, src_op, dest_op, \
2756 transfer_size, wb); \
2757 \
2758 case (DMA_REGION_GAMEPAK | (DMA_REGION_IWRAM << 4)): \
2759 dma_transfer_loop_region(gamepak, iwram, src_op, dest_op, \
2760 transfer_size, wb); \
2761 \
2762 case (DMA_REGION_EXT | (DMA_REGION_IWRAM << 4)): \
2763 dma_transfer_loop_region(ext, iwram, src_op, dest_op, \
2764 transfer_size, wb); \
2765 \
2766 case (DMA_REGION_BIOS | (DMA_REGION_EWRAM << 4)): \
2767 dma_transfer_loop_region(bios, ewram, src_op, dest_op, \
2768 transfer_size, wb); \
2769 \
2770 case (DMA_REGION_IWRAM | (DMA_REGION_EWRAM << 4)): \
2771 dma_transfer_loop_region(iwram, ewram, src_op, dest_op, \
2772 transfer_size, wb); \
2773 \
2774 case (DMA_REGION_EWRAM | (DMA_REGION_EWRAM << 4)): \
2775 dma_transfer_loop_region(ewram, ewram, src_op, dest_op, \
2776 transfer_size, wb); \
2777 \
2778 case (DMA_REGION_VRAM | (DMA_REGION_EWRAM << 4)): \
2779 dma_transfer_loop_region(vram, ewram, src_op, dest_op, \
2780 transfer_size, wb); \
2781 \
2782 case (DMA_REGION_PALETTE_RAM | (DMA_REGION_EWRAM << 4)): \
2783 dma_transfer_loop_region(palette_ram, ewram, src_op, dest_op, \
2784 transfer_size, wb); \
2785 \
2786 case (DMA_REGION_OAM_RAM | (DMA_REGION_EWRAM << 4)): \
2787 dma_transfer_loop_region(oam_ram, ewram, src_op, dest_op, \
2788 transfer_size, wb); \
2789 \
2790 case (DMA_REGION_IO | (DMA_REGION_EWRAM << 4)): \
2791 dma_transfer_loop_region(io, ewram, src_op, dest_op, \
2792 transfer_size, wb); \
2793 \
2794 case (DMA_REGION_GAMEPAK | (DMA_REGION_EWRAM << 4)): \
2795 dma_transfer_loop_region(gamepak, ewram, src_op, dest_op, \
2796 transfer_size, wb); \
2797 \
2798 case (DMA_REGION_EXT | (DMA_REGION_EWRAM << 4)): \
2799 dma_transfer_loop_region(ext, ewram, src_op, dest_op, \
2800 transfer_size, wb); \
2801 \
2802 case (DMA_REGION_BIOS | (DMA_REGION_VRAM << 4)): \
2803 dma_transfer_loop_region(bios, vram, src_op, dest_op, \
2804 transfer_size, wb); \
2805 \
2806 case (DMA_REGION_IWRAM | (DMA_REGION_VRAM << 4)): \
2807 dma_transfer_loop_region(iwram, vram, src_op, dest_op, \
2808 transfer_size, wb); \
2809 \
2810 case (DMA_REGION_EWRAM | (DMA_REGION_VRAM << 4)): \
2811 dma_transfer_loop_region(ewram, vram, src_op, dest_op, \
2812 transfer_size, wb); \
2813 \
2814 case (DMA_REGION_VRAM | (DMA_REGION_VRAM << 4)): \
2815 dma_transfer_loop_region(vram, vram, src_op, dest_op, \
2816 transfer_size, wb); \
2817 \
2818 case (DMA_REGION_PALETTE_RAM | (DMA_REGION_VRAM << 4)): \
2819 dma_transfer_loop_region(palette_ram, vram, src_op, dest_op, \
2820 transfer_size, wb); \
2821 \
2822 case (DMA_REGION_OAM_RAM | (DMA_REGION_VRAM << 4)): \
2823 dma_transfer_loop_region(oam_ram, vram, src_op, dest_op, \
2824 transfer_size, wb); \
2825 \
2826 case (DMA_REGION_IO | (DMA_REGION_VRAM << 4)): \
2827 dma_transfer_loop_region(io, vram, src_op, dest_op, \
2828 transfer_size, wb); \
2829 \
2830 case (DMA_REGION_GAMEPAK | (DMA_REGION_VRAM << 4)): \
2831 dma_transfer_loop_region(gamepak, vram, src_op, dest_op, \
2832 transfer_size, wb); \
2833 \
2834 case (DMA_REGION_EXT | (DMA_REGION_VRAM << 4)): \
2835 dma_transfer_loop_region(ext, vram, src_op, dest_op, \
2836 transfer_size, wb); \
2837 \
2838 case (DMA_REGION_BIOS | (DMA_REGION_PALETTE_RAM << 4)): \
2839 dma_transfer_loop_region(bios, palette_ram, src_op, dest_op, \
2840 transfer_size, wb); \
2841 \
2842 case (DMA_REGION_IWRAM | (DMA_REGION_PALETTE_RAM << 4)): \
2843 dma_transfer_loop_region(iwram, palette_ram, src_op, dest_op, \
2844 transfer_size, wb); \
2845 \
2846 case (DMA_REGION_EWRAM | (DMA_REGION_PALETTE_RAM << 4)): \
2847 dma_transfer_loop_region(ewram, palette_ram, src_op, dest_op, \
2848 transfer_size, wb); \
2849 \
2850 case (DMA_REGION_VRAM | (DMA_REGION_PALETTE_RAM << 4)): \
2851 dma_transfer_loop_region(vram, palette_ram, src_op, dest_op, \
2852 transfer_size, wb); \
2853 \
2854 case (DMA_REGION_PALETTE_RAM | (DMA_REGION_PALETTE_RAM << 4)): \
2855 dma_transfer_loop_region(palette_ram, palette_ram, src_op, dest_op, \
2856 transfer_size, wb); \
2857 \
2858 case (DMA_REGION_OAM_RAM | (DMA_REGION_PALETTE_RAM << 4)): \
2859 dma_transfer_loop_region(oam_ram, palette_ram, src_op, dest_op, \
2860 transfer_size, wb); \
2861 \
2862 case (DMA_REGION_IO | (DMA_REGION_PALETTE_RAM << 4)): \
2863 dma_transfer_loop_region(io, palette_ram, src_op, dest_op, \
2864 transfer_size, wb); \
2865 \
2866 case (DMA_REGION_GAMEPAK | (DMA_REGION_PALETTE_RAM << 4)): \
2867 dma_transfer_loop_region(gamepak, palette_ram, src_op, dest_op, \
2868 transfer_size, wb); \
2869 \
2870 case (DMA_REGION_EXT | (DMA_REGION_PALETTE_RAM << 4)): \
2871 dma_transfer_loop_region(ext, palette_ram, src_op, dest_op, \
2872 transfer_size, wb); \
2873 \
2874 case (DMA_REGION_BIOS | (DMA_REGION_OAM_RAM << 4)): \
2875 dma_transfer_loop_region(bios, oam_ram, src_op, dest_op, \
2876 transfer_size, wb); \
2877 \
2878 case (DMA_REGION_IWRAM | (DMA_REGION_OAM_RAM << 4)): \
2879 dma_transfer_loop_region(iwram, oam_ram, src_op, dest_op, \
2880 transfer_size, wb); \
2881 \
2882 case (DMA_REGION_EWRAM | (DMA_REGION_OAM_RAM << 4)): \
2883 dma_transfer_loop_region(ewram, oam_ram, src_op, dest_op, \
2884 transfer_size, wb); \
2885 \
2886 case (DMA_REGION_VRAM | (DMA_REGION_OAM_RAM << 4)): \
2887 dma_transfer_loop_region(vram, oam_ram, src_op, dest_op, \
2888 transfer_size, wb); \
2889 \
2890 case (DMA_REGION_PALETTE_RAM | (DMA_REGION_OAM_RAM << 4)): \
2891 dma_transfer_loop_region(palette_ram, oam_ram, src_op, dest_op, \
2892 transfer_size, wb); \
2893 \
2894 case (DMA_REGION_OAM_RAM | (DMA_REGION_OAM_RAM << 4)): \
2895 dma_transfer_loop_region(oam_ram, oam_ram, src_op, dest_op, \
2896 transfer_size, wb); \
2897 \
2898 case (DMA_REGION_IO | (DMA_REGION_OAM_RAM << 4)): \
2899 dma_transfer_loop_region(io, oam_ram, src_op, dest_op, \
2900 transfer_size, wb); \
2901 \
2902 case (DMA_REGION_GAMEPAK | (DMA_REGION_OAM_RAM << 4)): \
2903 dma_transfer_loop_region(gamepak, oam_ram, src_op, dest_op, \
2904 transfer_size, wb); \
2905 \
2906 case (DMA_REGION_EXT | (DMA_REGION_OAM_RAM << 4)): \
2907 dma_transfer_loop_region(ext, oam_ram, src_op, dest_op, \
2908 transfer_size, wb); \
2909 \
2910 case (DMA_REGION_BIOS | (DMA_REGION_IO << 4)): \
2911 dma_transfer_loop_region(bios, io, src_op, dest_op, \
2912 transfer_size, wb); \
2913 \
2914 case (DMA_REGION_IWRAM | (DMA_REGION_IO << 4)): \
2915 dma_transfer_loop_region(iwram, io, src_op, dest_op, \
2916 transfer_size, wb); \
2917 \
2918 case (DMA_REGION_EWRAM | (DMA_REGION_IO << 4)): \
2919 dma_transfer_loop_region(ewram, io, src_op, dest_op, \
2920 transfer_size, wb); \
2921 \
2922 case (DMA_REGION_VRAM | (DMA_REGION_IO << 4)): \
2923 dma_transfer_loop_region(vram, io, src_op, dest_op, \
2924 transfer_size, wb); \
2925 \
2926 case (DMA_REGION_PALETTE_RAM | (DMA_REGION_IO << 4)): \
2927 dma_transfer_loop_region(palette_ram, io, src_op, dest_op, \
2928 transfer_size, wb); \
2929 \
2930 case (DMA_REGION_OAM_RAM | (DMA_REGION_IO << 4)): \
2931 dma_transfer_loop_region(oam_ram, io, src_op, dest_op, \
2932 transfer_size, wb); \
2933 \
2934 case (DMA_REGION_IO | (DMA_REGION_IO << 4)): \
2935 dma_transfer_loop_region(io, io, src_op, dest_op, \
2936 transfer_size, wb); \
2937 \
2938 case (DMA_REGION_GAMEPAK | (DMA_REGION_IO << 4)): \
2939 dma_transfer_loop_region(gamepak, io, src_op, dest_op, \
2940 transfer_size, wb); \
2941 \
2942 case (DMA_REGION_EXT | (DMA_REGION_IO << 4)): \
2943 dma_transfer_loop_region(ext, io, src_op, dest_op, \
2944 transfer_size, wb); \
2945 \
2946 case (DMA_REGION_BIOS | (DMA_REGION_EXT << 4)): \
2947 dma_transfer_loop_region(bios, ext, src_op, dest_op, \
2948 transfer_size, wb); \
2949 \
2950 case (DMA_REGION_IWRAM | (DMA_REGION_EXT << 4)): \
2951 dma_transfer_loop_region(iwram, ext, src_op, dest_op, \
2952 transfer_size, wb); \
2953 \
2954 case (DMA_REGION_EWRAM | (DMA_REGION_EXT << 4)): \
2955 dma_transfer_loop_region(ewram, ext, src_op, dest_op, \
2956 transfer_size, wb); \
2957 \
2958 case (DMA_REGION_VRAM | (DMA_REGION_EXT << 4)): \
2959 dma_transfer_loop_region(vram, ext, src_op, dest_op, \
2960 transfer_size, wb); \
2961 \
2962 case (DMA_REGION_PALETTE_RAM | (DMA_REGION_EXT << 4)): \
2963 dma_transfer_loop_region(palette_ram, ext, src_op, dest_op, \
2964 transfer_size, wb); \
2965 \
2966 case (DMA_REGION_OAM_RAM | (DMA_REGION_EXT << 4)): \
2967 dma_transfer_loop_region(oam_ram, ext, src_op, dest_op, \
2968 transfer_size, wb); \
2969 \
2970 case (DMA_REGION_IO | (DMA_REGION_EXT << 4)): \
2971 dma_transfer_loop_region(io, ext, src_op, dest_op, \
2972 transfer_size, wb); \
2973 \
2974 case (DMA_REGION_GAMEPAK | (DMA_REGION_EXT << 4)): \
2975 dma_transfer_loop_region(gamepak, ext, src_op, dest_op, \
2976 transfer_size, wb); \
2977 \
2978 case (DMA_REGION_EXT | (DMA_REGION_EXT << 3)): \
2979 dma_transfer_loop_region(ext, ext, src_op, dest_op, \
2980 transfer_size, wb); \
2981 } \
2982 break; \
2983 } \
2984
dma_transfer(dma_transfer_type * dma)2985 cpu_alert_type dma_transfer(dma_transfer_type *dma)
2986 {
2987 u32 i;
2988 u32 length = dma->length;
2989 u32 read_value;
2990 u32 src_ptr = dma->source_address;
2991 uintptr_t dest_ptr = dma->dest_address;
2992 cpu_alert_type return_value = CPU_ALERT_NONE;
2993
2994 // Technically this should be done for source and destination, but
2995 // chances are this is only ever used (probably mistakingly!) for dest.
2996 // The only game I know of that requires this is Lucky Luke.
2997 if((dest_ptr >> 24) != ((dest_ptr + length - 1) >> 24))
2998 {
2999 u32 first_length = ((dest_ptr & 0xFF000000) + 0x1000000) - dest_ptr;
3000 u32 second_length = length - first_length;
3001 dma->length = first_length;
3002
3003 dma_transfer(dma);
3004
3005 dma->length = length;
3006
3007 length = second_length;
3008 dest_ptr += first_length;
3009 src_ptr += first_length;
3010 }
3011
3012 if(dma->length_type == DMA_16BIT)
3013 {
3014 src_ptr &= ~0x01;
3015 dest_ptr &= ~0x01;
3016 cycle_dma16_words += length;
3017
3018 switch((dma->dest_direction << 2) | dma->source_direction)
3019 {
3020 case 0x00:
3021 dma_transfer_loop(inc, inc, 16, writeback);
3022 case 0x01:
3023 dma_transfer_loop(dec, inc, 16, writeback);
3024 case 0x02:
3025 dma_transfer_loop(fix, inc, 16, writeback);
3026 case 0x03:
3027 break;
3028 case 0x04:
3029 dma_transfer_loop(inc, dec, 16, writeback);
3030 case 0x05:
3031 dma_transfer_loop(dec, dec, 16, writeback);
3032 case 0x06:
3033 dma_transfer_loop(fix, dec, 16, writeback);
3034 case 0x07:
3035 break;
3036 case 0x08:
3037 dma_transfer_loop(inc, fix, 16, writeback);
3038 case 0x09:
3039 dma_transfer_loop(dec, fix, 16, writeback);
3040 case 0x0A:
3041 dma_transfer_loop(fix, fix, 16, writeback);
3042 case 0x0B:
3043 break;
3044 case 0x0C:
3045 dma_transfer_loop(inc, inc, 16, reload);
3046 case 0x0D:
3047 dma_transfer_loop(dec, inc, 16, reload);
3048 case 0x0E:
3049 dma_transfer_loop(fix, inc, 16, reload);
3050 case 0x0F:
3051 break;
3052 }
3053 }
3054 else
3055 {
3056 src_ptr &= ~0x03;
3057 dest_ptr &= ~0x03;
3058 cycle_dma32_words += length;
3059
3060 switch((dma->dest_direction << 2) | dma->source_direction)
3061 {
3062 case 0x00:
3063 dma_transfer_loop(inc, inc, 32, writeback);
3064 case 0x01:
3065 dma_transfer_loop(dec, inc, 32, writeback);
3066 case 0x02:
3067 dma_transfer_loop(fix, inc, 32, writeback);
3068 case 0x03:
3069 break;
3070 case 0x04:
3071 dma_transfer_loop(inc, dec, 32, writeback);
3072 case 0x05:
3073 dma_transfer_loop(dec, dec, 32, writeback);
3074 case 0x06:
3075 dma_transfer_loop(fix, dec, 32, writeback);
3076 case 0x07:
3077 break;
3078 case 0x08:
3079 dma_transfer_loop(inc, fix, 32, writeback);
3080 case 0x09:
3081 dma_transfer_loop(dec, fix, 32, writeback);
3082 case 0x0A:
3083 dma_transfer_loop(fix, fix, 32, writeback);
3084 case 0x0B:
3085 break;
3086 case 0x0C:
3087 dma_transfer_loop(inc, inc, 32, reload);
3088 case 0x0D:
3089 dma_transfer_loop(dec, inc, 32, reload);
3090 case 0x0E:
3091 dma_transfer_loop(fix, inc, 32, reload);
3092 case 0x0F:
3093 break;
3094 }
3095 }
3096
3097 if((dma->repeat_type == DMA_NO_REPEAT) ||
3098 (dma->start_type == DMA_START_IMMEDIATELY))
3099 {
3100 dma->start_type = DMA_INACTIVE;
3101 address16(io_registers, (dma->dma_channel * 12) + 0xBA) &=
3102 (~0x8000);
3103 }
3104
3105 if(dma->irq)
3106 {
3107 raise_interrupt(IRQ_DMA0 << dma->dma_channel);
3108 return_value = CPU_ALERT_IRQ;
3109 }
3110
3111 return return_value;
3112 }
3113
3114 // Be sure to do this after loading ROMs.
3115
3116 #define map_region(type, start, end, mirror_blocks, region) \
3117 for(map_offset = (start) / 0x8000; map_offset < \
3118 ((end) / 0x8000); map_offset++) \
3119 { \
3120 memory_map_##type[map_offset] = \
3121 ((u8 *)region) + ((map_offset % mirror_blocks) * 0x8000); \
3122 } \
3123
3124 #define map_null(type, start, end) \
3125 for(map_offset = start / 0x8000; map_offset < (end / 0x8000); \
3126 map_offset++) \
3127 memory_map_##type[map_offset] = NULL; \
3128
3129 #define map_ram_region(type, start, end, mirror_blocks, region) \
3130 for(map_offset = (start) / 0x8000; map_offset < \
3131 ((end) / 0x8000); map_offset++) \
3132 { \
3133 memory_map_##type[map_offset] = \
3134 ((u8 *)region) + ((map_offset % mirror_blocks) * 0x10000) + 0x8000; \
3135 } \
3136
3137 #define map_vram(type) \
3138 for(map_offset = 0x6000000 / 0x8000; map_offset < (0x7000000 / 0x8000); \
3139 map_offset += 4) \
3140 { \
3141 memory_map_##type[map_offset] = vram; \
3142 memory_map_##type[map_offset + 1] = vram + 0x8000; \
3143 memory_map_##type[map_offset + 2] = vram + (0x8000 * 2); \
3144 memory_map_##type[map_offset + 3] = vram + (0x8000 * 2); \
3145 } \
3146
3147
3148 // Picks a page to evict
3149 u32 page_time = 0;
3150
evict_gamepak_page(void)3151 static u32 evict_gamepak_page(void)
3152 {
3153 // Find the one with the smallest frame timestamp
3154 u32 page_index = 0;
3155 u32 physical_index;
3156 u32 smallest = gamepak_memory_map[0].page_timestamp;
3157 u32 i;
3158
3159 for(i = 1; i < gamepak_ram_pages; i++)
3160 {
3161 if(gamepak_memory_map[i].page_timestamp <= smallest)
3162 {
3163 smallest = gamepak_memory_map[i].page_timestamp;
3164 page_index = i;
3165 }
3166 }
3167
3168 physical_index = gamepak_memory_map[page_index].physical_index;
3169
3170 memory_map_read[(0x8000000 / (32 * 1024)) + physical_index] = NULL;
3171 memory_map_read[(0xA000000 / (32 * 1024)) + physical_index] = NULL;
3172 memory_map_read[(0xC000000 / (32 * 1024)) + physical_index] = NULL;
3173
3174 return page_index;
3175 }
3176
load_gamepak_page(u32 physical_index)3177 u8 *load_gamepak_page(u32 physical_index)
3178 {
3179 if(physical_index >= (gamepak_size >> 15))
3180 return gamepak_rom;
3181
3182 u32 page_index = evict_gamepak_page();
3183 u32 page_offset = page_index * (32 * 1024);
3184 u8 *swap_location = gamepak_rom + page_offset;
3185
3186 gamepak_memory_map[page_index].page_timestamp = page_time;
3187 gamepak_memory_map[page_index].physical_index = physical_index;
3188 page_time++;
3189
3190 file_seek(gamepak_file_large, physical_index * (32 * 1024), SEEK_SET);
3191 file_read(gamepak_file_large, swap_location, (32 * 1024));
3192 memory_map_read[(0x8000000 / (32 * 1024)) + physical_index] = swap_location;
3193 memory_map_read[(0xA000000 / (32 * 1024)) + physical_index] = swap_location;
3194 memory_map_read[(0xC000000 / (32 * 1024)) + physical_index] = swap_location;
3195
3196 // If RTC is active page the RTC register bytes so they can be read
3197 if((rtc_state != RTC_DISABLED) && (physical_index == 0))
3198 memcpy(swap_location + 0xC4, rtc_registers, sizeof(rtc_registers));
3199
3200 return swap_location;
3201 }
3202
init_memory_gamepak(void)3203 static void init_memory_gamepak(void)
3204 {
3205 u32 map_offset = 0;
3206
3207 if(gamepak_size > gamepak_ram_buffer_size)
3208 {
3209 // Large ROMs get special treatment because they
3210 // can't fit into the 16MB ROM buffer.
3211 u32 i;
3212 for(i = 0; i < gamepak_ram_pages; i++)
3213 {
3214 gamepak_memory_map[i].page_timestamp = 0;
3215 gamepak_memory_map[i].physical_index = 0;
3216 }
3217
3218 map_null(read, 0x8000000, 0xD000000);
3219 }
3220 else
3221 {
3222 map_region(read, 0x8000000, 0x8000000 + gamepak_size, 1024, gamepak_rom);
3223 map_null(read, 0x8000000 + gamepak_size, 0xA000000);
3224 map_region(read, 0xA000000, 0xA000000 + gamepak_size, 1024, gamepak_rom);
3225 map_null(read, 0xA000000 + gamepak_size, 0xC000000);
3226 map_region(read, 0xC000000, 0xC000000 + gamepak_size, 1024, gamepak_rom);
3227 map_null(read, 0xC000000 + gamepak_size, 0xE000000);
3228 }
3229 }
3230
init_gamepak_buffer(void)3231 void init_gamepak_buffer(void)
3232 {
3233 // Try to initialize 32MB (this is mainly for non-PSP platforms)
3234 gamepak_rom = NULL;
3235
3236 gamepak_ram_buffer_size = 32 * 1024 * 1024;
3237 gamepak_rom = malloc(gamepak_ram_buffer_size);
3238
3239 if(!gamepak_rom)
3240 {
3241 // Try 16MB, for PSP, then lower in 2MB increments
3242 gamepak_ram_buffer_size = 16 * 1024 * 1024;
3243 gamepak_rom = malloc(gamepak_ram_buffer_size);
3244
3245 while(!gamepak_rom)
3246 {
3247 gamepak_ram_buffer_size -= (2 * 1024 * 1024);
3248 gamepak_rom = malloc(gamepak_ram_buffer_size);
3249 }
3250 }
3251
3252 // Here's assuming we'll have enough memory left over for this,
3253 // and that the above succeeded (if not we're in trouble all around)
3254 gamepak_ram_pages = gamepak_ram_buffer_size / (32 * 1024);
3255 gamepak_memory_map = malloc(sizeof(gamepak_swap_entry_type) *
3256 gamepak_ram_pages);
3257 }
3258
init_memory(void)3259 void init_memory(void)
3260 {
3261 u32 map_offset = 0;
3262
3263 memory_regions[0x00] = (u8 *)bios_rom;
3264 memory_regions[0x01] = (u8 *)bios_rom;
3265 memory_regions[0x02] = (u8 *)ewram;
3266 memory_regions[0x03] = (u8 *)iwram + 0x8000;
3267 memory_regions[0x04] = (u8 *)io_registers;
3268 memory_regions[0x05] = (u8 *)palette_ram;
3269 memory_regions[0x06] = (u8 *)vram;
3270 memory_regions[0x07] = (u8 *)oam_ram;
3271 memory_regions[0x08] = (u8 *)gamepak_rom;
3272 memory_regions[0x09] = (u8 *)(gamepak_rom + 0xFFFFFF);
3273 memory_regions[0x0A] = (u8 *)gamepak_rom;
3274 memory_regions[0x0B] = (u8 *)(gamepak_rom + 0xFFFFFF);
3275 memory_regions[0x0C] = (u8 *)gamepak_rom;
3276 memory_regions[0x0D] = (u8 *)(gamepak_rom + 0xFFFFFF);
3277 memory_regions[0x0E] = (u8 *)gamepak_backup;
3278
3279 memory_limits[0x00] = 0x3FFF;
3280 memory_limits[0x01] = 0x3FFF;
3281 memory_limits[0x02] = 0x3FFFF;
3282 memory_limits[0x03] = 0x7FFF;
3283 memory_limits[0x04] = 0x7FFF;
3284 memory_limits[0x05] = 0x3FF;
3285 memory_limits[0x06] = 0x17FFF;
3286 memory_limits[0x07] = 0x3FF;
3287 memory_limits[0x08] = 0x1FFFFFF;
3288 memory_limits[0x09] = 0x1FFFFFF;
3289 memory_limits[0x0A] = 0x1FFFFFF;
3290 memory_limits[0x0B] = 0x1FFFFFF;
3291 memory_limits[0x0C] = 0x1FFFFFF;
3292 memory_limits[0x0D] = 0x1FFFFFF;
3293 memory_limits[0x0E] = 0xFFFF;
3294
3295 // Fill memory map regions, areas marked as NULL must be checked directly
3296 map_region(read, 0x0000000, 0x1000000, 1, bios_rom);
3297 map_null(read, 0x1000000, 0x2000000);
3298 map_ram_region(read, 0x2000000, 0x3000000, 8, ewram);
3299 map_ram_region(read, 0x3000000, 0x4000000, 1, iwram);
3300 map_region(read, 0x4000000, 0x5000000, 1, io_registers);
3301 map_null(read, 0x5000000, 0x6000000);
3302 map_null(read, 0x6000000, 0x7000000);
3303 map_vram(read);
3304 map_null(read, 0x7000000, 0x8000000);
3305 init_memory_gamepak();
3306 map_null(read, 0xE000000, 0x10000000);
3307
3308 // Fill memory map regions, areas marked as NULL must be checked directly
3309 map_null(write, 0x0000000, 0x2000000);
3310 map_ram_region(write, 0x2000000, 0x3000000, 8, ewram);
3311 map_ram_region(write, 0x3000000, 0x4000000, 1, iwram);
3312 map_null(write, 0x4000000, 0x5000000);
3313 map_null(write, 0x5000000, 0x6000000);
3314
3315 // The problem here is that the current method of handling self-modifying code
3316 // requires writeable memory to be proceeded by 32KB SMC data areas or be
3317 // indirectly writeable. It's possible to get around this if you turn off the SMC
3318 // check altogether, but this will make a good number of ROMs crash (perhaps most
3319 // of the ones that actually need it? This has yet to be determined).
3320
3321 // This is because VRAM cannot be efficiently made incontiguous, and still allow
3322 // the renderer to work as efficiently. It would, at the very least, require a
3323 // lot of hacking of the renderer which I'm not prepared to do.
3324 // TODO(davidgfnet): add SMC VRAM detection
3325
3326 // However, it IS possible to directly map the first page no matter what because
3327 // there's 32kb of blank stuff sitting beneath it.
3328 if(direct_map_vram)
3329 {
3330 map_vram(write);
3331 }
3332 else
3333 {
3334 map_null(write, 0x6000000, 0x7000000);
3335 }
3336
3337 map_null(write, 0x7000000, 0x8000000);
3338 map_null(write, 0x8000000, 0xE000000);
3339 map_null(write, 0xE000000, 0x10000000);
3340
3341 memset(io_registers, 0, 0x8000);
3342 memset(oam_ram, 0, 0x400);
3343 memset(palette_ram, 0, 0x400);
3344 memset(iwram, 0, 0x10000);
3345 memset(ewram, 0, 0x80000);
3346 memset(vram, 0, 0x18000);
3347
3348 io_registers[REG_DISPCNT] = 0x80;
3349 io_registers[REG_P1] = 0x3FF;
3350 io_registers[REG_BG2PA] = 0x100;
3351 io_registers[REG_BG2PD] = 0x100;
3352 io_registers[REG_BG3PA] = 0x100;
3353 io_registers[REG_BG3PD] = 0x100;
3354 io_registers[REG_RCNT] = 0x8000;
3355
3356 backup_type = BACKUP_NONE;
3357
3358 sram_size = SRAM_SIZE_32KB;
3359 //flash_size = FLASH_SIZE_64KB;
3360
3361 flash_bank_ptr = gamepak_backup;
3362 flash_command_position = 0;
3363 eeprom_size = EEPROM_512_BYTE;
3364 eeprom_mode = EEPROM_BASE_MODE;
3365 eeprom_address = 0;
3366 eeprom_counter = 0;
3367
3368 flash_mode = FLASH_BASE_MODE;
3369
3370 rtc_state = RTC_DISABLED;
3371 memset(rtc_registers, 0, sizeof(rtc_registers));
3372 bios_read_protect = 0xe129f000;
3373 }
3374
memory_term(void)3375 void memory_term(void)
3376 {
3377 if (file_check_valid(gamepak_file_large))
3378 {
3379 file_close(gamepak_file_large);
3380 }
3381
3382 if (gamepak_memory_map)
3383 {
3384 free(gamepak_memory_map);
3385 gamepak_memory_map = NULL;
3386 }
3387
3388 if (gamepak_rom)
3389 {
3390 free(gamepak_rom);
3391 gamepak_rom = NULL;
3392 }
3393 }
3394
bios_region_read_allow(void)3395 void bios_region_read_allow(void)
3396 {
3397 memory_map_read[0] = bios_rom;
3398 }
3399
bios_region_read_protect(void)3400 void bios_region_read_protect(void)
3401 {
3402 memory_map_read[0] = NULL;
3403 }
3404
3405
3406 #define savestate_block(type) \
3407 cpu_##type##_savestate(); \
3408 input_##type##_savestate(); \
3409 main_##type##_savestate(); \
3410 memory_##type##_savestate(); \
3411 sound_##type##_savestate(); \
3412 video_##type##_savestate()
3413
3414
3415 const u8 *state_mem_read_ptr;
3416 u8 *state_mem_write_ptr;
3417
gba_load_state(const void * src)3418 void gba_load_state(const void* src)
3419 {
3420 u32 i;
3421 u32 current_color;
3422
3423 state_mem_read_ptr = src;
3424 savestate_block(read);
3425
3426 #ifdef HAVE_DYNAREC
3427 if (dynarec_enable)
3428 {
3429 flush_translation_cache_ram();
3430 flush_translation_cache_rom();
3431 flush_translation_cache_bios();
3432 }
3433 #endif
3434
3435 oam_update = 1;
3436 gbc_sound_update = 1;
3437
3438 for(i = 0; i < 512; i++)
3439 {
3440 current_color = palette_ram[i];
3441 palette_ram_converted[i] =
3442 convert_palette(current_color);
3443 }
3444
3445 // Oops, these contain raw pointers
3446 for(i = 0; i < 4; i++)
3447 gbc_sound_channel[i].sample_data = square_pattern_duty[2];
3448
3449 instruction_count = 0;
3450
3451 reg[CHANGED_PC_STATUS] = 1;
3452 }
3453
gba_save_state(void * dst)3454 void gba_save_state(void* dst)
3455 {
3456 state_mem_write_ptr = dst;
3457 savestate_block(write);
3458 }
3459
3460
3461 #define memory_savestate_builder(type) \
3462 void memory_##type##_savestate(void) \
3463 { \
3464 u32 i; \
3465 \
3466 state_mem_##type##_variable(backup_type); \
3467 state_mem_##type##_variable(sram_size); \
3468 state_mem_##type##_variable(flash_mode); \
3469 state_mem_##type##_variable(flash_command_position); \
3470 state_mem_##type##_variable(flash_bank_ptr); \
3471 state_mem_##type##_variable(flash_device_id); \
3472 state_mem_##type##_variable(flash_manufacturer_id); \
3473 state_mem_##type##_variable(flash_size); \
3474 state_mem_##type##_variable(eeprom_size); \
3475 state_mem_##type##_variable(eeprom_mode); \
3476 state_mem_##type##_variable(eeprom_address_length); \
3477 state_mem_##type##_variable(eeprom_address); \
3478 state_mem_##type##_variable(eeprom_counter); \
3479 state_mem_##type##_variable(rtc_state); \
3480 state_mem_##type##_variable(rtc_write_mode); \
3481 state_mem_##type##_array(rtc_registers); \
3482 state_mem_##type##_variable(rtc_command); \
3483 state_mem_##type##_array(rtc_data); \
3484 state_mem_##type##_variable(rtc_status); \
3485 state_mem_##type##_variable(rtc_data_bytes); \
3486 state_mem_##type##_variable(rtc_bit_count); \
3487 state_mem_##type##_array(eeprom_buffer); \
3488 state_mem_##type##_array(dma); \
3489 \
3490 state_mem_##type(iwram + 0x8000, 0x8000); \
3491 for(i = 0; i < 8; i++) \
3492 { \
3493 state_mem_##type(ewram + (i * 0x10000) + 0x8000, 0x8000); \
3494 } \
3495 state_mem_##type(vram, 0x18000); \
3496 state_mem_##type(oam_ram, 0x400); \
3497 state_mem_##type(palette_ram, 0x400); \
3498 state_mem_##type(io_registers, 0x8000); \
3499 \
3500 /* This is a hack, for now. */ \
3501 if((flash_bank_ptr < gamepak_backup) || \
3502 (flash_bank_ptr > (gamepak_backup + (1024 * 64)))) \
3503 flash_bank_ptr = gamepak_backup; \
3504 }
3505
3506 memory_savestate_builder(read)
3507 memory_savestate_builder(write)
3508
3509