1 /*
2 Interface routine for 68kem <-> Mame
3 */
4
5 #include "driver.h"
6 #include "mamedbg.h"
7 #include "m68000.h"
8 #include "state.h"
9
10 struct m68k_memory_interface a68k_memory_intf;
11
12 /* If we are only using assembler cores, we need to define these
13 * otherwise they are declared by the C core. */
14
15 #ifdef A68K0
16 #ifdef A68K2
17 int m68k_ICount;
18 struct m68k_memory_interface m68k_memory_intf;
19 #endif
20 #endif
21
22 enum
23 {
24 M68K_CPU_TYPE_INVALID,
25 M68K_CPU_TYPE_68000,
26 M68K_CPU_TYPE_68010,
27 M68K_CPU_TYPE_68EC020,
28 M68K_CPU_TYPE_68020,
29 M68K_CPU_TYPE_68030, /* Supported by disassembler ONLY */
30 M68K_CPU_TYPE_68040 /* Supported by disassembler ONLY */
31 };
32
33 #define A68K_SET_PC_CALLBACK(A) (*a68k_memory_intf.changepc)(A)
34
35 int illegal_op = 0 ;
36 int illegal_pc = 0 ;
37
38 #ifdef MAME_DEBUG
m68k_illegal_opcode(void)39 void m68k_illegal_opcode(void)
40 {
41 logerror("Illegal Opcode %4x at %8x\n",illegal_op,illegal_pc);
42 }
43 #endif
44
45 unsigned int m68k_disassemble(char* str_buff, unsigned int pc, unsigned int cpu_type);
46
47 #ifdef _WIN32
48 #define CONVENTION __cdecl
49 #else
50 #define CONVENTION
51 #endif
52
53 /* Use the x86 assembly core */
54 typedef struct
55 {
56 UINT32 d[8]; /* 0x0004 8 Data registers */
57 UINT32 a[8]; /* 0x0024 8 Address registers */
58
59 UINT32 isp; /* 0x0048 */
60
61 UINT32 sr_high; /* 0x004C System registers */
62 UINT32 ccr; /* 0x0050 CCR in Intel Format */
63 UINT32 x_carry; /* 0x0054 Extended Carry */
64
65 UINT32 pc; /* 0x0058 Program Counter */
66
67 UINT32 IRQ_level; /* 0x005C IRQ level you want the MC68K process (0=None) */
68
69 /* Backward compatible with C emulator - Only set in Debug compile */
70
71 UINT16 sr;
72 UINT16 filler;
73
74 int (*irq_callback)(int irqline);
75
76 UINT32 previous_pc; /* last PC used */
77
78 int (*reset_callback)(void);
79
80 UINT32 sfc; /* Source Function Code. (68010) */
81 UINT32 dfc; /* Destination Function Code. (68010) */
82 UINT32 usp; /* User Stack (All) */
83 UINT32 vbr; /* Vector Base Register. (68010) */
84
85 UINT32 BankID; /* Memory bank in use */
86 UINT32 CPUtype; /* CPU Type 0=68000,1=68010,2=68020 */
87 UINT32 FullPC;
88
89 struct m68k_memory_interface Memory_Interface;
90
91 } a68k_cpu_context;
92
93
94 static UINT8 M68K_layout[] = {
95 M68K_PC, M68K_ISP, -1,
96 M68K_SR, M68K_USP, -1,
97 M68K_D0, M68K_A0, -1,
98 M68K_D1, M68K_A1, -1,
99 M68K_D2, M68K_A2, -1,
100 M68K_D3, M68K_A3, -1,
101 M68K_D4, M68K_A4, -1,
102 M68K_D5, M68K_A5, -1,
103 M68K_D6, M68K_A6, -1,
104 M68K_D7, M68K_A7, 0
105 };
106
107 static UINT8 m68k_win_layout[] = {
108 48, 0,32,13, /* register window (top right) */
109 0, 0,47,13, /* disassembler window (top left) */
110 0,14,47, 8, /* memory #1 window (left, middle) */
111 48,14,32, 8, /* memory #2 window (right, middle) */
112 0,23,80, 1 /* command line window (bottom rows) */
113 };
114
115 #ifdef A68K0
116 extern a68k_cpu_context M68000_regs;
117
118 extern void CONVENTION M68000_RUN(void);
119 extern void CONVENTION M68000_RESET(void);
120
121 #endif
122
123 #ifdef A68K2
124 extern a68k_cpu_context M68020_regs;
125
126 extern void CONVENTION M68020_RUN(void);
127 extern void CONVENTION M68020_RESET(void);
128 #endif
129
130 /***************************************************************************/
131 /* Save State stuff */
132 /***************************************************************************/
133
134 static int IntelFlag[32] = {
135 0x0000,0x0001,0x0800,0x0801,0x0040,0x0041,0x0840,0x0841,
136 0x0080,0x0081,0x0880,0x0881,0x00C0,0x00C1,0x08C0,0x08C1,
137 0x0100,0x0101,0x0900,0x0901,0x0140,0x0141,0x0940,0x0941,
138 0x0180,0x0181,0x0980,0x0981,0x01C0,0x01C1,0x09C0,0x09C1
139 };
140
141
142 /* The assembler engine only keeps flags in intel format, so ... */
143
144 static UINT32 zero = 0;
145 static int stopped = 0;
146
a68k_prepare_substate(void)147 static void a68k_prepare_substate(void)
148 {
149 stopped = ((M68000_regs.IRQ_level & 0x80) != 0);
150
151 M68000_regs.sr = ((M68000_regs.ccr >> 4) & 0x1C)
152 | (M68000_regs.ccr & 0x01)
153 | ((M68000_regs.ccr >> 10) & 0x02)
154 | (M68000_regs.sr_high << 8);
155 }
156
a68k_post_load(void)157 static void a68k_post_load(void)
158 {
159 int intel = M68000_regs.sr & 0x1f;
160
161 M68000_regs.sr_high = M68000_regs.sr >> 8;
162 M68000_regs.x_carry = (IntelFlag[intel] >> 8) & 0x01;
163 M68000_regs.ccr = IntelFlag[intel] & 0x0EFF;
164 }
165
a68k_state_register(const char * type)166 void a68k_state_register(const char *type)
167 {
168 int cpu = cpu_getactivecpu();
169
170 state_save_register_UINT32(type, cpu, "D" , &M68000_regs.d[0], 8);
171 state_save_register_UINT32(type, cpu, "A" , &M68000_regs.a[0], 8);
172 state_save_register_UINT32(type, cpu, "PPC" , &M68000_regs.previous_pc, 1);
173 state_save_register_UINT32(type, cpu, "PC" , &M68000_regs.pc, 1);
174 state_save_register_UINT32(type, cpu, "USP" , &M68000_regs.usp, 1);
175 state_save_register_UINT32(type, cpu, "ISP" , &M68000_regs.isp, 1);
176 state_save_register_UINT32(type, cpu, "MSP" , &zero, 1);
177 state_save_register_UINT32(type, cpu, "VBR" , &M68000_regs.vbr, 1);
178 state_save_register_UINT32(type, cpu, "SFC" , &M68000_regs.sfc, 1);
179 state_save_register_UINT32(type, cpu, "DFC" , &M68000_regs.dfc, 1);
180 state_save_register_UINT32(type, cpu, "CACR" , &zero, 1);
181 state_save_register_UINT32(type, cpu, "CAAR" , &zero, 1);
182 state_save_register_UINT16(type, cpu, "SR" , &M68000_regs.sr, 1);
183 state_save_register_UINT32(type, cpu, "INT_LEVEL" , &M68000_regs.IRQ_level, 1);
184 state_save_register_UINT32(type, cpu, "INT_CYCLES", (UINT32 *)&m68k_ICount, 1);
185 state_save_register_int (type, cpu, "STOPPED" , &stopped);
186 state_save_register_int (type, cpu, "HALTED" , (int *)&zero);
187 state_save_register_UINT32(type, cpu, "PREF_ADDR" , &zero, 1);
188 state_save_register_UINT32(type, cpu, "PREF_DATA" , &zero, 1);
189 state_save_register_func_presave(a68k_prepare_substate);
190 state_save_register_func_postload(a68k_post_load);
191 }
192
193 /****************************************************************************
194 * 24-bit address, 16-bit data memory interface
195 ****************************************************************************/
196
197 #ifdef A68K0
198
readlong_a24_d16(offs_t address)199 static data32_t readlong_a24_d16(offs_t address)
200 {
201 data32_t result = cpu_readmem24bew_word(address) << 16;
202 return result | cpu_readmem24bew_word(address + 2);
203 }
204
writelong_a24_d16(offs_t address,data32_t data)205 static void writelong_a24_d16(offs_t address, data32_t data)
206 {
207 cpu_writemem24bew_word(address, data >> 16);
208 cpu_writemem24bew_word(address + 2, data);
209 }
210
changepc_a24_d16(offs_t pc)211 static void changepc_a24_d16(offs_t pc)
212 {
213 change_pc24bew(pc);
214 }
215
216 /* interface for 24-bit address bus, 16-bit data bus (68000, 68010) */
217 static const struct m68k_memory_interface interface_a24_d16 =
218 {
219 0,
220 cpu_readmem24bew,
221 cpu_readmem24bew_word,
222 readlong_a24_d16,
223 cpu_writemem24bew,
224 cpu_writemem24bew_word,
225 writelong_a24_d16,
226 changepc_a24_d16,
227 cpu_readmem24bew, /* Encrypted Versions */
228 cpu_readmem24bew_word,
229 readlong_a24_d16,
230 cpu_readmem24bew_word,
231 readlong_a24_d16
232 };
233
234 #endif /* A68k0 */
235
236 /****************************************************************************
237 * 24-bit address, 32-bit data memory interface
238 ****************************************************************************/
239
240 #ifdef A68K2
241
242 /* potentially misaligned 16-bit reads with a 32-bit data bus (and 24-bit address bus) */
readword_a24_d32(offs_t address)243 static data16_t readword_a24_d32(offs_t address)
244 {
245 data16_t result;
246
247 if (!(address & 1))
248 return cpu_readmem24bedw_word(address);
249 result = cpu_readmem24bedw(address) << 8;
250 return result | cpu_readmem24bedw(address + 1);
251 }
252
253 /* potentially misaligned 16-bit writes with a 32-bit data bus (and 24-bit address bus) */
writeword_a24_d32(offs_t address,data16_t data)254 static void writeword_a24_d32(offs_t address, data16_t data)
255 {
256 if (!(address & 1))
257 {
258 cpu_writemem24bedw_word(address, data);
259 return;
260 }
261 cpu_writemem24bedw(address, data >> 8);
262 cpu_writemem24bedw(address + 1, data);
263 }
264
265 /* potentially misaligned 32-bit reads with a 32-bit data bus (and 24-bit address bus) */
readlong_a24_d32(offs_t address)266 static data32_t readlong_a24_d32(offs_t address)
267 {
268 data32_t result;
269
270 if (!(address & 3))
271 return cpu_readmem24bedw_dword(address);
272 else if (!(address & 1))
273 {
274 result = cpu_readmem24bedw_word(address) << 16;
275 return result | cpu_readmem24bedw_word(address + 2);
276 }
277 result = cpu_readmem24bedw(address) << 24;
278 result |= cpu_readmem24bedw_word(address + 1) << 8;
279 return result | cpu_readmem24bedw(address + 3);
280 }
281
282 /* potentially misaligned 32-bit writes with a 32-bit data bus (and 24-bit address bus) */
writelong_a24_d32(offs_t address,data32_t data)283 static void writelong_a24_d32(offs_t address, data32_t data)
284 {
285 if (!(address & 3))
286 {
287 cpu_writemem24bedw_dword(address, data);
288 return;
289 }
290 else if (!(address & 1))
291 {
292 cpu_writemem24bedw_word(address, data >> 16);
293 cpu_writemem24bedw_word(address + 2, data);
294 return;
295 }
296 cpu_writemem24bedw(address, data >> 24);
297 cpu_writemem24bedw_word(address + 1, data >> 8);
298 cpu_writemem24bedw(address + 3, data);
299 }
300
changepc_a24_d32(offs_t pc)301 static void changepc_a24_d32(offs_t pc)
302 {
303 change_pc24bedw(pc);
304 }
305
306 /* interface for 24-bit address bus, 32-bit data bus (68EC020) */
307 static const struct m68k_memory_interface interface_a24_d32 =
308 {
309 WORD_XOR_BE(0),
310 cpu_readmem24bedw,
311 readword_a24_d32,
312 readlong_a24_d32,
313 cpu_writemem24bedw,
314 writeword_a24_d32,
315 writelong_a24_d32,
316 changepc_a24_d32,
317 cpu_readmem24bedw,
318 readword_a24_d32,
319 readlong_a24_d32,
320 readword_a24_d32,
321 readlong_a24_d32
322 };
323
324
325 /****************************************************************************
326 * 32-bit address, 32-bit data memory interface
327 ****************************************************************************/
328
329 /* potentially misaligned 16-bit reads with a 32-bit data bus (and 32-bit address bus) */
readword_a32_d32(offs_t address)330 static data16_t readword_a32_d32(offs_t address)
331 {
332 data16_t result;
333
334 if (!(address & 1))
335 return cpu_readmem32bedw_word(address);
336 result = cpu_readmem32bedw(address) << 8;
337 return result | cpu_readmem32bedw(address + 1);
338 }
339
340 /* potentially misaligned 16-bit writes with a 32-bit data bus (and 32-bit address bus) */
writeword_a32_d32(offs_t address,data16_t data)341 static void writeword_a32_d32(offs_t address, data16_t data)
342 {
343 if (!(address & 1))
344 {
345 cpu_writemem32bedw_word(address, data);
346 return;
347 }
348 cpu_writemem32bedw(address, data >> 8);
349 cpu_writemem32bedw(address + 1, data);
350 }
351
352 /* potentially misaligned 32-bit reads with a 32-bit data bus (and 32-bit address bus) */
readlong_a32_d32(offs_t address)353 static data32_t readlong_a32_d32(offs_t address)
354 {
355 data32_t result;
356
357 if (!(address & 3))
358 return cpu_readmem32bedw_dword(address);
359 else if (!(address & 1))
360 {
361 result = cpu_readmem32bedw_word(address) << 16;
362 return result | cpu_readmem32bedw_word(address + 2);
363 }
364 result = cpu_readmem32bedw(address) << 24;
365 result |= cpu_readmem32bedw_word(address + 1) << 8;
366 return result | cpu_readmem32bedw(address + 3);
367 }
368
369 /* potentially misaligned 32-bit writes with a 32-bit data bus (and 32-bit address bus) */
writelong_a32_d32(offs_t address,data32_t data)370 static void writelong_a32_d32(offs_t address, data32_t data)
371 {
372 if (!(address & 3))
373 {
374 cpu_writemem32bedw_dword(address, data);
375 return;
376 }
377 else if (!(address & 1))
378 {
379 cpu_writemem32bedw_word(address, data >> 16);
380 cpu_writemem32bedw_word(address + 2, data);
381 return;
382 }
383 cpu_writemem32bedw(address, data >> 24);
384 cpu_writemem32bedw_word(address + 1, data >> 8);
385 cpu_writemem32bedw(address + 3, data);
386 }
387
changepc_a32_d32(offs_t pc)388 static void changepc_a32_d32(offs_t pc)
389 {
390 change_pc32bedw(pc);
391 }
392
393 /* interface for 24-bit address bus, 32-bit data bus (68020) */
394 static const struct m68k_memory_interface interface_a32_d32 =
395 {
396 WORD_XOR_BE(0),
397 cpu_readmem32bedw,
398 readword_a32_d32,
399 readlong_a32_d32,
400 cpu_writemem32bedw,
401 writeword_a32_d32,
402 writelong_a32_d32,
403 changepc_a32_d32,
404 cpu_readmem32bedw,
405 readword_a32_d32,
406 readlong_a32_d32,
407 readword_a32_d32,
408 readlong_a32_d32
409 };
410
411 #endif /* A68K2 */
412
413 /********************************************/
414 /* Interface routines to link Mame -> 68KEM */
415 /********************************************/
416
417 #define READOP(a) (cpu_readop16((a) ^ a68k_memory_intf.opcode_xor))
418
419 #ifdef A68K0
420
m68000_init(void)421 void m68000_init(void)
422 {
423 a68k_state_register("m68000");
424 M68000_regs.reset_callback = 0;
425 }
426
m68k16_reset_common(void)427 static void m68k16_reset_common(void)
428 {
429 int (*rc)(void);
430
431 rc = M68000_regs.reset_callback;
432 memset(&M68000_regs,0,sizeof(M68000_regs));
433 M68000_regs.reset_callback = rc;
434
435 M68000_regs.a[7] = M68000_regs.isp = (( READOP(0) << 16 ) | READOP(2));
436 M68000_regs.pc = (( READOP(4) << 16 ) | READOP(6)) & 0xffffff;
437 M68000_regs.sr_high = 0x27;
438
439 #ifdef MAME_DEBUG
440 M68000_regs.sr = 0x2700;
441 #endif
442
443 M68000_RESET();
444 }
445
m68000_reset(void * param)446 void m68000_reset(void *param)
447 {
448 struct m68k_encryption_interface *interface = param;
449
450 /* Default Memory Routines */
451 if (a68k_memory_intf.read8 != cpu_readmem24bew)
452 a68k_memory_intf = interface_a24_d16;
453
454 /* Import encryption routines if present */
455 if (param)
456 {
457 a68k_memory_intf.read8pc = interface->read8pc;
458 a68k_memory_intf.read16pc = interface->read16pc;
459 a68k_memory_intf.read32pc = interface->read32pc;
460 a68k_memory_intf.read16d = interface->read16d;
461 a68k_memory_intf.read32d = interface->read32d;
462 }
463
464 m68k16_reset_common();
465 M68000_regs.Memory_Interface = a68k_memory_intf;
466 }
467
m68000_exit(void)468 void m68000_exit(void)
469 {
470 /* nothing to do ? */
471 }
472
473
474 #ifdef TRACE68K /* Trace */
475 static int skiptrace=0;
476 #endif
477
m68000_execute(int cycles)478 int m68000_execute(int cycles)
479 {
480 if (M68000_regs.IRQ_level == 0x80) return cycles; /* STOP with no IRQs */
481
482 m68k_ICount = cycles;
483
484 #ifdef MAME_DEBUG
485 do
486 {
487 if (mame_debug)
488 {
489 #ifdef TRACE68K
490
491 int StartCycle = m68k_ICount;
492
493 skiptrace++;
494
495 if (skiptrace > 0)
496 {
497 int mycount, areg, dreg;
498
499 areg = dreg = 0;
500 for (mycount=7;mycount>=0;mycount--)
501 {
502 areg = areg + M68000_regs.a[mycount];
503 dreg = dreg + M68000_regs.d[mycount];
504 }
505
506 logerror("=> %8x %8x ",areg,dreg);
507 logerror("%6x %4x %d\n",M68000_regs.pc,M68000_regs.sr & 0x271F,m68k_ICount);
508 }
509 #endif
510
511 #if 0
512 m68k_memory_intf = a68k_memory_intf;
513 #endif
514 MAME_Debug();
515 M68000_RUN();
516
517 #ifdef TRACE68K
518 if ((M68000_regs.IRQ_level & 0x80) || (cpu_getstatus(cpu_getactivecpu()) == 0))
519 m68k_ICount = 0;
520 else
521 m68k_ICount = StartCycle - 12;
522 #endif
523 }
524 else
525 M68000_RUN();
526
527 } while (m68k_ICount > 0);
528
529 #else
530
531 M68000_RUN();
532
533 #endif /* MAME_DEBUG */
534
535 return (cycles - m68k_ICount);
536 }
537
538
m68000_get_context(void * dst)539 unsigned m68000_get_context(void *dst)
540 {
541 if( dst )
542 *(a68k_cpu_context*)dst = M68000_regs;
543 return sizeof(a68k_cpu_context);
544 }
545
m68000_set_context(void * src)546 void m68000_set_context(void *src)
547 {
548 if( src )
549 {
550 M68000_regs = *(a68k_cpu_context*)src;
551 a68k_memory_intf = M68000_regs.Memory_Interface;
552 }
553 }
554
m68000_get_reg(int regnum)555 unsigned m68000_get_reg(int regnum)
556 {
557 switch( regnum )
558 {
559 case REG_PC:
560 case M68K_PC: return M68000_regs.pc;
561 case REG_SP:
562 case M68K_ISP: return M68000_regs.isp;
563 case M68K_USP: return M68000_regs.usp;
564 case M68K_SR: return M68000_regs.sr;
565 case M68K_VBR: return M68000_regs.vbr;
566 case M68K_SFC: return M68000_regs.sfc;
567 case M68K_DFC: return M68000_regs.dfc;
568 case M68K_D0: return M68000_regs.d[0];
569 case M68K_D1: return M68000_regs.d[1];
570 case M68K_D2: return M68000_regs.d[2];
571 case M68K_D3: return M68000_regs.d[3];
572 case M68K_D4: return M68000_regs.d[4];
573 case M68K_D5: return M68000_regs.d[5];
574 case M68K_D6: return M68000_regs.d[6];
575 case M68K_D7: return M68000_regs.d[7];
576 case M68K_A0: return M68000_regs.a[0];
577 case M68K_A1: return M68000_regs.a[1];
578 case M68K_A2: return M68000_regs.a[2];
579 case M68K_A3: return M68000_regs.a[3];
580 case M68K_A4: return M68000_regs.a[4];
581 case M68K_A5: return M68000_regs.a[5];
582 case M68K_A6: return M68000_regs.a[6];
583 case M68K_A7: return M68000_regs.a[7];
584 case REG_PREVIOUSPC: return M68000_regs.previous_pc;
585 /* TODO: Verify that this is the right thing to do for the purpose? */
586 default:
587 if( regnum <= REG_SP_CONTENTS )
588 {
589 unsigned offset = M68000_regs.isp + 4 * (REG_SP_CONTENTS - regnum);
590 if( offset < 0xfffffd )
591 return (*a68k_memory_intf.read32)( offset );
592 }
593 }
594 return 0;
595 }
596
m68000_set_reg(int regnum,unsigned val)597 void m68000_set_reg(int regnum, unsigned val)
598 {
599 switch( regnum )
600 {
601 case REG_PC:
602 case M68K_PC: M68000_regs.pc = val; break;
603 case REG_SP:
604 case M68K_ISP: M68000_regs.isp = val; break;
605 case M68K_USP: M68000_regs.usp = val; break;
606 case M68K_SR: M68000_regs.sr = val; break;
607 case M68K_VBR: M68000_regs.vbr = val; break;
608 case M68K_SFC: M68000_regs.sfc = val; break;
609 case M68K_DFC: M68000_regs.dfc = val; break;
610 case M68K_D0: M68000_regs.d[0] = val; break;
611 case M68K_D1: M68000_regs.d[1] = val; break;
612 case M68K_D2: M68000_regs.d[2] = val; break;
613 case M68K_D3: M68000_regs.d[3] = val; break;
614 case M68K_D4: M68000_regs.d[4] = val; break;
615 case M68K_D5: M68000_regs.d[5] = val; break;
616 case M68K_D6: M68000_regs.d[6] = val; break;
617 case M68K_D7: M68000_regs.d[7] = val; break;
618 case M68K_A0: M68000_regs.a[0] = val; break;
619 case M68K_A1: M68000_regs.a[1] = val; break;
620 case M68K_A2: M68000_regs.a[2] = val; break;
621 case M68K_A3: M68000_regs.a[3] = val; break;
622 case M68K_A4: M68000_regs.a[4] = val; break;
623 case M68K_A5: M68000_regs.a[5] = val; break;
624 case M68K_A6: M68000_regs.a[6] = val; break;
625 case M68K_A7: M68000_regs.a[7] = val; break;
626 /* TODO: Verify that this is the right thing to do for the purpose? */
627 default:
628 if( regnum <= REG_SP_CONTENTS )
629 {
630 unsigned offset = M68000_regs.isp + 4 * (REG_SP_CONTENTS - regnum);
631 if( offset < 0xfffffd )
632 (*a68k_memory_intf.write32)( offset, val );
633 }
634 }
635 }
636
m68k_assert_irq(int int_line)637 void m68k_assert_irq(int int_line)
638 {
639 /* Save icount */
640 int StartCount = m68k_ICount;
641
642 M68000_regs.IRQ_level = int_line;
643
644 /* Now check for Interrupt */
645
646 m68k_ICount = -1;
647 M68000_RUN();
648
649 /* Restore Count */
650 m68k_ICount = StartCount;
651 }
652
m68k_clear_irq(int int_line)653 void m68k_clear_irq(int int_line)
654 {
655 M68000_regs.IRQ_level = 0;
656 }
657
m68000_set_irq_line(int irqline,int state)658 void m68000_set_irq_line(int irqline, int state)
659 {
660 if (irqline == IRQ_LINE_NMI)
661 irqline = 7;
662 switch(state)
663 {
664 case CLEAR_LINE:
665 m68k_clear_irq(irqline);
666 return;
667 case ASSERT_LINE:
668 m68k_assert_irq(irqline);
669 return;
670 default:
671 m68k_assert_irq(irqline);
672 return;
673 }
674 }
675
m68000_set_irq_callback(int (* callback)(int irqline))676 void m68000_set_irq_callback(int (*callback)(int irqline))
677 {
678 M68000_regs.irq_callback = callback;
679 }
680
m68000_set_reset_callback(int (* callback)(void))681 void m68000_set_reset_callback(int (*callback)(void))
682 {
683 M68000_regs.reset_callback = callback;
684 }
685
686 /****************************************************************************
687 * Return a formatted string for a register
688 ****************************************************************************/
m68000_info(void * context,int regnum)689 const char *m68000_info(void *context, int regnum)
690 {
691 #ifdef MAME_DEBUG
692 extern int m68k_disassemble(char* str_buff, int pc, int cputype);
693 #endif
694
695 static char buffer[32][47+1];
696 static int which;
697 a68k_cpu_context *r = context;
698
699 which = (which+1) % 32;
700 buffer[which][0] = '\0';
701 if( !context )
702 r = &M68000_regs;
703
704 switch( regnum )
705 {
706 case CPU_INFO_REG+M68K_PC: sprintf(buffer[which], "PC:%06X", r->pc); break;
707 case CPU_INFO_REG+M68K_ISP: sprintf(buffer[which], "ISP:%08X", r->isp); break;
708 case CPU_INFO_REG+M68K_USP: sprintf(buffer[which], "USP:%08X", r->usp); break;
709 case CPU_INFO_REG+M68K_SR: sprintf(buffer[which], "SR:%08X", r->sr); break;
710 case CPU_INFO_REG+M68K_VBR: sprintf(buffer[which], "VBR:%08X", r->vbr); break;
711 case CPU_INFO_REG+M68K_SFC: sprintf(buffer[which], "SFC:%08X", r->sfc); break;
712 case CPU_INFO_REG+M68K_DFC: sprintf(buffer[which], "DFC:%08X", r->dfc); break;
713 case CPU_INFO_REG+M68K_D0: sprintf(buffer[which], "D0:%08X", r->d[0]); break;
714 case CPU_INFO_REG+M68K_D1: sprintf(buffer[which], "D1:%08X", r->d[1]); break;
715 case CPU_INFO_REG+M68K_D2: sprintf(buffer[which], "D2:%08X", r->d[2]); break;
716 case CPU_INFO_REG+M68K_D3: sprintf(buffer[which], "D3:%08X", r->d[3]); break;
717 case CPU_INFO_REG+M68K_D4: sprintf(buffer[which], "D4:%08X", r->d[4]); break;
718 case CPU_INFO_REG+M68K_D5: sprintf(buffer[which], "D5:%08X", r->d[5]); break;
719 case CPU_INFO_REG+M68K_D6: sprintf(buffer[which], "D6:%08X", r->d[6]); break;
720 case CPU_INFO_REG+M68K_D7: sprintf(buffer[which], "D7:%08X", r->d[7]); break;
721 case CPU_INFO_REG+M68K_A0: sprintf(buffer[which], "A0:%08X", r->a[0]); break;
722 case CPU_INFO_REG+M68K_A1: sprintf(buffer[which], "A1:%08X", r->a[1]); break;
723 case CPU_INFO_REG+M68K_A2: sprintf(buffer[which], "A2:%08X", r->a[2]); break;
724 case CPU_INFO_REG+M68K_A3: sprintf(buffer[which], "A3:%08X", r->a[3]); break;
725 case CPU_INFO_REG+M68K_A4: sprintf(buffer[which], "A4:%08X", r->a[4]); break;
726 case CPU_INFO_REG+M68K_A5: sprintf(buffer[which], "A5:%08X", r->a[5]); break;
727 case CPU_INFO_REG+M68K_A6: sprintf(buffer[which], "A6:%08X", r->a[6]); break;
728 case CPU_INFO_REG+M68K_A7: sprintf(buffer[which], "A7:%08X", r->a[7]); break;
729 case CPU_INFO_FLAGS:
730 sprintf(buffer[which], "%c%c%c%c%c%c%c%c%c%c%c%c%c%c%c%c",
731 r->sr & 0x8000 ? 'T':'.',
732 r->sr & 0x4000 ? '?':'.',
733 r->sr & 0x2000 ? 'S':'.',
734 r->sr & 0x1000 ? '?':'.',
735 r->sr & 0x0800 ? '?':'.',
736 r->sr & 0x0400 ? 'I':'.',
737 r->sr & 0x0200 ? 'I':'.',
738 r->sr & 0x0100 ? 'I':'.',
739 r->sr & 0x0080 ? '?':'.',
740 r->sr & 0x0040 ? '?':'.',
741 r->sr & 0x0020 ? '?':'.',
742 r->sr & 0x0010 ? 'X':'.',
743 r->sr & 0x0008 ? 'N':'.',
744 r->sr & 0x0004 ? 'Z':'.',
745 r->sr & 0x0002 ? 'V':'.',
746 r->sr & 0x0001 ? 'C':'.');
747 break;
748 case CPU_INFO_NAME: return "68000";
749 case CPU_INFO_FAMILY: return "Motorola 68K";
750 case CPU_INFO_VERSION: return "0.16";
751 case CPU_INFO_FILE: return __FILE__;
752 case CPU_INFO_CREDITS: return "Copyright 1998,99 Mike Coates, Darren Olafson. All rights reserved";
753 case CPU_INFO_REG_LAYOUT: return (const char*)M68K_layout;
754 case CPU_INFO_WIN_LAYOUT: return (const char*)m68k_win_layout;
755 }
756 return buffer[which];
757 }
758
m68000_dasm(char * buffer,unsigned pc)759 unsigned m68000_dasm(char *buffer, unsigned pc)
760 {
761 A68K_SET_PC_CALLBACK(pc);
762
763 #ifdef MAME_DEBUG
764 m68k_memory_intf = a68k_memory_intf;
765 return m68k_disassemble(buffer, pc, M68K_CPU_TYPE_68000);
766 #else
767 sprintf(buffer, "$%04X", cpu_readop16(pc) );
768 return 2;
769 #endif
770 }
771
772 /****************************************************************************
773 * M68010 section
774 ****************************************************************************/
775
776 #if (HAS_M68010)
777
m68010_reset(void * param)778 void m68010_reset(void *param)
779 {
780 if (a68k_memory_intf.read8 != cpu_readmem24bew)
781 a68k_memory_intf = interface_a24_d16;
782
783 m68k16_reset_common();
784
785 M68000_regs.CPUtype=1;
786 M68000_regs.Memory_Interface = a68k_memory_intf;
787 }
788
m68010_init(void)789 void m68010_init(void) { m68000_init(); }
m68010_exit(void)790 void m68010_exit(void) { m68000_exit(); }
m68010_execute(int cycles)791 int m68010_execute(int cycles) { return m68000_execute(cycles); }
m68010_get_context(void * dst)792 unsigned m68010_get_context(void *dst) { return m68000_get_context(dst); }
793
m68010_set_context(void * src)794 void m68010_set_context(void *src)
795 {
796 if( src )
797 {
798 M68000_regs = *(a68k_cpu_context*)src;
799 a68k_memory_intf = M68000_regs.Memory_Interface;
800 }
801 }
802
m68010_get_reg(int regnum)803 unsigned m68010_get_reg(int regnum) { return m68000_get_reg(regnum); }
m68010_set_reg(int regnum,unsigned val)804 void m68010_set_reg(int regnum, unsigned val) { m68000_set_reg(regnum,val); }
m68010_set_irq_line(int irqline,int state)805 void m68010_set_irq_line(int irqline, int state) { m68000_set_irq_line(irqline,state); }
m68010_set_irq_callback(int (* callback)(int irqline))806 void m68010_set_irq_callback(int (*callback)(int irqline)) { m68000_set_irq_callback(callback); }
807
m68010_info(void * context,int regnum)808 const char *m68010_info(void *context, int regnum)
809 {
810 switch( regnum )
811 {
812 case CPU_INFO_NAME: return "68010";
813 }
814 return m68000_info(context,regnum);
815 }
816
m68010_dasm(char * buffer,unsigned pc)817 unsigned m68010_dasm(char *buffer, unsigned pc)
818 {
819 A68K_SET_PC_CALLBACK(pc);
820
821 #ifdef MAME_DEBUG
822 m68k_memory_intf = a68k_memory_intf;
823 return m68k_disassemble(buffer, pc, M68K_CPU_TYPE_68010);
824 #else
825 sprintf(buffer, "$%04X", cpu_readop16(pc) );
826 return 2;
827 #endif
828 }
829 #endif
830
831
832 #endif /* A68K0 */
833
834
835 /****************************************************************************
836 * M68020 section
837 ****************************************************************************/
838
839 #ifdef A68K2
840
m68020_init(void)841 void m68020_init(void)
842 {
843 a68k_state_register("m68020");
844 M68020_regs.reset_callback = 0;
845 }
846
m68k32_reset_common(void)847 static void m68k32_reset_common(void)
848 {
849 int (*rc)(void);
850
851 rc = M68020_regs.reset_callback;
852 memset(&M68020_regs,0,sizeof(M68020_regs));
853 M68020_regs.reset_callback = rc;
854
855 M68020_regs.a[7] = M68020_regs.isp = (( READOP(0) << 16 ) | READOP(2));
856 M68020_regs.pc = (( READOP(4) << 16 ) | READOP(6)) & 0xffffff;
857 M68020_regs.sr_high = 0x27;
858
859 #ifdef MAME_DEBUG
860 M68020_regs.sr = 0x2700;
861 #endif
862
863 M68020_RESET();
864 }
865
866 #if (HAS_M68020)
867
m68020_reset(void * param)868 void m68020_reset(void *param)
869 {
870 if (a68k_memory_intf.read8 != cpu_readmem32bedw)
871 a68k_memory_intf = interface_a32_d32;
872
873 m68k32_reset_common();
874
875 M68020_regs.CPUtype=2;
876 M68020_regs.Memory_Interface = a68k_memory_intf;
877 }
878
m68020_exit(void)879 void m68020_exit(void)
880 {
881 /* nothing to do ? */
882 }
883
m68020_execute(int cycles)884 int m68020_execute(int cycles)
885 {
886 if (M68020_regs.IRQ_level == 0x80) return cycles; /* STOP with no IRQs */
887
888 m68k_ICount = cycles;
889
890 #ifdef MAME_DEBUG
891 do
892 {
893 if (mame_debug)
894 {
895 #ifdef TRACE68K
896
897 int StartCycle = m68k_ICount;
898
899 skiptrace++;
900
901 if (skiptrace > 0)
902 {
903 int mycount, areg, dreg;
904
905 areg = dreg = 0;
906 for (mycount=7;mycount>=0;mycount--)
907 {
908 areg = areg + M68020_regs.a[mycount];
909 dreg = dreg + M68020_regs.d[mycount];
910 }
911
912 logerror("=> %8x %8x ",areg,dreg);
913 logerror("%6x %4x %d\n",M68020_regs.pc,M68020_regs.sr & 0x271F,m68k_ICount);
914 }
915 #endif
916
917 #if 0
918 m68k_memory_intf = a68k_memory_intf;
919 #endif
920 MAME_Debug();
921 M68020_RUN();
922
923 #ifdef TRACE68K
924 if ((M68020_regs.IRQ_level & 0x80) || (cpu_getstatus(cpu_getactivecpu()) == 0))
925 m68k_ICount = 0;
926 else
927 m68k_ICount = StartCycle - 12;
928 #endif
929 }
930 else
931 M68020_RUN();
932
933 } while (m68k_ICount > 0);
934
935 #else
936
937 M68020_RUN();
938
939 #endif /* MAME_DEBUG */
940
941 return (cycles - m68k_ICount);
942 }
943
m68020_get_context(void * dst)944 unsigned m68020_get_context(void *dst)
945 {
946 if( dst )
947 *(a68k_cpu_context*)dst = M68020_regs;
948 return sizeof(a68k_cpu_context);
949 }
950
m68020_set_context(void * src)951 void m68020_set_context(void *src)
952 {
953 if( src )
954 {
955 M68020_regs = *(a68k_cpu_context*)src;
956 a68k_memory_intf = M68020_regs.Memory_Interface;
957 }
958 }
959
m68020_get_reg(int regnum)960 unsigned m68020_get_reg(int regnum)
961 {
962 switch( regnum )
963 {
964 case REG_PC:
965 case M68K_PC: return M68020_regs.pc;
966 case REG_SP:
967 case M68K_ISP: return M68020_regs.isp;
968 case M68K_USP: return M68020_regs.usp;
969 case M68K_SR: return M68020_regs.sr;
970 case M68K_VBR: return M68020_regs.vbr;
971 case M68K_SFC: return M68020_regs.sfc;
972 case M68K_DFC: return M68020_regs.dfc;
973 case M68K_D0: return M68020_regs.d[0];
974 case M68K_D1: return M68020_regs.d[1];
975 case M68K_D2: return M68020_regs.d[2];
976 case M68K_D3: return M68020_regs.d[3];
977 case M68K_D4: return M68020_regs.d[4];
978 case M68K_D5: return M68020_regs.d[5];
979 case M68K_D6: return M68020_regs.d[6];
980 case M68K_D7: return M68020_regs.d[7];
981 case M68K_A0: return M68020_regs.a[0];
982 case M68K_A1: return M68020_regs.a[1];
983 case M68K_A2: return M68020_regs.a[2];
984 case M68K_A3: return M68020_regs.a[3];
985 case M68K_A4: return M68020_regs.a[4];
986 case M68K_A5: return M68020_regs.a[5];
987 case M68K_A6: return M68020_regs.a[6];
988 case M68K_A7: return M68020_regs.a[7];
989 case REG_PREVIOUSPC: return M68020_regs.previous_pc;
990 /* TODO: Verify that this is the right thing to do for the purpose? */
991 default:
992 if( regnum <= REG_SP_CONTENTS )
993 {
994 unsigned offset = M68020_regs.isp + 4 * (REG_SP_CONTENTS - regnum);
995 if( offset < 0xfffffd )
996 return (*a68k_memory_intf.read32)( offset );
997 }
998 }
999 return 0;
1000 }
1001
m68020_set_reg(int regnum,unsigned val)1002 void m68020_set_reg(int regnum, unsigned val)
1003 {
1004 switch( regnum )
1005 {
1006 case REG_PC:
1007 case M68K_PC: M68020_regs.pc = val; break;
1008 case REG_SP:
1009 case M68K_ISP: M68020_regs.isp = val; break;
1010 case M68K_USP: M68020_regs.usp = val; break;
1011 case M68K_SR: M68020_regs.sr = val; break;
1012 case M68K_VBR: M68020_regs.vbr = val; break;
1013 case M68K_SFC: M68020_regs.sfc = val; break;
1014 case M68K_DFC: M68020_regs.dfc = val; break;
1015 case M68K_D0: M68020_regs.d[0] = val; break;
1016 case M68K_D1: M68020_regs.d[1] = val; break;
1017 case M68K_D2: M68020_regs.d[2] = val; break;
1018 case M68K_D3: M68020_regs.d[3] = val; break;
1019 case M68K_D4: M68020_regs.d[4] = val; break;
1020 case M68K_D5: M68020_regs.d[5] = val; break;
1021 case M68K_D6: M68020_regs.d[6] = val; break;
1022 case M68K_D7: M68020_regs.d[7] = val; break;
1023 case M68K_A0: M68020_regs.a[0] = val; break;
1024 case M68K_A1: M68020_regs.a[1] = val; break;
1025 case M68K_A2: M68020_regs.a[2] = val; break;
1026 case M68K_A3: M68020_regs.a[3] = val; break;
1027 case M68K_A4: M68020_regs.a[4] = val; break;
1028 case M68K_A5: M68020_regs.a[5] = val; break;
1029 case M68K_A6: M68020_regs.a[6] = val; break;
1030 case M68K_A7: M68020_regs.a[7] = val; break;
1031 /* TODO: Verify that this is the right thing to do for the purpose? */
1032 default:
1033 if( regnum <= REG_SP_CONTENTS )
1034 {
1035 unsigned offset = M68020_regs.isp + 4 * (REG_SP_CONTENTS - regnum);
1036 if( offset < 0xfffffd )
1037 (*a68k_memory_intf.write32)( offset, val );
1038 }
1039 }
1040 }
1041
m68020_assert_irq(int int_line)1042 void m68020_assert_irq(int int_line)
1043 {
1044 /* Save icount */
1045 int StartCount = m68k_ICount;
1046
1047 M68020_regs.IRQ_level = int_line;
1048
1049 /* Now check for Interrupt */
1050
1051 m68k_ICount = -1;
1052 M68020_RUN();
1053
1054 /* Restore Count */
1055 m68k_ICount = StartCount;
1056 }
1057
m68020_clear_irq(int int_line)1058 void m68020_clear_irq(int int_line)
1059 {
1060 M68020_regs.IRQ_level = 0;
1061 }
1062
m68020_set_irq_line(int irqline,int state)1063 void m68020_set_irq_line(int irqline, int state)
1064 {
1065 if (irqline == IRQ_LINE_NMI)
1066 irqline = 7;
1067 switch(state)
1068 {
1069 case CLEAR_LINE:
1070 m68020_clear_irq(irqline);
1071 return;
1072 case ASSERT_LINE:
1073 m68020_assert_irq(irqline);
1074 return;
1075 default:
1076 m68020_assert_irq(irqline);
1077 return;
1078 }
1079 }
1080
m68020_set_irq_callback(int (* callback)(int irqline))1081 void m68020_set_irq_callback(int (*callback)(int irqline))
1082 {
1083 M68020_regs.irq_callback = callback;
1084 }
1085
m68020_set_reset_callback(int (* callback)(void))1086 void m68020_set_reset_callback(int (*callback)(void))
1087 {
1088 M68020_regs.reset_callback = callback;
1089 }
1090
m68020_info(void * context,int regnum)1091 const char *m68020_info(void *context, int regnum)
1092 {
1093 #ifdef MAME_DEBUG
1094 extern int m68k_disassemble(char* str_buff, int pc, int cputype);
1095 #endif
1096
1097 static char buffer[32][47+1];
1098 static int which;
1099 a68k_cpu_context *r = context;
1100
1101 which = (which + 1) % 32;
1102 buffer[which][0] = '\0';
1103 if( !context )
1104 r = &M68020_regs;
1105
1106 switch( regnum )
1107 {
1108 case CPU_INFO_REG+M68K_PC: sprintf(buffer[which], "PC:%06X", r->pc); break;
1109 case CPU_INFO_REG+M68K_ISP: sprintf(buffer[which], "ISP:%08X", r->isp); break;
1110 case CPU_INFO_REG+M68K_USP: sprintf(buffer[which], "USP:%08X", r->usp); break;
1111 case CPU_INFO_REG+M68K_SR: sprintf(buffer[which], "SR:%08X", r->sr); break;
1112 case CPU_INFO_REG+M68K_VBR: sprintf(buffer[which], "VBR:%08X", r->vbr); break;
1113 case CPU_INFO_REG+M68K_SFC: sprintf(buffer[which], "SFC:%08X", r->sfc); break;
1114 case CPU_INFO_REG+M68K_DFC: sprintf(buffer[which], "DFC:%08X", r->dfc); break;
1115 case CPU_INFO_REG+M68K_D0: sprintf(buffer[which], "D0:%08X", r->d[0]); break;
1116 case CPU_INFO_REG+M68K_D1: sprintf(buffer[which], "D1:%08X", r->d[1]); break;
1117 case CPU_INFO_REG+M68K_D2: sprintf(buffer[which], "D2:%08X", r->d[2]); break;
1118 case CPU_INFO_REG+M68K_D3: sprintf(buffer[which], "D3:%08X", r->d[3]); break;
1119 case CPU_INFO_REG+M68K_D4: sprintf(buffer[which], "D4:%08X", r->d[4]); break;
1120 case CPU_INFO_REG+M68K_D5: sprintf(buffer[which], "D5:%08X", r->d[5]); break;
1121 case CPU_INFO_REG+M68K_D6: sprintf(buffer[which], "D6:%08X", r->d[6]); break;
1122 case CPU_INFO_REG+M68K_D7: sprintf(buffer[which], "D7:%08X", r->d[7]); break;
1123 case CPU_INFO_REG+M68K_A0: sprintf(buffer[which], "A0:%08X", r->a[0]); break;
1124 case CPU_INFO_REG+M68K_A1: sprintf(buffer[which], "A1:%08X", r->a[1]); break;
1125 case CPU_INFO_REG+M68K_A2: sprintf(buffer[which], "A2:%08X", r->a[2]); break;
1126 case CPU_INFO_REG+M68K_A3: sprintf(buffer[which], "A3:%08X", r->a[3]); break;
1127 case CPU_INFO_REG+M68K_A4: sprintf(buffer[which], "A4:%08X", r->a[4]); break;
1128 case CPU_INFO_REG+M68K_A5: sprintf(buffer[which], "A5:%08X", r->a[5]); break;
1129 case CPU_INFO_REG+M68K_A6: sprintf(buffer[which], "A6:%08X", r->a[6]); break;
1130 case CPU_INFO_REG+M68K_A7: sprintf(buffer[which], "A7:%08X", r->a[7]); break;
1131 case CPU_INFO_FLAGS:
1132 sprintf(buffer[which], "%c%c%c%c%c%c%c%c%c%c%c%c%c%c%c%c",
1133 r->sr & 0x8000 ? 'T':'.',
1134 r->sr & 0x4000 ? '?':'.',
1135 r->sr & 0x2000 ? 'S':'.',
1136 r->sr & 0x1000 ? '?':'.',
1137 r->sr & 0x0800 ? '?':'.',
1138 r->sr & 0x0400 ? 'I':'.',
1139 r->sr & 0x0200 ? 'I':'.',
1140 r->sr & 0x0100 ? 'I':'.',
1141 r->sr & 0x0080 ? '?':'.',
1142 r->sr & 0x0040 ? '?':'.',
1143 r->sr & 0x0020 ? '?':'.',
1144 r->sr & 0x0010 ? 'X':'.',
1145 r->sr & 0x0008 ? 'N':'.',
1146 r->sr & 0x0004 ? 'Z':'.',
1147 r->sr & 0x0002 ? 'V':'.',
1148 r->sr & 0x0001 ? 'C':'.');
1149 break;
1150 case CPU_INFO_NAME: return "68020";
1151 case CPU_INFO_FAMILY: return "Motorola 68K";
1152 case CPU_INFO_VERSION: return "0.16";
1153 case CPU_INFO_FILE: return __FILE__;
1154 case CPU_INFO_CREDITS: return "Copyright 1998,99 Mike Coates, Darren Olafson. All rights reserved";
1155 case CPU_INFO_REG_LAYOUT: return (const char*)M68K_layout;
1156 case CPU_INFO_WIN_LAYOUT: return (const char*)m68k_win_layout;
1157 }
1158 return buffer[which];
1159 }
1160
m68020_dasm(char * buffer,unsigned pc)1161 unsigned m68020_dasm(char *buffer, unsigned pc)
1162 {
1163 A68K_SET_PC_CALLBACK(pc);
1164
1165 #ifdef MAME_DEBUG
1166 m68k_memory_intf = a68k_memory_intf;
1167 return m68k_disassemble(buffer, pc, M68K_CPU_TYPE_68020);
1168 #else
1169 sprintf(buffer, "$%04X", cpu_readop16(pc) );
1170 return 2;
1171 #endif
1172 }
1173 #endif
1174
1175 #if (HAS_M68EC020)
1176
m68ec020_reset(void * param)1177 void m68ec020_reset(void *param)
1178 {
1179 if (a68k_memory_intf.read8 != cpu_readmem24bedw)
1180 a68k_memory_intf = interface_a24_d32;
1181
1182 m68k32_reset_common();
1183
1184 M68020_regs.CPUtype=2;
1185 M68020_regs.Memory_Interface = a68k_memory_intf;
1186 }
1187
m68ec020_init(void)1188 void m68ec020_init(void) { m68020_init(); }
m68ec020_exit(void)1189 void m68ec020_exit(void) { m68020_exit(); }
m68ec020_execute(int cycles)1190 int m68ec020_execute(int cycles) { return m68020_execute(cycles); }
m68ec020_get_context(void * dst)1191 unsigned m68ec020_get_context(void *dst) { return m68020_get_context(dst); }
1192
m68ec020_set_context(void * src)1193 void m68ec020_set_context(void *src)
1194 {
1195 if( src )
1196 {
1197 M68020_regs = *(a68k_cpu_context*)src;
1198 a68k_memory_intf = M68020_regs.Memory_Interface;
1199 }
1200 }
1201
m68ec020_get_reg(int regnum)1202 unsigned m68ec020_get_reg(int regnum) { return m68020_get_reg(regnum); }
m68ec020_set_reg(int regnum,unsigned val)1203 void m68ec020_set_reg(int regnum, unsigned val) { m68020_set_reg(regnum,val); }
m68ec020_set_irq_line(int irqline,int state)1204 void m68ec020_set_irq_line(int irqline, int state) { m68020_set_irq_line(irqline,state); }
m68ec020_set_irq_callback(int (* callback)(int irqline))1205 void m68ec020_set_irq_callback(int (*callback)(int irqline)) { m68020_set_irq_callback(callback); }
1206
m68ec020_info(void * context,int regnum)1207 const char *m68ec020_info(void *context, int regnum)
1208 {
1209 switch( regnum )
1210 {
1211 case CPU_INFO_NAME: return "68EC020";
1212 }
1213 return m68020_info(context,regnum);
1214 }
1215
m68ec020_dasm(char * buffer,unsigned pc)1216 unsigned m68ec020_dasm(char *buffer, unsigned pc)
1217 {
1218 A68K_SET_PC_CALLBACK(pc);
1219
1220 #ifdef MAME_DEBUG
1221 m68k_memory_intf = a68k_memory_intf;
1222 return m68k_disassemble(buffer, pc, M68K_CPU_TYPE_68EC020);
1223 #else
1224 sprintf(buffer, "$%04X", cpu_readop16(pc) );
1225 return 2;
1226 #endif
1227 }
1228
1229 #endif
1230
1231 #endif /* A68K2 */
1232